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Functional Description
Table 4-1. BCSR/FLASH Hard Reset Configuration Word
Data
Bus
Bits
Prog
Value
[Bin]
L2CPC
8:9
‘10’
CI/BADDR(29)/IRQ2 selected as BADDR(29)
WT/BADDR(30)/IRQ3 selected as BADDR(30)
L2_HIT/IRQ4 selected as unassigned
CPU_BG/BADDR(31)/IRQ5 as BADDR(31)
DPPC
10:11
‘11’
Data Parity Pin configuration as:
DP0 as EXT_BR2
DP1 as EXT_BG2
DP2 as EXT_DBG2
DP3 as EXT_BR3
DP4 as EXT_BG3
DP5 as EXT_DBG3
DP6 as IRQ6
DP7 as IRQ7
12
’0’
Reserved.
ISB
13:15
’010’
BMS
16
’0’
Boot memory (Flash) at 0xFE000000.
BBD
17
’0’
ABB/IRQ2 pin is ABB
DBB/IRQ3 pin is DBB
MMR
18:19
’11’/’00’
‘11’ - Mask Masters Requests. Boot Master is
PCI when PCI is enabled in the FLASH.
‘00’ - No masking, Local Bus SDRAM mode in
the BCSR.
LBPC
20:21
’01’/’00’
‘11’ - Local Bus pins function as PCI bus
(FLASH).
‘00’ - Local Bus pins function as Local Bus
(BCSR).
APPC
22:23
’10’
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Field
Reserved
MOTOROLA
Implication
Offset In
Flash
[Hex]
Value
[Hex]
8
B2
10
36 / 02b
IMMR initial value 0x0F000000, i.e., the
internal space resides initially at this address.
MODCK1/AP(1)/TC(0) functions as BKSEL0
MODCK2/AP(2)/TC(1) functions as BKSEL1
MODCK3/AP(3)/TC(2) functions as BKSEL2
IRQ7~/APE~ functions as IRQ7~
CS11~/AP(0) functions as CS11~
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