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eZ80190 Development Kit
User Manual
PRELIMINARY
UM014103-0803
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
eZ80190 Development Kit
User Manual
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.zilog.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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User Manual
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Safeguards
The following precautions must be observed when working with the
devices described in this document.
Caution: Always use a grounding strap to prevent damage resulting from
electrostatic discharge (ESD).
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PRELIMINARY
Safeguards
eZ80190 Development Kit
User Manual
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Table of Contents
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Hardware Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
eZ80® Development Platform Overview . . . . . . . . . . . . . . . . . . . . . . . . 2
eZ80® Development Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
eZ80190 Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I/O Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Embedded Modem Socket Interface . . . . . . . . . . . . . . . . . . . . . . . 28
eZ80® Development Platform Memory . . . . . . . . . . . . . . . . . . . . . 31
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I2C Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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eZ80190 Development Kit
User Manual
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Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . .
eZ80190 Module Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus Software Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Loader Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mounting the Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing the Power Supply Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZPAK II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZDI Target Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZPAK II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZDS II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZDS II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cannot Download Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
No Output on Console Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IrDA Port Not Working . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Difference Between EMAC and IP Address . . . . . . . . . . . . . . . . . . . . .
Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IP Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting ZiLOG Customer Support . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ80® Development Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Array Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U10 Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
PRELIMINARY
48
50
50
51
51
51
52
52
52
54
54
54
54
55
56
56
57
57
57
57
58
58
58
59
60
61
61
66
74
74
74
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U15 Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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User Manual
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Table of Contents
PRELIMINARY
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List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
UM014103-0803
eZ80® Development Platform Block Diagram with
eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
The eZ80® Development Platform . . . . . . . . . . . . . . . . . . . 5
The eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Basic eZ80® Development Platform Block Diagram . . . . . 8
Physical Dimensions of the eZ80® Development Platform 9
eZ80® Development Platform Peripheral Bus Connector
Pin Configuration—JP1 . . . . . . . . . . . . . . . . . . . . . . . . . . 11
eZ80® Development Platform I/O Connector Pin
Configuration—JP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trigger Pins J21 and J22 . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Embedded Modem Socket Interface—J1, J5, and J9 . . . . 29
Memory Map of the eZ80® Development Platform and
eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Physical Dimensions of the eZ80190 Module . . . . . . . . . 45
eZ80190 Module—Top Layer . . . . . . . . . . . . . . . . . . . . . 46
eZ80190 Module—Bottom Layer . . . . . . . . . . . . . . . . . . . 47
9VDC Universal Power Supply Components . . . . . . . . . . 52
Inserting a New Plug Configuration . . . . . . . . . . . . . . . . . 53
eZ80® Development Platform Schematic Diagram,
#1 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
eZ80® Development Platform Schematic Diagram,
#2 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
eZ80® Development Platform Schematic Diagram,
#3 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
eZ80® Development Platform Schematic Diagram,
#4 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PRELIMINARY
List of Figures
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User Manual
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Figure 20. eZ80® Development Platform Schematic Diagram,
#5 of 5—RS-485 Cable . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21. eZ80190 Module Schematic Diagram, #1 of 8—CPU . . .
Figure 22. eZ80190 Module Schematic Diagram, #2 of 8—
36-Pin SRAM Device . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23. eZ80190 Module Schematic Diagram, #3 of 8—
NOR Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24. eZ80190 Module Schematic Diagram, #4 of 8—
Ethernet Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25. eZ80190 Module Schematic Diagram, #5 of 8—
Ethernet Module Logic . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26. eZ80190 Module Schematic Diagram, #6 of 8—
Ethernet Module Peripherals . . . . . . . . . . . . . . . . . . . . . . .
Figure 27. eZ80190 Module Schematic Diagram, #7 of 8—Headers .
Figure 28. eZ80190 Module Schematic Diagram, #8 of 8—
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures
PRELIMINARY
65
66
67
68
69
70
71
72
73
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List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
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eZ80® Development Platform Hardware Specifications . . 2
eZ80® Development Platform Peripheral Bus Connector
Identification—JP11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
eZ80® Development Platform I/O Connector
Identification—JP21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
GPIO Port Connector J6 . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CPU Bus Connector J8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LED and Port Emulation Addresses . . . . . . . . . . . . . . . . . 24
LED Anode/General-Purpose Port Output Control
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General-Purpose Port Data Register . . . . . . . . . . . . . . . . . 25
Bit Access to the LED Cathode, Modem, and Triggers . . 26
Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Connector J9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
J3—DIS_EM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
J7—FlashWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
J11—DIS_FL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
J12—5VDC/3.3VDC for an Embedded Modem . . . . . . . 36
J14—RI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
J15—RS485_1_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
J16—RS485_2_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
J17—RT_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
J18—RT_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
J19—EX_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
J20—EX_FL_DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PRELIMINARY
List of Tables
eZ80190 Development Kit
User Manual
xii
Table 24.
Table 25.
Table 26.
List of Tables
I2C Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Current Characteristics of the eZ80® Development
Platform with Different Module Loads . . . . . . . . . . . . . . . 42
Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . 48
PRELIMINARY
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Introduction
The eZ80190 Development Kit provides a general-purpose platform for
evaluating the capabilities and operation of ZiLOG’s eZ80190 microprocessor. The eZ80F91 Development Kit features two primary boards: the
eZ80® Development Platform and the eZ80190 Module. This arrangement provides a full development platform when using both boards. It can
also provide a smaller-sized reference platform with the eZ80190 Module
as a stand-alone development tool.
Kit Features
The key features of the eZ80190 Development Kit are:
•
eZ80® Development Platform:
– Up to 2 MB fast SRAM (12 ns access time)
– Embedded Modem Socket with a U.S. Telephone Line Interface
– I2C EEPROM
– I2C Configuration Register
– GPIO Port and Memory Headers
– LEDs, including a 7 x 5 LED matrix
– Jumpers
– Two RS232 connectors—Console, Modem
– 9 VDC Power Connector
– RS485 connector1
– JTAG Debug Interface1
– ZiLOG Debug Interface (ZDI)
– ZiLOG Developer Studio II and the eZ80® C-Compiler
1. The eZ80® Development Platform’s RS485 and JTAG functions are not supported on the
eZ80190 device.
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Kit Features
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User Manual
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•
eZ80190 Module:
– eZ80190 device operating at 50 MHz
– 1 MB Flash Memory
– 512 KB SRAM
– 10 BaseT Ethernet Interface
– Real-Time Clock with Battery Back-Up
•
•
•
ZPAK II Debug Interface Tool
4-port 10 BaseT Ethernet hub
eZ80® Software and Documentation CD-ROM
Hardware Specifications
Table 1 lists the specifications of the eZ80® Development Platform.
Table 1. eZ80® Development Platform
Hardware Specifications
Operating Temperature: 20ºC ±5ºC
Operating Voltage:
9 VDC
eZ80® Development Platform Overview
The purpose of the eZ80190 Development Kit is to provide the developer
with a set of tools for evaluating the features of the eZ80® family of
devices, and to be able to develop a new application before building application hardware. The eZ80® Development Platform is designed to accept
a number of application-specific modules and eZ80®-based add-on modules, including the eZ80190 Module, which features an Ethernet MAC, a
Real-Time Clock, and the eZ80190 microprocessor with a fast MultiplyAccumulate unit.
Introduction
PRELIMINARY
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When attached to the eZ80® Development Platform, the eZ80190 Module
can operate in stand-alone mode with Flash memory, or interface via the
ZPAK II debug interface tool to a host PC running ZiLOG Developer Studio II Integrated Development Environment (ZDS IDE) software. If the
user’s eZ80® application demands Internet connectivity and/or a network
connection, the eZ80190 microprocessor can serve web pages over a
TCP/IP network, allowing easy system monitoring and control, and
effortless processor code updates.
The address bus, data bus, and all eZ80190 Module control signals are
buffered on the eZ80® Development Platform to provide sufficient drive
capability.
A block diagram of the eZ80® Development Platform and the eZ80190
Module is shown in Figure 1.
UM014103-0803
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eZ80® Development Platform Overview
eZ80190 Development Kit
User Manual
4
GPIO
eZ80190
Address Bus
Data Bus
Peripheral Device Signals
®
eZ80
Ethermet
Module
Interface
Address Bus
Data Bus
RS232-0
(Console)
EMAC
SRAM
(512 KB
up to 2 MB)
RS485
RS232-1
(Modem)
Flash
(1 MB)
Embedded
Modem
SRAM
(512 KB)
LED
(7x5 matrix)
Pushbuttons
RTC with
Battery
eZ80190
Module
GPIO
and
Address
Decoder
I2C
EEPROM
I2C
Register
Application Module Headers
Figure 1. eZ80® Development Platform Block Diagram
with eZ80190 Module
Introduction
PRELIMINARY
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Figure 2 is a photographic representation of the eZ80® Development Platform segmented into its key blocks, as shown in the legend for the figure.
C
A
B
D
E
Key to blocks A–E:
A. Power and serial communications.
B. eZ80190 Module interface.
C. Debug interface.
D. Application module interfaces.
E. General-Purpose Port and LED with address
decoder.
Figure 2. The eZ80® Development Platform
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eZ80® Development Platform Overview
eZ80190 Development Kit
User Manual
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Figure 3 is a photographic representation of the eZ80190 Module segmented into its key blocks, as shown in the legend for the figure.
A
D
C
B
A
Note: Key to blocks A–D.
A. eZ80190 Module interfaces.
B. eZ80190 CPU.
C. 10/100 BaseT Ethernet Interface
D. IrDA transceiver.
Figure 3. The eZ80190 Module
The structures of the eZ80® Development Platform and the eZ80190
Module are illustrated in the Schematic Diagrams starting on page 61.
Introduction
PRELIMINARY
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eZ80® Development Platform
This section describes the eZ80® Development Platform hardware, its key
components and its interfaces, including detailed programmer interface
information such as memory maps, register definitions, and interrupt
usage.
Functional Description
The eZ80® Development Platform consists of seven major hardware
blocks. These blocks, listed below, are diagrammed in Figure 4.
•
•
eZ80190 Module interface (2 male headers)
•
•
•
•
•
Application Module interface (2 female headers)
UM014103-0803
Power supply for the eZ80® Development Platform, the eZ80190
Module, and application modules
General-Purpose Port and LED matrix
RS232 serial communications ports
Embedded modem interface
I2C devices
PRELIMINARY
Functional Description
eZ80190 Development Kit
User Manual
8
Peripheral Device Signals
Address Bus
eZ80
Module
Interface
Data Bus
SRAM
(512 KB
up to 2 MB)
RS232-0
(Console)
RS232-1
(Modem)
Embedded
Modem
LED
(7x5 matrix)
Pushbuttons
GPIO
and
Address
Decoder
I2C
EEPROM
I2C
Register
Application Module Headers
Figure 4. Basic eZ80® Development Platform Block Diagram
eZ80® Development Platform
PRELIMINARY
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Physical Dimensions
The dimensions of the eZ80® Development Platform PCB is 177.8 mm
x 182.9 mm. The overall height is 38.1 mm. See Figure 5.
175.3 mm
43.2 mm
114.3 mm
96.5 mm
55.9 mm
157.5 mm
167.6 mm
5.1 mm
165.1 mm
5.1 mm
Figure 5. Physical Dimensions of the eZ80® Development Platform
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Functional Description
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User Manual
10
Operational Description
The eZ80® Development Platform can accept any eZ80®-core-based
modules, provided that the module interfaces correctly to the eZ80®
Development Platform. The purpose of the eZ80® Development Platform
is to provide the application developer with a tool to evaluate the features
of the eZ80190 device and to develop an application without building
additional hardware.
eZ80190 Module Interface
The eZ80190 Module interface provides easy an connection for the
eZ80190 Module. This interface is designed to fit future eZ80® modules
and user-developed modules using current eZ80® devices.
The eZ80190 Module interface consists of two 50-pin receptacles, JP1
and JP2, which are described in the next pages.
Peripheral Bus Connector (JP1)
Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the
50-pin header, located at position JP1 on the eZ80® Development Platform. Table 2 describes the pins and their functions.
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JP1
A6
A10
GND_EXT
A8
A13
A15
A18
A19
A2
A11
A4
A5
DIS_ETH
A21
A22
CS0
CS2
D1
D3
D5
D7
MREQ
GND_EXT
WR
BUSACK
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
A0
A3
V3.3_EXT
A7
A9
A14
A1 6
GND_EXT
A1
A12
A20
A17
DIS_FLASH
V3.3_EXT
A23
CS1
D0
D2
D4
GND_EXT
D6
IOREQ
RD
INSTRD
BUSREQ
HEADER 25X2
IDC50
Figure 6. eZ80® Development Platform
Peripheral Bus Connector Pin Configuration—JP1
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Table 2. eZ80® Development Platform
Peripheral Bus Connector Identification—JP11
Signal Direction
Active Level
eZ801900100ZCO
Signal2
Pin #
Symbol
1
A6
Bidirectional
Yes
2
A0
Bidirectional
Yes
3
A10
Bidirectional
Yes
4
A3
Bidirectional
Yes
5
GND
6
VDD
7
A8
Bidirectional
Yes
8
A7
Bidirectional
Yes
9
A13
Bidirectional
Yes
10
A9
Bidirectional
Yes
11
A15
Bidirectional
Yes
12
A14
Bidirectional
Yes
13
A18
Bidirectional
Yes
14
A16
Bidirectional
Yes
15
A19
Bidirectional
Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should
be below 10 pF to satisfy the timing requirements for the eZ80® CPU. All unused inputs should be
pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.
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Table 2. eZ80® Development Platform
Peripheral Bus Connector Identification—JP11 (Continued)
Signal Direction
Active Level
eZ801900100ZCO
Signal2
Pin #
Symbol
16
GND
17
A2
Bidirectional
Yes
18
A1
Bidirectional
Yes
19
A11
Bidirectional
Yes
20
A12
Bidirectional
Yes
21
A4
Bidirectional
Yes
22
A20
Bidirectional
Yes
23
A5
Bidirectional
Yes
24
A17
Bidirectional
Yes
25
DIS_ETH
Output
Low
No
26
DIS_FLASH
Output
Low
No
27
A21
28
VDD
29
30
Bidirectional
Yes
A22
Bidirectional
Yes
A23
Bidirectional
Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should
be below 10 pF to satisfy the timing requirements for the eZ80® CPU. All unused inputs should be
pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.
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Table 2. eZ80® Development Platform
Peripheral Bus Connector Identification—JP11 (Continued)
Signal Direction
Active Level
eZ801900100ZCO
Signal2
CS0
Input
Low
Yes
32
CS1
Input
Low
Yes
33
CS2
Input
Low
Yes
34
D0
Bidirectional
Yes
35
D1
Bidirectional
Yes
36
D2
Bidirectional
No
37
D3
Bidirectional
Yes
38
D4
Bidirectional
Yes
39
D5
Bidirectional
Yes
40
GND
41
D7
Bidirectional
Yes
42
D6
Bidirectional
Yes
43
MREQ
Bidirectional
Low
Yes
44
IORQ
Bidirectional
Low
Yes
45
GND
Pin #
Symbol
31
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should
be below 10 pF to satisfy the timing requirements for the eZ80® CPU. All unused inputs should be
pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.
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Table 2. eZ80® Development Platform
Peripheral Bus Connector Identification—JP11 (Continued)
Signal Direction
Active Level
eZ801900100ZCO
Signal2
RD
Bidirectional
Low
Yes
47
WR
Bidirectional
Low
Yes
48
INSTRD
Input
Low
Yes
49
BUSACK
Input
Pull-Up 10 KΩ; Low
Yes
50
BUSREQ
Output
Pull-Up 10 KΩ; Low
Yes
Pin #
Symbol
46
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should
be below 10 pF to satisfy the timing requirements for the eZ80® CPU. All unused inputs should be
pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.
I/O Connector (JP2)
Figure 7 illustrates the pin layout of the eZ80® Development Platform’s I/O
Connector in the 50-pin header. The I/O Connector is located at position
JP2 on the eZ80® Development Platform. Table 3 describes the pins and
their functions.
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JP2
PB7
PB5
PB3
PB1
GND_EXT
PC6
PC4
PC2
PC0
PD6
PD5
PD3
PD1
TDO
GND_EXT
TCK
RTC_VDD
IICSCL
IICSDA
FLASHWE
CS3
RESET
V3.3_EXT
HALT_SLP
V3.3_EXT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
PB6
PB4
PB2
PB0
PC7
PC5
PC3
PC1
PD7
GND_EXT
PD4
PD2
PD0
TDI
TRIGOUT
TMS
EZ80CLK
GND_EXT
DIS_IRDA
WAIT
GND_EXT
NMI
HEADER 25X2
IDC50
Figure 7. eZ80® Development Platform
I/O Connector Pin Configuration—JP2
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Table 3. eZ80® Development Platform
I/O Connector Identification—JP21
Signal Direction
Active Level
eZ80F91 Signal2
Pin #
Symbol
1
PB7
Bidirectional
Yes
2
PB6
Bidirectional
Yes
3
PB5
Bidirectional
Yes
4
PB4
Bidirectional
Yes
5
PB3
Bidirectional
Yes
6
PB2
Bidirectional
Yes
7
PB1
Bidirectional
Yes
8
PB0
Bidirectional
Yes
9
GND
10
PC7
Bidirectional
Yes
11
PC6
Bidirectional
Yes
12
PC5
Bidirectional
Yes
13
PC4
Bidirectional
Yes
14
PC3
Bidirectional
Yes
15
PC2
Bidirectional
Yes
16
PC1
Bidirectional
Yes
17
PC0
Bidirectional
Yes
18
PD7
Bidirectional
Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
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Table 3. eZ80® Development Platform
I/O Connector Identification—JP21 (Continued)
Signal Direction
Active Level
eZ80F91 Signal2
Pin #
Symbol
19
PD6
20
GND
21
PD5
Bidirectional
Yes
22
PD4
Bidirectional
Yes
23
PD3
Bidirectional
Yes
24
PD2
Bidirectional
Yes
25
PD1
Bidirectional
Yes
26
PD0
Bidirectional
Yes
27
TDO
Input
Yes
28
TDI/ZDA
Output
Yes
29
GND
30
TRIGOUT
Input
31
TCK/ZCL
Output
32
TMS
Output
33
RTC_VDD
34
EZ80CLK
35
SCL
36
GND
Bidirectional
High
Yes
High
Yes
Input
Yes
Bidirectional
Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
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Table 3. eZ80® Development Platform
I/O Connector Identification—JP21 (Continued)
Pin #
Symbol
37
SDA
38
GND
39
FlashWE
40
GND
41
CS3
42
DIS_IrDA
43
RESET
44
WAIT
45
VDD
46
GND
47
HALT_SLP
48
NMI
49
VDD
50
Reserved
Signal Direction
Active Level
Bidirectional
eZ80F91 Signal2
Yes
Output
Low
No
Input
Low
Yes
Output
Low
No
Bidirectional
Low
Yes
Output
Pull-Up 10 KΩ; Low
Yes
Input
Low
Yes
Output
Low
Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams on
pages 66 through 73.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
Almost all of the connectors’ signals are received directly from the CPU.
Four input signals, in particular, offer options to the application developer
by disabling certain functions of the eZ80190 Module.
These four inputs are:
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•
•
•
•
Disable Ethernet (DIS_ETH)
Disable Flash (DIS_FL)
Flash Write Enable (FlashWE)
Disable IrDA (DIS_IrDA—not used)
These four signals are described below.
Disable Ethernet
When active Low, the DIS_ETH output signal disables the EMAC from
responding to CPU requests. As a result, additional input/output or memory devices can be used in the CS3 address space. The logic that disables
the Ethernet signal is listed in Appendix A on page 74.
Disable Flash
When active Low, the DIS_FL input signal disables the Flash chip on the
eZ80190 Module.
Flash Write Enable
When active Low, the FlashWE input signal enables Write operations on
the Flash boot block of the eZ80190 Module.
Disable IrDA
This signal does not perform a function on the eZ80190 Module. UART0
is always used with the RS232 interface on the eZ80® Development Platform.
Application Module Interface
An Application Module Interface is provided to allow the user to add an
application-specific module to the eZ80® Development Platform. ZiLOG’s
Thermostat Application Module (not provided in the kit) is an example
application-specific module that demonstrates an HVAC control system.
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To design an application module, the user should be familiar with the
architecture and features of the eZ80190 Module currently installed.
Implementing an application module via the Application Module Interface
requires that the eZ80190 Module also be mounted on the eZ80® Development Platform, because it (the eZ80190 Module) contains the eZ80190
microprocessor. To mount an application module, use the two male connectors J6 and J8.
Connector J6 carries the GPIO signals, and connector J8 carries memory
and control signals. Tables 4 and 5 list the signals and functions related to
each of these jumpers by pin. Power and ground signals are omitted for
the sake of simplicity.
Table 4. GPIO Port Connector J6*
Signal
Pin #
Function
Direction
SCL
5
I2C
Bidirectional
SDA
7
I2C Data
Bidirectional
MOD_DIS
9
Modem Disable
Input
If a shunt is installed between
pins 6 and 9, the modem
function on the eZ80®
Development Platform is
disabled.
MWAIT
13
WAIT signal for
the CPU
Input
This signal does not perform a
function on the eZ80190
Module.
EM_D0
15
GPIO, Bit 0
Bidirectional
CS3
17
Chip Select 3 of
the CPU
Output
EM_D[7:1]
21,23,25, Port A, Bit [7:1]
27,29,31,
33
Clock
Notes
This signal is also present on
the J8.
Bidirectional
Note: *All of the signals are driven directly by the CPU.
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Table 4. GPIO Port Connector J6* (Continued)
Signal
Pin #
Function
Direction
Reserved
35
PC[7:0]
39,41,43, Port C, Bit [7:0]
45,47,49,
51,53
ID_[2:0]
6,8,10
eZ80®
Development
Platform ID
Output
CON_DIS
12
Console Disable
Input
Reserved
16,18
PD[7:0]
22,24,26, Port D, Bit[7:0]
28,30,32,
34,36
Bidirectional
PB[7:0]
40,42,44, Port B, Bit[7:0]
46,48,50,
52,54
Bidirectional
Notes
Bidirectional
If a shunt is installed between
pins 12 and 14, the Console
function on the eZ80®
Development Platform is
disabled.
Note: *All of the signals are driven directly by the CPU.
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Table 5. CPU Bus Connector J8*
Signal
Pin #
Function
Direction
A[0:7]
3–10
Address Bus, Low Byte
Output
A[8:15]
13–20
Address Bus, High Byte
Output
A[16:23]
23–30
Address Bus, Upper Byte
Output
RD
33
Read Signal
Output
RESET
35
Push Button Reset
Output
BUSACK
37
CPU Bus Acknowledge Signal
Output
NMI
39
Nonmaskable Interrupt
Input
D[0:7]
43–50
Data Bus
Bidirectional
CS[0:3]
53–56
Chip Selects
Output
MREQ
57
Memory Request
Output
WR
34
Write Signal
Output
INSTRD
36
Instruction Fetch
Output
BUSREQ
38
CPU Bus Request signal
Input
PHY
40
Clock output of the CPU
Output
Note: *All of the signals except BUSACK and INSTRD are driven by lowvoltage CMOS technology (LVC) drivers.
I/O Functionality
The eZ80® Development Platform provides additional functionality, featuring general-purpose port, an LED matrix, a modem reset, and two user triggers. These functions are memory-mapped with an address decoder based
on the Generic Array Logic GAL22lV10D (U15) device manufactured by
Lattice Semiconductor, and a bidirectional latch (U16). Additionally, U15 is
used to decode addresses for access to the 7 x 5 LED matrix.
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Table 6 lists the memory map addresses to registers that allow access to the
above functions. The register at address 800000h controls general-purpose port output control and LED anode register functions. The register at
address 800001h controls the register functions for the LED cathode,
modem reset, and user triggers. Address 800002h controls general-purpose port data.
Table 6. LED and Port Emulation Addresses
Address
Register Function
Access
800000h
LED Anode/General-Purpose Port
Output Control
WR
800001h
LED Cathode/Modem/Trig
WR
800002h
General-Purpose Port Data
RD/WR
General-Purpose Port
The general-purpose port is emulated with the use of the GPIO Output
Control Register and the GPIO Data Register. If bit 7 in the GPIO Output
Control Register is 1, all of the lines on the general-purpose port are configured as inputs. If this bit is 0, all of the lines on the general-purpose
port are configured as outputs. Table 7 lists the multiple functions of the
register.
Table 7. LED Anode/General-Purpose Port Output Control Register
Bit #
Function
7
6
5
4
3
2
1
Anode Col 1
X
Anode Col 2
X
Anode Col 3
Anode Col 4
eZ80® Development Platform
0
X
X
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Table 7. LED Anode/General-Purpose Port Output Control Register (Continued)
Bit #
Function
7
6
5
Anode Col 5
3
2
1
0
X
Anode Col 6
X
Anode Col 6
GPIO Output
4
X
X
The GPIO Data Register receives inputs or provides outputs for each of
the seven general-purpose port lines, depending on the configuration of
the port. See Table 8.
Table 8. General-Purpose Port Data Register
Bit #
Function
7
6
5
4
3
2
1
GPIO D0
X
GPIO D1
X
GPIO D2
X
GPIO D3
X
GPIO D4
X
GPIO D5
X
GPIO D6
GPIO D7
0
X
X
Caution: Reading from the general-purpose port can damage the drivers
used for the general-purpose port and memory. The port can,
however, be used for writing data.
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LED Matrix
The one 7 x 5 LED matrix device on the eZ80® Development Platform is a
memory-mapped device that can be used to display information, such as
programmed alphanumeric characters. For example, the LED display
sample program that is shipped with this kit displays the alphanumeric
message:
eZ80
To illuminate any LED in the matrix, its respective anode bit must be set
to 1 and its corresponding cathode bit must be set to 0.
Bits 0–6 in Table 7 are LED anode bits. They must be set High (1) and
their corresponding cathode bits, bits 0–4 in Table 9, must be set Low (0)
to illuminate each of the LED’s, respectively.
Bit 7 in Table 7 does not carry any significance within the LED matrix. It
is used for the general-purpose port as a control bit.
Table 9 indicates the multiple register functions of the LED cathode,
modem, and triggers. This table shows the bit configuration for each cathode bit. Bits 5, 6, and 7 do not carry any significance within the LED
matrix. These three bits are control bits for the modem reset, Trig1, and
Trig2 functions, respectively.
Table 9. Bit Access to the LED Cathode, Modem, and Triggers
Bit #
Function
7
6
5
4
3
2
1
Cathode Row 5
X
Cathode Row 4
X
Cathode Row 3
Cathode Row 2
eZ80® Development Platform
0
X
X
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Table 9. Bit Access to the LED Cathode, Modem, and Triggers (Continued)
Bit #
Function
7
6
5
Cathode Row 1
4
3
2
1
0
X
MRESET
X
Trig 1
X
Trig 2
X
An LED display sample program is shipped with the eZ80190 Development Kit. Please refer to the eZ80190 Development Kit Quick Start Guide
(QS0004) or to the Tutorial section in the ZiLOG Developer Studio II—
eZ80 User Manual (UM0123).
Modem Reset
The Modem Reset signal, MRESET, is used to reset an optional socket
modem. This signal is controlled by bit 5 in the register shown in Table 9.
The MRESET signal is available at the embedded modem socket interface
(J9, Pin 1). Setting this bit Low places the optional socket modem into a
reset state. The user must pull this bit High again to enable the socket
modem. Reference the appropriate documentation for the socket modem to
reset timing requirements. More information about this signal is provided
in the next section.
User Triggers
Two general-purpose trigger output pins are provided on the eZ80®
Development Platform. Labeled J21 (Trig2) and J22 (Trig1), these pins
allow the user a way to trigger external equipment to aid in the debug of
the system. See Figure 8 for trigger pin details.
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J21
J22
Ground
Trigger output
Trig2
Trig1
Figure 8. Trigger Pins J21 and J22
Bits 6 and 7 in Table 9 are the control bits for the user triggers. If either
bit is a 1, the corresponding Trig1 and Trig2 signals are driven High. If
either bit is 0, the corresponding Trig1 and Trig2 signals are driven Low.
Embedded Modem Socket Interface
The eZ80® Development Platform features a socket for an optional 56K
modem (a modem is not included in the kit). The tested modem for this
eZ80190 Development Kit is a Conexant socket modem, part number
SF56D/SP. Information about this modem and its interface is available in the
SmartSCM SocketModem data sheet (Doc. No. 101522D) from www.conexant.com.
Connectors J1, J5, and J9 provide connection capability. The modem
socket interface provided by these three connectors is shown in Figure 9.
Tables 10 through 12 identify the pins for each connector. The embedded
modem utilizes UART1, which is available via the Port C pins.
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J5
1
J1
2
2
4
24
25
26
27
J9
1
28
29
3
6
7
30
31
8
9
32
Figure 9. Embedded Modem Socket Interface—J1, J5, and J9
Table 10. Connector J5
Pin Symbol
Description
1
M-TIP
Telephone Line Interface—TIP.
2
M-RING
Telephone Line Interface—RING.
Table 11. Connector J9
Pin Symbol
Description
1
MRESET
Reset, active Low, 50–100 ms. Closure to GND for reset.
3
GND
Ground.
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Table 11. Connector J9
6
D1
DCD indicator; can drive an LED anode without additional circuitry.
7
D2
RxD indicator; can drive an LED anode without additional circuitry.
8
D3
DTR indicator; can drive an LED anode without additional circuitry.
9
D4
TxD indicator; can drive an LED anode without additional circuitry.
Table 12. Connector J1
Pin Symbol
Description
2
MOD_DIS
Modem disable, active Low.
4
VCC
+5 VDC or +3.3 VDC input.
24
GND
Ground.
25
PC4_DTR1 DTR interface; TTL levels.
26
PC6_DCD1 DCD interface; TTL levels.
27
PC3_CTS1 CTS interface; TTL levels.
28
PC5_DSR1 DSR interface; TTL levels.
29
PC7_RI1
30
PC0_TXD1 TxD interface; TTL levels.
31
PC1_RXD1 RxD interface; TTL levels.
32
PC2_RTS1 RTS interface; TTL levels.
Ring Indicator interface; TTL levels.
Components P4, T1, C3, C4, and U11 provide the phone line interface to
the modem. On the eZ80® Development Platform, LEDs D1, D2, D3, and
D4 function as status indicators for this optional modem.
The phone line connection for the modem is for the United States only.
Connecting the modem outside of the U.S. requires modification.
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eZ80® Development Platform Memory
Memory space on the eZ80® Development Platform consists of onboard
SRAM and additional footprints.
Onboard SRAM
The eZ80® Development Platform features 512 KB SRAM at U20. This
SRAM provides the basic memory requirement for small applications
development. This SRAM is in the address range B80000h–BFFFFFh.
Additional SRAM
The amount of eZ80® Development Platform memory can be extended if
required by adding SRAM devices. U19, U18, and U17 provide this capability. However, the user should be aware that additional SRAM must be
installed in the following order:
1. U19, address range B00000h–B7FFFFh
2. U18, address range A80000h–AFFFFFh
3. U17, address range A00000h–A7FFFFh
If SRAM memory is installed in a different order than the above
sequence, SRAM will not be contiguous unless the user is able to change
the address decoder, U10. Memory access decoding is performed by this
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
Memory Map
A memory map of the eZ80® CPU is illustrated in Figure 10. Flash memory and SRAM on the eZ80190 Module are addressed when CS0 and CS1
are active Low. SRAM on the eZ80® Development Platform is addressed
when CS2 is active Low.
The eZ80190 MCU features 8 KB of internal SRAM in the address range
E000h–FFFFh and 1 KB of MACC RAM in the address range DC00h–
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DFFFh. Internal RAM can be mapped anywhere in the 16 MB address
space in 64 KB steps (DC00h–FFFFh to DC00h–FFFFFFh). The software
included in the eZ80190 Development Kit assumes internal RAM in the
range E000h–FFFFh for the interrupt vector table. This range overlaps the
address range assigned to Flash memory (CS0) on the eZ80190 Module.
Note: The Ethernet controller, located on the eZ80190 Module, is mapped as an
I/O device at address 300h. It uses CS3.
FFFFFFh
DFFFFFh
SRAM Memory
up to 2 MB
C7FFFFh
C00000h
BFFFFFh
B80000h
CS1
Ethernet Module
SRAM
Main Board
SRAM (512 KB)
Expansion SRAM Memory
up to 1.5 MB
CS2
80FFFFh
800000h
7FFFFFh
Expansion Module
Flash Memory up to 4 MB
Up to 4 MB
400000h
3FFFFFh
CS0 (8 MB)
Flash Memory
0FFFFFh
000000h
Up to 4 MB
1 MB on
Ethernet Module
Figure 10. Memory Map of the eZ80® Development Platform
and eZ80190 Module
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The LED matrix and the general-purpose port circuitry are mapped in the
address range 800000h–80ffffh. The CS2 chip select should be driven
Low to select the LED matrix or general-purpose port.
LEDs
As stated earlier, LEDs D1, D2, D3, and D4 function as status indicators
for an optional modem. This section describes each LED and the LED
matrix device.
Data Carrier Detect
The Data Carrier Detect (DCD) signal at D1 indicates that a good carrier
signal is being received from the remote modem.
RX
The RX signal at D2 indicates that data is received from the modem.
Data Terminal Ready
The Data Terminal Ready (DTR) signal at D3 informs the modem that the
PC is ready.
TX
The TX signal at D4 indicates that data is transmitted to the modem.
Push Buttons
The eZ80® Development Platform provides user controls in the form of
push buttons. These push buttons serve as input devices to the eZ80®
Ethernet Device device. The programmer can use them as necessary for
application development. All push buttons are connected to the generalpurpose port pins.
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PB0
The PB0 push button switch, SW1, is connected to bit 0 of the generalpurpose port. This switch can be used as the port input if required by the
user.
PB1
The PB1 push button switch, SW2, is connected to bit 1 of the generalpurpose port. This switch can be used as the port input if required by the
user.
PB2
The PB2 push button switch, SW3, is connected to bit 2 of the generalpurpose port. This switch can be used as the port input if required by the
user.
RESET
The Reset push button switch, SW4, resets the eZ80® CPU and the eZ80®
Development Platform.
Jumpers
The eZ80® Development Platform provides a number of jumpers that are
used to enable or disable functionality on the platform, enable or disable
optional features, or to provide protection from inadvertent use.
Jumper J2
The J2 jumper enables/disables IrDA transceiver functionality. When the
shunt is placed, IrDA communication is disabled. This jumper does not
perform any functions when the eZ80190 Module is installed.
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Jumper J3
The J3 jumper connection controls the mode of the general-purpose port
and communication with the 7 x 5 LED. When the shunt is placed, the
general-purpose port is disabled. See Table 13.
Table 13. J3—DIS_EM
Shunt
Status
Function
Affected Device
In
Application Module
Hardware Disabled
Communication with 7 x 5 LED and Port emulation
circuit is disabled.
Out
Application Module
Hardware Enabled
Communication with 7 x 5 LED and the generalpurpose port circuit is enabled.
Jumper J7
The J7 jumper connection controls Flash boot loader programming. When
the shunt is placed, overwriting of the Flash boot loader program is
enabled. See Table 14.
Table 14. J7—FlashWE
Shunt
Status
Function
Affected Device
Out
The Flash boot sector of the eZ80190
Module is write-protected.
Flash boot sector of the eZ80190
Module.
In
The Flash boot sector of the eZ80190
Module is enabled for writing or
overwriting.
Flash boot sector of the eZ80190
Module.
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Jumper J11
The J11 jumper connection controls access to the Flash memory device.
When the shunt is removed, access to the Flash device is disabled/prevented. See Table 15.
Table 15. J11—DIS_FL
Shunt
Status
Function
Affected Device
OUT
All access to Flash on the eZ80190
Module is disabled.
Flash on eZ80190 Module.
IN
Flash on the eZ80190 Module is
enabled.
Flash on eZ80190 Module.
Jumper J12
The J12 jumper connection controls the selection of a 5 V or 3 VDC
power supply to the embedded modem, if an embedded modem is used.
See Table 16.
Table 16. J12—5VDC/3.3VDC for an Embedded Modem
Shunt
Status
Function
Affected Device
1–2
5 VDC is provided to power the embedded modem.
Embedded modem.
2–3
3.3 VDC is provided to power the embedded modem. Embedded modem.
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Jumper J14
The J14 jumper connection controls the polarity of the Ring Indicator.
See Table 17.
Table 17. J14—RI
Shunt
Status
Function
Affected Device
1–2
The Ring Indicator for UART1 is inverted.
UART1.
2–3
The Ring Indicator for UART1 is not inverted.
UART1.
For jumpers J15–J18, RS485 functionality is not available on the
eZ80190 Module. However, this functionality is available in other eZ80®
devices.
Jumper J15
The J15 jumper connection controls the selection RS485 circuit along
with UART0. When the shunt is placed, the RS485 circuit is enabled. See
Table 18. RS485 functionality will be available in future eZ80® devices.
Table 18. J15—RS485_1_EN*
Shunt
Status
Function
Affected Device
In
The RS485 circuit is enabled on UART0.
The UART0 CONSOLE interface and IrDA are
disabled.
IrDA, UART0 CONSOLE
interface, RS485 interface.
Out
The RS485 circuit is disabled on UART0.
IrDA, UART0 CONSOLE
interface, RS485 interface.
Note: *To enable the RS485 circuit, the corresponding IrDA/RS232 circuit must be disabled.
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Jumper J16
The J16 jumper connection controls the selection of the RS485 circuit.
However, UART1 MODEM interface and the socket modem interface are
disabled if the RS485 circuit is enabled. When the shunt is placed, the
RS485 circuit is enabled. See Table 19.
Table 19. J16—RS485_2_EN
Shunt
Status
Function
Affected Device
In
The RS485 circuit is enabled on UART1. The UART1 MODEM interface,
UART1 MODEM interface and the Socket
Socket Modem Interface, and
Modem interface are disabled.
RS485 interface.
Out
The RS485 circuit is disabled on UART1.
UART1 MODEM interface,
Socket Modem Interface, and
RS485 interface.
Jumper J17
The J17 jumper connection controls the selection of the RS485 termination resistor circuit. When the shunt is placed, the RS485 termination
resistor circuit is enabled. See Table 20.
Table 20. J17—RT_1*
Shunt
Status
Function
Affected Device
In
The Termination Resistor for RS485_1 is IN.
RS485 interface.
Out
The Termination Resistor for RS485_1 is OUT.
RS485 interface.
Note: *Before enabling the termination resistor, ensure that the device is located at the end of the
interface line.
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Jumper J18
The J18 jumper connection controls the selection of the RS485 termination resistor circuit. When the shunt is placed, the RS485 termination
resistor circuit is enabled. See Table 21.
Table 21. J18—RT_2*
Shunt
Status
Function
Affected Device
In
The Termination Resistor for RS485_2 is IN.
RS485 interface.
Out
The Termination Resistor for RS485_2 is OUT.
RS485 interface.
Note: *Before enabling the termination resistor, ensure that the device is located at the end of the
interface line.
Jumper J19
The J19 jumper connection selects the range of memory addresses for the
external chip select signal, CS_EX, to the application module. See
Table 22.
Table 22. J19—EX_SEL
Shunt
Status
Function
Affected Device
1–2
CS_EX is decoded in the CS0 memory space and is Application module
located in the address range 400000h–7FFFFFh.
addressing.
3–4
CS_EX is decoded in the CS2 memory space and is Application module
located in the address range A00000h–A7FFFFh.
addressing.
5–6
CS_EX is decoded in the CS2 memory space and is Application module
located in the address range A80000h–AFFFFFh.
addressing.
7–8
CS_EX is decoded in the CS2 memory space and is Application module
located in the address range B00000h–B7FFFFh.
addressing.
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Jumper J20
The J20 jumper connection controls the selection of the external chip
select in the external application module. When the shunt is placed, the
external chip select signal, CS_EX, is disabled. See Table 23.
Table 23. J20—EX_FL_DIS
Shunt
Status
Function
Affected Device
IN
The jumper for EX_FL_DIS is IN. The chip select on the application module
is disabled.
OUT
The jumper for EX_FL_DIS is OUT. The chip select on the application module
is enabled.
Connectors
A number of connectors are available for connecting external devices
such as the ZPAK II emulator, PC serial ports, external modems, the console, and LAN/telephone lines.
J6 and J8 are the headers, or connectors, that provide pin-outs to connect
any external application module, such as ZiLOG’s Thermostat Application Module.
Connector J6
The J6 connector provides pin-outs to make use of GPIO functionality.
Connector J8
The J8 connector provides pin-outs to access memory and other control
signals.
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Console
Connector P2 is the RS232 terminal, which can be used for observing the
console output. P2 can be connected to a PC running a HyperTerminal
program if required.
Modem
Connector P3 provides a terminal for connecting an external modem, if
used with the eZ80190 Development Kit.
I2C Devices
The two I2C devices on the eZ80® Development Platform are the U2
EEPROM and the U13 Configuration register. The EEPROM provides
16 KB of memory. The Configuration register provides access to control
the configuration of an application-specific function at the Application
Module Interface. Neither device is utilized by the eZ80190 Development
Kit software. The user is free to develop proprietary software for these
two devices. The addresses for accessing these devices are listed in
Table 24.
Table 24. I2C Addresses
Device/Bit #
7
6
5
4
3
2
1
0
EEPROM (U10)*
1
0
1
0
0
A1
A0
R/W
Configuration Register (U13)
1
0
0
1
1
1
0
R/W
Note: *EEPROM address bits A0 and A1 are configured for 0s.
DC Characteristics
Understanding proper DC current requirements for the eZ80® Development Platform when application modules are plugged into it is very
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important for developing applications. This section provides an estimate
of the average current requirement when different combinations of these
application modules are plugged in to the eZ80® Development Platform.
The measurements of current that are shown in Table 25 are for the user’s
reference. These values can vary depending on the type of application that
is developed to run with the platform.
Table 25. DC Current Characteristics of the
eZ80® Development Platform with Different Module Loads
Platform/Modules Configurations
eZ80® Development Platform and
eZ80190 Module
Current
Requirement (mA) Status
173
When connected only to a
power supply, and when
no program is running.
eZ80® Development Platform, eZ80190 174
Module, and Modem Module
When connected only to a
power supply, and when
no program is running.
eZ80® Development Platform, eZ80190 195
Module, and Thermostat Application
Module
When connected only to a
power supply, and when
no program is running.
eZ80® Development Platform, eZ80190 203
Module, Modem Module, and
Thermostat Application Module
When connected only to a
power supply, and when
no program is running.
eZ80® Development Platform and
eZ80190 Module
325
When the LED demo is
running.
eZ80® Development Platform, eZ80190 325
Module, and Modem Module
When the LED demo is
running.
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Table 25. DC Current Characteristics of the
eZ80® Development Platform with Different Module Loads (Continued)
Platform/Modules Configurations
Current
Requirement (mA) Status
eZ80® Development Platform, eZ80190 350
Module, and Thermostat Application
Module
When the LED demo is
running.
eZ80® Development Platform, eZ80190 360
Module, Modem Module, and
Thermostat Application Module
When the LED demo is
running.
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eZ80190 Module
This section describes the eZ80190 Module hardware, its interfaces and
key components, including the CPU, Ethernet Media Access Controller
(EMAC), and memory.
Functional Description
The eZ80190 Module is a compact, high-performance Ethernet module
specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity via
Ethernet and/or fast Multiply-Accumulate operations. Additional devices
such as serial ports, LED matrices, GPIO ports, and I2C devices are supported when connected to the eZ80® Development Platform. A block diagram representing both of these boards is shown in Figure 1 on page 4.
The eZ80190 Module is developed to be a plug-in module to the eZ80®
Development Platform. The small-footprint eZ80190 Module provides a
CPU, SRAM, Flash memory, a real-time clock, and an EMAC. This lowcost, expandable module is powered by the eZ80190 microprocessor, a
member of ZILOG’s new eZ80® product family. The module also contains a battery and an oscillator in support of the onboard Real-Time
Clock (RTC). The eZ80190 Module can also be used as a stand-alone
development tool when provided with an external power source.
Physical Dimensions
The footprint of the eZ80190 Module PCB is 63.5 mm x 78.7 mm. With an
RJ-45 Ethernet connector, the overall height is 25 mm. See Figure 11.
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78.7 mm
63.5 mm
63.5 mm
Figure 11. Physical Dimensions of the eZ80190 Module
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Figure 12 illustrates the top layer silkscreen of the eZ80190 Module.
Figure 12. eZ80190 Module—Top Layer
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Figure 13 illustrates the bottom layer silkscreen of the eZ80190 Module.
Figure 13. eZ80190 Module—Bottom Layer
Operational Description
The purpose of the eZ80190 Module as a feature of the eZ80190 Development Kit is to provide the application developer with a plug-in tool to
evaluate memory and the other features of the eZ80190 device.
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Ethernet Media Access Controller
The eZ80190 Module contains a CS8900A Ethernet Media Access Controller (EMAC—combines MAC and PHY functions) which is attached to
the data/address bus (A0–A3, D0–D7, RD, and WR) of the processor.
This chip is connected to the processor’s CS3 Chip Select, and to the PD4
pins for interrupt purposes. Connection of pins PD6 and PD7 for
LANACT (wake-up from sleep) and SLEEP is optional and resistorselectable onboard (see below). Details about the internal registers of the
CS8900A EMAC can be found on the Cirrus Logic website at www.cirrus.com.
Ethernet LEDs
There are two green LEDs, a Link LED and a LAN LED, that are located
adjacent to each other on the eZ80190 Module. A steady LAN LED (top)
indicates received link pulses from the Ethernet. A flashing Link LED
(bottom) indicates Traffic (RX or TX) on the LAN.
Ethernet Connector
The eZ80190 Module is equipped with an RJ-45 connector that features
integrated magnetics (transformer, common mode chokes). The remaining pins on the onboard RJ-45 connector are not connected.
An RJ-45 loopback connector can be used to verify the correct operation
of the Receiver and the Transmitter. Pin assignments for the RJ-45 Ethernet connector are shown in Table 26.
Table 26. Ethernet Connector Pin Assignments
Pin
eZ80190 Module
Function
1
TX+
2
TX–
3
RX+
6
RX–
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To connect the eZ80190 Module directly to another host (e.g., to a personal computer), a crossover cable must be used.
The EMAC can be additionally protected by placing an ESD protection
array on the module at U8. This array can be either of the LCDA15C-6
(Semtech) or ESDA25B1 (ST Microelectronics) devices.
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt
GPIO input bit PD4 serves as an active High interrupt input for the
EMAC’s INTRQ0 output.
GPIO output bit PD7 can be used to place the EMAC into SLEEP mode.
When pulling SLEEP (PD7) Low after enabling HWStandbyE and
HWSleepE modes, the chip draws lower current, because only the
receiver is operating. A zero-Ohm resistor at position R14 on the eZ80190
Development Kit is required for this function.
If LAN activity is detected, the LANACT signal is pulled Low. The
LANACT is connected to GPIO input PD6 and can be used in interrupt
edge-detection mode to wake up and reinitialize the Ethernet chip. A
zero-Ohm resistor at position R15 on the module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector.
EMAC Access
CS3 is used for selecting the Ethernet MAC. For 50 MHz operation, set
the CS3_CTL register (I/O address B3h) to F8h (7 wait states for I/O).
The EMAC requires –IOR to be active for 135 ns and –IOW to be active
for 110 ns.
To satisfy proper setup times at 50 MHz, –IOR is delayed by one clock
cycle and –IOW is delayed by two clock cycles when CS3 goes active. To
satisfy proper hold times at 50 MHz, the EMAC address and data are
latched when CS3 goes inactive.
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eZ80190 Module Memory
The eZ80190 Module contains 512 KB SRAM and 1 MB Flash memory.
This addressing structure provides 1.5 MB of contiguous RAM for immediate use.
SRAM Memory
The eZ80190 Module features 512 KB of fast SRAM. Access speed is
typically 12 ns or faster, allowing zero-wait-state operation at 50 MHz.
With the CPU at 50 MHz, onboard SRAM can be accessed with zero wait
states. CS1_CTL (chip select CS1) is set to 08h (no wait states).
Flash Memory
The Flash Boot Loader, application code, and user configuration data are
held permanently in Flash memory.
Internal RAM
The eZ80190 MCU features 8 KB of zero-wait-state internal SRAM. This
internal RAM can be mapped anywhere in the 16 MB address space in the
address range E000h–FFFFh.
Reset Generator
The onboard Reset Generator Chip is connected to the eZ80190 Reset
input pin. It performs reliable Power-On Reset functions, generating a
reset pulse with a duration of 200 ms if the power supply drops below
2.93 V. This reset pulse ensures that the board always starts in a defined
condition. The RESET pin on the I/O connector reflects the status of the
RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80190 Development Kit with a low-impedance output (e.g. a 100-Ohm push button).
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Real Time Clock
The onboard real-time clock can function when the system power supply
is down. An onboard capacitor (GoldCap) or external accumulator/battery
serves as a standby power supply. The M41T11 Real-Time-Clock
included on the eZ80190 Module contains Binary Coded Decimal (BCD)
counting registers for Seconds, Minutes, Hours, Day, Month, Year; it also
contains a Century bit and 56 bytes of backed-up RAM. The fullycharged 0.1 F GoldCap bridges power outages with a maximum of 4
hours. The GoldCap, in contrast to a battery or an accumulator, offers an
advantage in that service/replacement is not necessary.
The I2C address of the RTC is D0h for Writes and D1h for Reads.
Details about the internal registers of the M41T11 Real-Time clock can
be found on the ST Microelectronics website (www.st.com).
I2C Bus Software Emulation
The eZ80190 device contains two powerful master/slave mode I2C bus
controllers. The I2C data (SDA) and clock (SCL) pins on PD1/PD0 and
PC1/PC0 GPIO are multiplexed with the UART and SPI functions. To use
I2C bus operation in parallel with console and modem I/O, the module
IICSCL/IICSDA pins on connector JP2 can be linked to PA7 (IICSDA)
and PA6 (IICSCL) of the eZ80190 device. In this case, an I2C mastermode software emulation is necessary to access I2C devices.
Using PA7/PA6 or PC1/PC0 for IICSDA/IICSCL is resistor-selectable on
the eZ80190 Module.
DC Characteristics
As different combinations of application modules are loaded onto the
eZ80® Development Platform, current requirements change. Please see
Table 25 on page 42 to reference current consumption values for these
different modules.
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Flash Loader Utility
The Flash Loader utility resides in the boot sector of Flash memory,
located on the eZ80190 Module. The Flash Loader utility allows the user
to program application code into Flash memory.
Please refer to the External Flash Loader Product User Guide (PUG0012)
for more details.
Mounting the Module
When mounting the eZ80190 Module onto the eZ80® Development Platform, check its orientation to the platform to ensure a correct fit. Pin 11 of
JP1 on the eZ80190 Module must align with pin 1 of JP1 on the eZ80®
Development Platform; Pin 11 of JP2 on the eZ80190 Module must align
with pin 1 of JP2 on the eZ80® Development Platform, etc.
Changing the Power Supply Plug
The universal 9VDC power supply offers three different plug configurations and a tool that aids in removing one plug configuration to insert
another, as shown in Figure 14.
Figure 14. 9VDC Universal Power Supply Components
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To exchange one plug configuration for another, perform the following
steps:
1. Place the tip of the removal tool into the round hole at the top of the
current plug configuration.
2. Press down to disengage the keeper tab and push the plug configuration out of its slot.
3. Select the plug configuration appropriate for your location, and insert
it into the slot formerly occupied by the previous plug configuration.
4. Push the new plug configuration down until it snaps into place, as
indicated in Figure 15.
Figure 15. Inserting a New Plug Configuration
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ZPAK II
ZPAK II is a debug tool used to develop and debug hardware and software. It is a networked device featuring an Ethernet interface and an
RS232 console port. ZPAK II is shipped with a preconfigured IP address
that can be changed to suit the user on a local network. For more information about using and configuring ZPAK II, please refer to the ZPAK II
Debug Interface Tool Product User Guide (PUG0015) and the eZ80190
Development Kit Quick Start Guide (QS0004).
ZDI Target Interface Module
The ZDI Target Interface Module provides a physical interface between
ZPAK II and the eZ80® Development Platform. The TIM module supports
ZDI functions. For more information on using the TIM module or ZDI
please refer to the eZ80190 Development Kit Quick Start Guide
(QS0004) and the eZ80190 Module Product Specification (PS0191).
JTAG
Connector P1 is the JTAG connector on the eZ80® Development Platform. JTAG will be supported in the next offering of eZ80® products.
Application Modules
ZiLOG offers the Thermostat Application module, which can be used for
evaluating and developing process control and simple I/O applications.
The Thermostat Application module is equipped with an LCD display that
can be used to display process control and other physical parameters. For
additional reading about the Thermostat application, please see the Java
Thermostat Demo Application Note (AN0104) on zilog.com.
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ZPAK II
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ZDS II
ZiLOG Developer Studio II (ZDS II) Integrated Development Environment is a complete stand-alone system that provides a state-of-the-art
development environment. Based on the Windows® Win98SE/NT4.0SP6/Win2000-SP2/WinXP user interfaces, ZDS II integrates a languagesensitive editor, project manager, C-Compiler, assembler, linker, librarian,
and source-level symbolic debugger that supports the eZ80® CPU. For
more information about using and configuring ZDS II, please refer to the
ZiLOG Developer Studio II—eZ80 User Manual (UM0123).
ZDS II
ZDS II
PRELIMINARY
UM014103-0803
eZ80190 Development Kit
User Manual
57
Troubleshooting
Overview
Before contacting ZiLOG Customer Support to submit a problem report,
please follow these simple steps. If a hardware failure is suspected, contact a local ZiLOG representative for assistance.
Cannot Download Code
If you are unable to download code to RAM using ZDS, make sure to
press and release the Reset button on the eZ80® Development Platform
prior to selecting Build → Debug → Reset + Go in ZDS.
No Output on Console Port
The eZ80190 Development Kit is shipped with a Flash Loader utility that
is loaded in the protected boot sector of Flash memory (U3). Upon powerup of the eZ80® Development Platform and the eZ80 Webserver-i E-NET
Module, the eZ80190 device on the module starts running code from this
Flash memory area. This code enables the Console port with settings of
57.6 kbps, 8, N, 1.
The Console checks the Receive buffer. If a space character is received on
the Console port, the Flash Loader utility is enabled and a boot message
should be displayed on your connected device. If no message is displayed, check the following:
•
•
UM014103-0803
Jumper J2 must be ON (IrDA is disabled)
On Connector J6, the jumper must be removed from pins 6 and 9 (pin
names con_dis and GND).
PRELIMINARY
Overview
eZ80190 Development Kit
User Manual
58
IrDA Port Not Working
If you plan on using the IrDA transceiver on the eZ80 Webserver-i E-NET
Module, make sure the hardware is set up as follows:
•
Jumper J2 must be OFF (to enable the control gate that drives the
IrDA device)
•
Set port pin PD2 Low. When this port pin and Jumper J2 are turned
OFF, the IrDA device is enabled.
•
Install a jumper on connector J6 across pin names con_dis and GND
to disable the console serial port driver
Difference Between EMAC and IP Address
Media Access Control (MAC)
Each and every Ethernet device interface to the network media (e.g., network adapter, port on a hub) contains a unique MAC address, which is
hard-coded into the hardware when it is manufactured. An Ethernet
device addresses a host using a unique 48-bit address called its Ethernet
address or Media Access Control (MAC) address.
MAC addresses are usually represented as six colon-separated pairs of
hex digits, e.g., 6:0:20:11:ac: 85. The first three bytes (e.g., 6-0-20) are
the manufacturer’s code, which can be used to identify the manufacturer.
The last three bytes are the unique station ID or serial number for the
interface. This station ID is unique and is associated with a particular
Ethernet device. The Data Link layer's protocol-specific header specifies
the MAC address of the packet's source and destination. When a packet is
sent to all hosts (broadcast), a special MAC address (ff:ff:ff:ff:ff:ff) is
used.
MAC addresses uniquely identify each node in a network at the Media
Access Control layer, the lowest network layer that directly interfaces
with the physical media (e.g., twisted-pair wires).
Troubleshooting
PRELIMINARY
UM014103-0803
eZ80190 Development Kit
User Manual
59
On a Local Area Network or other network, the MAC address is the computer's unique hardware number. (On an Ethernet LAN, the MAC address
is the same as an Ethernet address.) When it is connected to the Internet, a
computer (or host as the Internet protocol considers it), a correspondence
table relates the Internet Protocol (IP) address to the computer's physical
(MAC) address on the LAN.
IP Address
An IP address is a 32-bit number that identifies each sender or receiver of
information that is sent in packets across the Internet.
An IP address contains two parts: the identifier of a particular network on
the Internet, and an identifier of the particular device (which can be a
server or a workstation) within that network. On the Internet itself—that
is, between the router that moves packets from one point to another along
the route—only the network part of the address is examined.
Relationship of the IP Address to the Physical Address
The machine or physical address used within an organization's local area
networks can be different than the IP address coming from the Internet.
The most typical example is the 48-bit Ethernet address. TCP/IP includes
the Address Resolution Protocol (ARP) that lets the administrator create a
table that maps IP addresses to physical addresses.
The Ethernet MAC address of the ZPAK II
When connecting the ZPAK II serial port to a PC running HyperTerminal,
hold the space bar and reset the ZPAK II.
When HyperTerminal prompts with
eZ80>
enter e to display the MAC address.
UM014103-0803
PRELIMINARY Difference Between EMAC and IP Address
eZ80190 Development Kit
User Manual
60
Resolving IP Address/Subnet Mask Conflicts
For running demos properly. the ZPAK II IP address and subnet mask
must be properly configured. Please follow the instructions provided in
the eZ80190 Development Kit Quick Start Guide (QS0004) to set up and
run the demos on ZDS II.
Contacting ZiLOG Customer Support
For additional troubleshooting solutions, see ZDS Online Help.
For valuable information about hardware and software development tools,
visit ZiLOG Customer Support online. Download the latest released version of ZiLOG Developer Studio!
Get the latest software updates from ZiLOG as soon as they are available!
Troubleshooting
PRELIMINARY
UM014103-0803
eZ80F91 Development Kit
User Manual
Schematic Diagrams
61
eZ80® Development Platform
Figures 16 through 20 present the schematics of the eZ80® Development Platform.
MA6
MA10
DO NOT USE J6_17 AND J6_35
VCC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
9V_DC
9VDC
SCL
SDA
GND
-DIS_MOD
-MWAIT
EM_D0
-CS3
GND
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
GND
PC7_RI1
PC6_DCD1
PC5_DSR1
PC4_DTR1
PC3_CTS1
PC2_RTS1
PC1_RXD1
PC0_TXD1
GND
GND
A8
A10
A12
A14
GND
A16
A18
A20
A22
VDD
-RESET
GND
D0
D2
D4
D6
GND
-CS0
-CS2
-MEMRQ VDD
ID_2
ID_1
ID_0
-DIS_CON
GND
-DIS_ETH
GND
PD7_RI0
PD6_DCD0
PD5_DSR0
PD4_DTR0
PD3_CTS0
PD2_RTS0
PD1_RXD0
PD0_TXD0
GND
PB7_MOSI
PB6_MISO
PB5_T5_O
PB4_T4_O
PB3_SCK
PB2_SS
PB1_T1_I PB2_SS
PB0_T0_I PB1_T1_I
PB0_T0_I
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
A1
A3
A5
A7
GND
A9
A11
A13
A15
VDD
R3
10K
GND
A17
A19
A21
A23
VDD
-CS1
-CS_EX
-IORQ
J4
VDD
1
3
5
GND
MA23
-M_CS1
MD0
MD2
MD4
MD6
-M_IORQ
-M_RD
INSTRD
-BUSREQ
A1
A2
A3
A4
A5
A6
A7
A8
1
19
VDD
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1OE
2OE
VCC
GND
2
4
6
8
11
13
15
17
GND
1
19
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
1OE
2OE
VCC
GND
J5
M_TIP
M_RING
M_TIP
M_RING
R19
PRSTn
TCK
TDI
J9
DCD
-RESET
D1
1
TC74LVC08
VDD
RX
TDI
TDO
TCK
R5
1K
TVCC_RESETn
VDD
1
3
5
7
9
11
13
2
4
6
8
10
12
14
D3
1
DTR
R20
0
2
GND
TX
0
2
1
TMS
PRSTn
TRIGOUT
-MRESET
R8
0
R9
D2
1
P1
2
J2
1
2
-MRESET
GND
1
2
3
4
5
6
7
8
9
2
0
HEADER 9
SDA
8
VDD
4
3
GND
NC
AT24C128
20
10
-FLASHWE
GND
1
2
U21
HEADER 2
-M_CS0
-M_CS1
-M_CS2
-M_IORQ
-M_MEMRQ
-M_WR
-M_RD
-M_CS3
M_PHI
VDD
GND
C31
0.1uF
A16
A17
A18
A19
A20
A21
A22
A23
18
16
14
12
9
7
5
3
20
10
2
3
4
5
6
7
8
9
10
11
1
13
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE1
OE2
VCC
GND
23
22
21
20
19
18
17
16
15
14
24
12
-CS0
-CS1
-CS2
-IORQ
-MEMRQ
-WR
-RD
-CS3
PHI
VDD
GND
C34
0.1uF
74LVC827/SO
VDD
GND
C33
0.1uF
J12
VCC
1
2
3
VDD
Header 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MODEM's
AGND
-DIS_MOD
D[7:0]
U7
VCC
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
-M_RD
-L_RD
2
3
4
5
6
7
8
9
1
19
A0
A1
A2
A3
A4
A5
A6
A7
DIR
OE
B0
B1
B2
B3
B4
B5
B6
B7
VCC
GND
74LVC245/SO
GND
PC4_DTR1
PC6_DCD1
PC3_CTS1
PC5_DSR1
PC7_RI1
PC0_TXD1
PC1_RXD1
PC2_RTS1
VCC
VDD
GND
HEADER 32
MODEM CONNECTORS
Figure 16. eZ80® Development Platform Schematic Diagram, #1 of 5
PRELIMINARY
WP
5
J7
con 7x2
UM014103-0803
GND
SDA
VCC
SCL
HEADER 2
A8
A9
A10
A11
A12
A13
A14
A15
18
16
14
12
9
7
5
3
R21
D4
-DIS_IRDA
GND
A0
A1
C30
0.1uF
J1
1
2
6
7
VDD
GND
74LVC244A
-DIS_IRDA
-MWAIT
GND
-NMI
R4
10K
1
3
SCL
U5
MA16
MA17
MA18
MA19
MA20
MA21
MA22
MA23
ZDI
INTERFACE
2
4
6
20
10
1
2
GND
74LVC244A
VDD
GND
TC74LVT125
2
4
6
8
11
13
15
17
R2
10K
PB6_MISO
PB4_T4_O
PB2_SS
PB0_T0_I
PC7_RI1
PC5_DSR1
PC3_CTS1
PC1_RXD1
PD7_RI0
GND
PD4_DTR0
PD2_RTS0
PD0_TXD0
TDI
TRIGOUT
TMS
M_PHI
GND
VCC
GND
U2
A[23:0]
A0
A1
A2
A3
A4
A5
A6
A7
18
16
14
12
9
7
5
3
74LVC244A
U3
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1OE
2OE
Header 3x2
7
7
U8A
-DIS_FL
VDD
2
GND
1
19
10K
14
1
14
U9A
MA1
MA12
MA20
MA17
-DIS_FL
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
HEADER 2
VDD
2
GND
2
4
6
8
11
13
15
17
VDD
GND
GND
MA7
MA9
MA14
MA16
Header 25x2
-WR
INSTRD
-BUSREQ
PHI
PHI
GND
D1
D3
D5
D7
Header 30x2
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
A[23:0]
U1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
VDD
JP2
PB7_MOSI
PB5_T5_O
PB3_SCK
PB1_T1_I
GND
PC6_DCD1
PC4_DTR1
PC2_RTS1
PC0_TXD1
PD6_DCD0
PD5_DSR0
PD3_CTS0
PD1_RXD0
TDO
GND
TCK
RTC_VDD
SCL
SDA
-FLASHWE
-M_CS3
-RESET
VDD
HALT_SLP
VDD
VDD
MA0
MA3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Header 25x2
R1
10K
Header 30x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
A0
A2
A4
A6
-RD
ID_2
ID_1
ID_0
J8
VDD
-BUSACK
-NMI
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
GND
MA8
MA13
MA15
MA18
MA19
MA2
MA11
MA4
MA5
-DIS_ETH
MA21
MA22
-M_CS0
-M_CS2
MD1
MD3
MD5
MD7
-M_MEMRQ
GND
-M_WR
-BUSACK
J6
VCC
VDD
GND
20
10
D[7:0]
D0
D1
D2
D3
D4
D5
D6
D7
18
17
16
15
14
13
12
11
VDD
C1
0.1uF
GND
MD[7:0]
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
eZ80F91 Development Kit
User Manual
62
R6 10K
J11
J20
-CS3
2
CLK/I0
VCC
GND
-EM_EN
M_TIP
P4
1
-CS_EX_IN
-MEM_CEN1
-MEM_CEN2 -MEM_CEN1
-MEM_CEN3 -MEM_CEN2
-MEM_CEN4 -MEM_CEN3
-MEM_CEN4
-L_RD
-DIS_FL
VDD
28
14
GND
T1
SIDACTOR P3100SB
U11
C2
0.1uF
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
VCC
OE
GND
CT4
CT3
CT2
CT1
CT0
2
5
6
9
12
15
16
19
U13
-MRESET
1
3
10
7
TRIG2
AN0
10
1
D5
8
VDD
20
Pin2
JP5
1
Pin2
11
SDA
SCL
1
-CS2
14
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
VCC
OE
GND
2
5
6
9
12
15
16
19
20
2
9
AN3
9
AN4
4
8
GND
-CON_DIS
U8C
TC74LVT125
AN5
10
5
5
AN6
J19
6
-CS_EX_IN
-MEM_CEN1
-MEM_CEN2
-MEM_CEN3
-DIS_IRDA
U8B
TC74LVT125
VDD
R10
10K
MD[7:0]
U15
-MEMRQ
-IORQ
-IORQ
2
CLK/I0
VCC
GND
22V10A/LCC_0
VDD
GND
VDD
GND
28
14
-DIS_ETH
R11
10K
R12
10K
U16
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
3
4
5
6
7
8
9
10
-EM_WR
-EM_RD
14
1
-EM_WR_OE
13
2
VDD
C7
0.1uF
GND
11
23
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
22
21
20
19
18
17
16
15
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
OEAB VCC
OEBA
GND
CEAB
CEBA
SW1
PB0_T0_I
SW PUSHBUTTON
SW2
PB1_T1_I
SW PUSHBUTTON
LEAB
LEBA
74LCX543/SO
24
SW3
VDD
PB2_SS
SW PUSHBUTTON
12
C8
0.1uF
GND
Figure 17. eZ80® Development Platform Schematic Diagram, #2 of 5
UM014103-0803
1
3
5
7
EX_SEL
GND
-EM_RD
-EM_WR
-CT_WR
-AN_WR
2
4
6
8
6
LTP-757
-CS3
A6
A7
-MOD_DIS
-DIS_0
C6
0.1uF
GND
17
18
19
20
21
23
24
25
26
27
11
U8D
TC74LVT125
74HCT374
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
12
VDD
VDD
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
ID_2
ID_1
ID_0
GND
-EM_WR_OE
-CS3
3
4
5
6
7
9
10
11
12
13
16
GND
-DIS_1
7
D0
D1
D2
D3
D4
D5
D6
D7
VDD
GND
16
15
14
13
12
11
10
9
PCA8550
14
4
-AN_WR
VDD
WP
N_MUX_O
MUX_SEL
M_OUT_A
M_OUT_B
M_OUT_C
M_OUT_D
11
AN2
3
4
7
8
13
14
17
18
SCL
SDA
OVERR
M_IN_A
M_IN_B
M_IN_C
M_IN_D
GND
GND
U14
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
12
C5
0.1uF
AN1
D[7:0]
SCL
SDA
JP4
TRIG1
-MRESET
TRIG1
TRIG2
14
13
-CT_WR
D0
D1
D2
D3
D4
D5
D6
D7
7
3
4
7
8
13
14
17
18
74HCT374
PHI
J3
C4
0.001uF
GND
D0
D1
D2
D3
D4
D5
D6
D7
1
-EM_EN
A0
A1
-RD
-WR
A2
A3
A4
A5
RJ14
C3
0.001uF
R7
R13
10K
-DIS_EM
1
2
3
4
U12
D[7:0]
-RD
-WR
2
1
1
2
3
4
M_RING
7
-CS2
-EX_FL_DIS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
17
18
19
20
21
23
24
25
26
27
22V10A/LCC
10K
-CS0
-CS1
SDA
SCL
3
4
5
6
7
9
10
11
12
13
16
VDD
MD[7:0]
-RD
-WR
2
1
-EX_FL_DIS
D0
D1
D2
D3
D4
D5
D6
D7
PHI
2
1
-FL_DIS
D[7:0]
-CS0
-CS1
U10
-CS2
-FL_DIS
-CS0
A23
A22
A21
A20
A19
A18
A17
A16
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
MD[7:0]
Ferrite Core
VDD
A[23:0]
PRELIMINARY
-CS_EX
eZ80F91 Development Kit
User Manual
63
A[23:0]
A[23:0]
D[7:0]
D[7:0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A[23:0]
-MEM_CEN1
-WR
-RD
D[7:0]
D0
D1
D2
D3
D4
D5
D6
D7
-MEM_CEN1
-MEM_CEN2
-MEM_CEN3
-MEM_CEN4
1
2
3
4
5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36
6
13
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC
CE
WE
OE
D0
D1
D2
D3
D4
D5
D6
D7
VDD0
VDD1
9
27
VDD
10
28
GND
C9
0.1uF
VSS0
VSS1
AS7C34096
U18
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
D0
D1
D2
D3
D4
D5
D6
D7
7
8
11
12
25
26
29
30
-MEM_CEN2
-WR
-RD
1
2
3
4
5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36
6
13
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC
CE
WE
OE
VDD0
VDD1
D0
D1
D2
D3
D4
D5
D6
D7
7
8
11
12
25
26
29
30
9
27
VDD
10
28
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
C10
0.1uF
VSS0
VSS1
AS7C34096
-MEM_CEN1
-MEM_CEN2
-MEM_CEN3
-MEM_CEN4
-MEM_CEN3
-WR
-RD
1
2
3
4
5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC
A[23:0]
6
13
31
CE
WE
OE
D0
D1
D2
D3
D4
D5
D6
D7
VDD0
VDD1
9
27
VDD
10
28
GND
AS7C34096
U9C
TC74LVC08
8
10
7
VDD
GND
14
VDD
GND
U9B
TC74LVC08
4
6
14
7
5
U9D
TC74LVC08
12
11
7
13
Figure 18. eZ80® Development Platform Schematic Diagram, #3 of 5
UM014103-0803
PRELIMINARY
-MEM_CEN4
-WR
-RD
1
2
3
4
5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36
6
13
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC
CE
WE
OE
D0
D1
D2
D3
D4
D5
D6
D7
VDD0
VDD1
D0
D1
D2
D3
D4
D5
D6
D7
7
8
11
12
25
26
29
30
9
27
VDD
10
28
GND
C12
0.1uF
VSS0
VSS1
AS7C34096
GND
-RD
-WR
U20
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
D0
D1
D2
D3
D4
D5
D6
D7
7
8
11
12
25
26
29
30
C11
0.1uF
VSS0
VSS1
9
-RD
-WR
D[7:0]
D[7:0]
U19
A[23:0]
D0
D1
D2
D3
D4
D5
D6
D7
14
D[7:0]
A[23:0]
U17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
eZ80F91 Development Kit
User Manual
64
GND
9VDC
9VDC
VDD
1
2
14
PD0_TXD0
GND
12
PD2_RTS0
22
-DIS_CON
VDD
13
R14
23
10K
20
19
18
PD3_CTS0
PD1_RXD0
17
16
26
1
3
V-
C1-
J10
C16
0.1 F
C29
T1OUT
11
T3OUT
T3IN
2
3
1
RESET
TXD0
C20
+
0.1
C23
22uF
U25
RTS0
21
R1IN
R2OUT
R2IN
R3OUT
R3IN
R4OUT
R4IN
R5OUT
R5IN
25
3.3V
2
VIN VOUT
GND
P2
1
6
2
7
3
8
4
9
5
R2OUTB
R1OUT
22/10
C22
PWR JACK
-RESET
SW4
3
1
INVALID
VCC
+ C19
S26
FORCEOFF
FORCEON
VCC
5V
3
0.1
D6
J13
C17
0.1uF
10
T2OUT
T2IN
OUT
HEADER 5
C2+
T1IN
IN
GND
V+
TXD0
CTS0
RXD0
RTS0
4
GND
5
6
CTS0
7
RXD0
VDD
VDD
+ C28
R15
LT1086-3.3/TO220
22/6.3
680
C29
D7
0.1
CONSOLE
GREEN
J15
3.3 OK
DB9 Female
8
1
2
GND
15
F1
RXE160
2
0.1
0.1
C1+
27
1
C15
24
U23
LM7805C/TO220/0.5A
2
C14
VCC
U22
28
1
2
3
4
5
C13
0.1 F
GND
-DIS_0
R17
10K
RS485_1_EN
MAX3245CAI
C21
U26
VDD
PD1_RXD0
0.1
C24
0.1
C25
24
1
0.1
2
PC0_TXD1
PC4_DTR1
PC2_RTS1
VDD
-MOD_DIS
R16
10K
RI1_B
PC7_RI1
RI1_NB
J14
1
2
3
Header 3
RI1_B
PC5_DSR1
RI1_NB
PC3_CTS1
PC1_RXD1
13
12
22
23
20
19
18
17
16
15
26
2
V+
V-
C1-
27
3
PD2_RTS0
3
PD0_TXD0
4
C26
RO
VCC
RE
B
DE
A
DI
GND
8
VCC
R23
7
C32
0.1uF
6
5
120
1
2
P4
0.1
0.1
C2T1IN
T1OUT
T2IN
T2OUT
T3IN
T3OUT
9
TXD1
10
DTR1
11
RTS1
PC1_RXD1
PC2_RTS1
INVALID
1
2
FORCEOFF
FORCEON
GND
RT_1
U27
PC0_TXD1
21
3
4
RO
VCC
RE
B
DE
A
DI
GND
8
7
5
1
2
3
4
5
6
7
8
con8
C18
0.1uF
6
R22
GND
120
J18
DS1487
R2OUTB
R1OUT
R1IN
R2OUT
R2IN
R3OUT
R3IN
R4OUT
R4IN
R5OUT
R5IN
4
DSR1
5
RI1
6
CTS1
7
RXD1
8
DCD1
25
P3
DCD1
DSR1
RXD1
RTS1
TXD1
CTS1
DTR1
RI1
1
6
2
7
3
8
4
9
5
1
2
J16
RT_2
1
2
MODEM
-DIS_1
RS485_2_EN
DB9 Male
R18
10K
MAX3245CAI
VCC
Figure 19. eZ80® Development Platform Schematic Diagram, #4 of 5
UM014103-0803
J17
DS1487
C27
C2+
GND
PC6_DCD1
14
C1+
VCC
U24
28
1
PRELIMINARY
eZ80F91 Development Kit
User Manual
65
MATES WITH AMP = 749268-1
P1
1
2
3
4
5
6
7
8
LENGTH = 5'
WIRES 28 AWG
Figure 20. eZ80® Development Platform Schematic Diagram, #5 of 5—RS-485 Cable
UM014103-0803
PRELIMINARY
eZ80F91 Development Kit
User Manual
eZ80190 Module
66
Figures 21 through 28 present the schematics of the eZ80190 Module.
X1
R13
-SLEEP
CLK_OUT
-MREQ
-WR
-RD
-CS0
-CS1
-CS2
-CS3
-RD
-CS[0..3]
-CS0 --> FLASH
-CS1 --> RAM
-CS2 --> ext. IO
-CS3 --> ETH
-MREQ
D[0..7]
A[0..23]
A8
A9
A10
A11
A12
A13
-BUSREQ
-BUSACK
-MREQ
don't
stuff
R30
0R
0603
PA[0..7]
MREQ
WR
RD
CS0
CS1
CS2
CS3
VDD
VSS
A0
A1
A2
A3
A4
A5
A6
A7
VDD
VSS
A8
A9
A10
A11
A12
A13
U1
eZ80190
TQFP100
PC[0..7]
TEST
PC7/RI1
PC6/DCD1
PC5/DSR1
PC4/DTR1
PC3/SS1/CTS1
PC2/SCK1/RTS1
PC1/SDA1/MOSI1/RxD1
PC0/SCL1/MISO1/TxD1
VSS
VDD
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ZDA
ZCL
RESET
IORQ
INSTRD
HALT
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ZDA
ZCL
-RESET
-IOREQ
-INSTRD
-HALT
PB[0..7]
PC[0..7]
PD[0..7]
ZDA
ZCL
-RESET
-IOREQ
R4
-NMI
R31
0R
0603
-INSTRD
-HALT
1k
0603
PB[0..7]
PC[0..7]
PD[0..7]
ZDA
ZCL
PB[0..7]
CLK_OUT
PC1
CLK_OUT
PA[0..7]
-NMI
-RESET
-IOREQ
-INSTRD
-HALT
-NMI
D0
D1
D2
D3
D4
D5
D6
D7
-BUSACK
50.000MHz, 3.3V
SG-710
A14
A15
VDD
VSS
A16
A17
A18
A19
A20
A21
A22
A23
VDD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VSS
NMI
-BUSREQ
PD[0..7]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A[0..23]
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC0
D[0..7]
1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
-WR
A14
A15
-CS[0..3]
OE
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD6
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
-BUSACK
0R R14
0603
-ACTIVE
OUT
4k7
0603
don't
stuff
-RD
3
PD7
0R R15
0603
-WR
XIN
A16
A17
A18
A19
A20
A21
A22
A23
-ACTIVE
PA[0..7]
PD4
-BUSREQ
-SLEEP
=
ETHIRQ
PHI
BUSREQ
VSS
VDD
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BUSACK
EXTAL
XTAL
VSS
VDD
PD7/RI0
PD6/DCD0
PD5/DSR0
PD4/DTR0
PD3/SS0/CTS0
PD2/SCK0/RTS0
PD1/SDA0/MOSI0/RxD0
PD0/SCL0/MISO0/TxD0
ETHIRQ
A[0..23]
D[0..7]
IICSDA
IICSCL
IICSDA
IICSCL
PA7
0R R32
0603
0R R33
0603
PA6
C18
1nF
0603
C19
1nF
0603
C20
1nF
0603
place caps close
to pins 97, 8, 38, 48
Figure 21. eZ80190 Module Schematic Diagram, #1 of 8—CPU
UM014103-0803
PRELIMINARY
Schematic Diagrams
eZ80F91 Development Kit
User Manual
67
U2
D[0..7]
A[0..23]
-CS1
-RD
-WR
D[0..7]
A21/ A22/ A23
not us ed her e
A[0..23]
-CS1
-RD
-WR
=
A18
A0
A1
A2
A3
-CSRAM
D0
D1
-CSRAM
D2
D3
-WR
A12
A9
A6
A4
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
N.C.
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
N.C.
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A20
A16
A15
A14
A13
-RD
D7
D6
D5
D4
A11
A8
A10
A7
A5
A19
D7
D6
D5
D4
D3
D2
D1
D0
10
9
8
7
6
5
4
3
2
RN1
1
9 x 4k7
SIP10
512kx8 fast SRAM
SOJ36.400
AS7C34096-10JC
V3.3
VDD
C1
100nF
0603
VSS
GND
Figure 22. eZ80190 Module Schematic Diagram, #2 of 8—36-Pin SRAM Device
UM014103-0803
PRELIMINARY
Schematic Diagrams
eZ80F91 Development Kit
User Manual
68
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Pi n37=N. C.
f or 4Mbi t Fl as hes
D[0..7]
A[0..23]
-RD
-WR
-CS0
-DIS_FLASH
-RESET
VDD
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
I nt el - Ty pe
U4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
25
26
27
28
32
33
34
35
DFLASH0
DFLASH1
DFLASH2
DFLASH3
DFLASH4
DFLASH5
DFLASH6
DFLASH7
CE
OE
WE
RP
WP
22
24
9
10
12
-CSFLASH
-RD
-WR
-RESFLASH
-WP
11
VPP
29
38
A21
A20
VPP
VSS
VSS
C2
100nF
0603
U3
23
39
A[0..23]
30
31
D[0..7]
N.C.
N.C.
2
5
6
9
10
15
16
19
20
23
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
3
4
7
8
11
14
17
18
21
22
1OE
2OE
1
13
D0
D1
D2
D3
D4
D5
D6
D7
-CSFLASH
74CBTLV3384
SO24.300
R5
0R 0603
A20/ A21 us ed f or
16/ 32Mbi t - Fl as h
Flash 1Mx8 3.3V
TSOP40.20MM
MT28F008B3VG
D[0..7]
A22/ A23
not us ed her e
A[0..23]
U5A
U6A
-CS0
1
-FLASH_EN
2
-RD
3
-DIS_FLASH
1
2
-CSFLASH
-WR
R6
10k
0603
-CS0
74LCX32
TSSOP14
74LCX04
TSSOP14
V3.3
-DIS_FLASH
VDD
-RESET
VSS
R7
10k
0603
= -RESFLASH
U6B
GND
-FLASHWE
-FLASHWE
-FLASHWE
Note: Must be pulled Low
externally for programming.
3
4
-WP
74LCX04
TSSOP14
Figure 23. eZ80190 Module Schematic Diagram, #3 of 8—NOR Flash Device
UM014103-0803
PRELIMINARY
Schematic Diagrams
eZ80F91 Development Kit
User Manual
69
R8
device addresses:
00300h bis 0030Fh
-ETHRD
-ETHWR
SD[0..7]
SA[0..3]
ETHIRQ
-SLEEP
-ACTIVE
5682F5;5
LED5682F
4k99/1%
0603
ESD protection array
U8
TXDTXD+
R2
RXD-
through-hole
solder pad
place near
FAST JACK
VDD
-ACTIVE
=
L1
-LANLED
GND
6
5
LCDA15C-6
SO8.150
CTD
JP4
HEADER 1
SIP1
do not
stuff
RDR3
100
0603
GND
CASE
TD+
8R2
0603
RXD+
VSS
3
C3
560pF
0603
8R2
0603
SD[0..7]
-SLEEP
7 TD-
TD-
-DIS_ETH
ETHIRQ
2
4
C4
100nF
0603
V3.3
RD-
i nt . Pul l - Up
R1
SA[0..3]
8 TD+
GND
-ETHRD
-ETHWR
SD[0..7]
RD+ 1
-SLEEP
TXD+
-ETHWR
lower LED
R12
TXD-
-ETHRD
R10
100
0603
green
-LINKLED
9
TQFP100
SD0
SD1
SD2
SD3
-DIS_ETH
CS8900A-CQ3
Y1
20.000 MHz
HC49
RXDRXD+
R9
100
0603
upper LED
J1
1
2
3
4
CRD 5
6
8
s hi el d
10
-DIS_ETH
U7
green
-LANLED
-LANLED
-LINKLED
1
SA[0..3]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
LANLED
LINKLED/HC0
XTAL2
XTAL1
AVSS
AVDD
AVSS
RES
RXDRXD+
AVDD
AVSS
TXDTXD+
AVSS
AVDD
DODO+
CICI+
DIDI+
BSTATU S/HC1
SLEEP
TEST
SD4
SD5
SD6
SD7
SA0
SA1
SA2
SA3
SD9
SD8
MEMW
MEMR
INTRQ2
INTRQ1
INTRQ0
IOCS16
MEMCS16
INTRQ3
SHBE
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
REFRESH
SA12
SA13
SA14
SA15
SA16
DVSS
DVDD
DVSS
SA17
SA18
SA19
IOR
IOW
AEN (TCK)
IOCHRDY
SD0
SD1
SD2
SD3
DVDD
DVSS
SD4
SD5
SD6
SD7
RESET
ETHIRQ
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
LD1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
R11
4k7
0603
Dual-LED assembly,
right angle, grn/grn
SD10
SD11
DVSS
DVDD
SD12
SD13
SD14
SD15
CSOUT
DMACK0
DMARQ0
DMACK1
DMARQ1
DMACK2
DMARQ2
DVSS
DVDD
DVSS
CHIPSEL
EEDATAIN
EEDATAOUT (TDO)
EESK
EECS
ELCS
AVSS
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10k
0603
RD+
C5
100nF
0603
C6
100nF
0603
plane or
big trace
CASE
HFJ11-1041(E)
HALOFASTJACK
TX+
TXRX+
RX-
<- >
<- >
<- >
<- >
1
2
3
6
CASE
ferrite
1210
do not stuff
Figure 24. eZ80190 Module Schematic Diagram, #4 of 8—Ethernet Module
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U9
D[0..7]
A[0..23]
-RD
-WR
-CS3
CLK_OUT
D[0..7]
D0
D1
D2
D3
D4
D5
D6
D7
A[0..23]
3
4
5
6
7
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
-RD
D[0..7]
-WR
-CS3
=
-ETHWR
-WR
-CSETH
13
14
11
-RD
2
1
23
-CSETH
-CSETH
22
21
20
19
18
17
16
15
B0
B1
B2
B3
B4
B5
B6
B7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD[0..7]
SA[0..3]
OEAB
LEAB
CEAB
A[0..23]
CSETH_P
SA[0..3]
SD[0..7]
OEBA
LEBA
CEBA
74LCX543
TSSOP24
-ETHRD
U10
-ETHWR
CLK_OUT
A0
A1
A2
A3
SD[0..7]
2
3
4
5
6
7
8
9
D1
D2
D3
D4
D5
D6
D7
D8
11
1
LE
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
SA0
SA1
SA2
SA3
-ETHRD
-ETHWR
SA[0..3]
74LCX573
TSSOP20
U5B
-RD
-CSETH1D
U6C
4
10
5
-CSETH1D
CLK_OUT
CLK
1
Q
6
74LCX74
TSSOP14
V3.3
12
11
PR
3
Q
D
R16
0R
0603
8
-ETHWR
U5C
-WR
9
U11B
Q
Q
-CSETH2D 10
9
CLK
CL
CLK_OUT
D
U11A
13
2
CL
-CSETH
-ETHRD
74LCX32
TSSOP14
don't
stuff
74LCX04
TSSOP14
6
5
CSETH_P
6
PR
5
4
8
R17
0R
0603
74LCX32
TSSOP14
V3.3
74LCX74
TSSOP14
V3.3
VDD
VSS
GND
Figure 25. eZ80190 Module Schematic Diagram, #5 of 8—Ethernet Module Logic
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power supervisor
3
V3.3
VDD
GND
RESET
1
C7
100nF
0603
U12
R 18
2k2
0603
-RESET
2
-RESET
open-drain
-RESET
C8
10nF
0603
M AX6328UR29
SO T-23-L3
alternative:
Maxim MAX6802UR29D3
real-time clock
Gold Cap
C9
0,1F
GOLDCAP_SD_V
R19
V3.3
100
0603
D1
TM M BAT 41
M IN IM ELF_AK
C 10
100nF
0603
RTC _VDD
RTC _VDD
R20
RTC _VDD
1
2
Y2
3
V+
GND
VBAT
U 13
8
VBAT
SD A
SCL
O SC I
OS CO
FT/OUT
4
32.7
68kHz
XTAL3
0R
0603
5
6
IIC SD A
II
CS CL
R21
4k7
0603
7
M 41T11M 6
SO 8.150
R 23
4k7
0603
R 22
4k7
0603
V3.3
IIC SD A
II
CS CL
C11
unpl
ace
0603
IIC SD A
II
CS CL
I2C bus address:
VD D
VSS
{D0} H /{D1} H
GND
Figure 26. eZ80190 Module Schematic Diagram, #6 of 8—Ethernet Module Peripherals
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72
A[0..23]
D[0..7]
-CS[0..3]
IICSDA
IICSCL
CLK_OUT
-DIS_FLASH
-FLASHWE
RTC_VDD
PB[0..7]
PC[0..7]
PD[0..7]
PA[0..7]
-DIS_ETH
-RESET
-RD
-WR
-IOREQ
-MREQ
-INSTRD
-HALT
-BUSREQ
-BUSACK
-NMI
ZDA
ZCL
A[0..23]
connector 1
connector 2
D[0..7]
JP1
-CS[0..3]
GND_EXT
A6
A10
GND_EXT
A8
A13
A15
A18
A19
A2
A11
A4
A5
-DIS_ETH
A21
A22
-CS0
-CS2
D1
D3
D5
D7
-MREQ
GND_EXT
-WR
-BUSACK
IICSDA
IICSCL
R24
CLK_OUT
33
-DIS_FLASH
EZ80CLK
0603
place near eZ80
output (PHI)
-FLASHWE
RTC_VDD
PB[0..7]
PC[0..7]
PD[0..7]
R25
10k
0603
PA[0..7]
-DIS_ETH
-RESET
-RD
-WR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
V3.3_EXT
A0
A3
V3.3_EXT
A7
A9
A14
A16
GND_EXT
A1
A12
A20
A17
-DIS_FLASH
V3.3_EXT
A23
-CS1
D0
D2
D4
GND_EXT
D6
-IOREQ
-RD
-INSTRD
-BUSREQ
PA7
PA5
PA3
PA1
V3.3_EXT
PB7
PB5
PB3
PB1
GND_EXT
PC6
PC4
PC2
PC0
PD6
PD5
PD3
PD1
GND_EXT
ZCL
RTC_VDD
IICSCL
IICSDA
-FLASHWE
-CS3
-RESET
V3.3_EXT
-HALT
V3.3_EXT
Header 30x2
-IOREQ
-MREQ
-INSTRD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Header 30x2
peripheral bus
connector
R26
2k2
0603
JP2
I/O connector
PA6
PA4
PA2
PA0
GND_EXT
PB6
PB4
PB2
PB0
PC7
PC5
PC3
PC1
PD7
GND_EXT
PD4
PD2
PD0
ZDA
EZ80CLK
GND_EXT
GND_EXT
GND_EXT
NOTUSED1
GND_EXT
-NMI
NC
Pin 50 open,
to be keyed
-HALT
-BUSREQ
-BUSACK
R27
10k
0603
-NMI
R28
10k
0603
R29
10k
0603
ZDA
ZCL
NOTUSED1
( * WAI T * )
V3.3
V3.3_EXT
GND_EXT
GND
Figure 27. eZ80190 Module Schematic Diagram, #7 of 8—Headers
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73
common power plane
V3.3
VDD
no power supply on board
Input: VDD ( = V3.3) = 3.3V ±5%
Power: Pmax = tbd
Ptyp = tbd
Current: lmax = tbd
ltyp = tbd
C12
22uF
SMT7343
C13
22uF
SMT7343
C14
1nF
0603
C15
100nF
0603
C16
1nF
0603
GND
C17
100nF
0603
VSS
common ground plane
PCB1
eZ80190 ethernet module board
98Cxxxx-xxx
U6D
U5D
12
9
8
11
13
74LCX32
TSSOP14
74LCX04
TSSOP14
unused gates
U6E
11
10
74LCX04
TSSOP14
U6F
13
12
74LCX04
TSSOP14
Figure 28. eZ80190 Module Schematic Diagram, #8 of 8—Power Supply
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Appendix A
General Array Logic Equations
This appendix shows the equations for disabling the Ethernet signals provided by the U10 and U15 General Array Logic (GAL) devices.
U10 Address Decoder
//`define idle
2'b00
//`define state1 2'b01
//`define state2 2'b11
//`define state3 2'b10
// FOR eZ80® Development Platform Rev B
// This PAL generates 4 memory chip selects
module l92_decod(
nCS_EX, //Enables Extension Module's Memory when Low
nFL_DIS,//when Low WEB Module Flash is disabled
(nDIS_FL=0),
//when High nDIS_FL depends upon state of
nmemenX
nCS0,
A7,
//A23
A6,
//A22
A5,
//A21
A4,
//A20
A3,
//A19
A2,
//A18
A1,
//A17
A0,
//A16
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nCS2,
nEX_FL_DIS,//disables Flash on the expansion module,
when Low
nEM_EN, //enables Development Platform LED and
//the general-purpose port.
nDIS_FL,//disables E-NET Module Flash when Low
nL_RD, //enables local data bus to be read by CPU
nmemen1,
nmemen2,
nmemen3,
nmemen4
);
input
nFL_DIS
nCS0
nCS2
A7
A6
A5
A4
A3
A2
A1
A0
nEX_FL_DIS
//input[7:0]A;
General Array Logic Equations
/* synthesis loc="P4"*/,
/* synthesis loc="P5"*/,
/* synthesis loc="P3"*/, //was 23
/* synthesis loc="P6"*/,
/* synthesis loc="P7"*/,
/* synthesis loc="P9"*/,
/* synthesis loc="P10"*/,
/* synthesis loc="P11"*/,
/* synthesis loc="P12"*/,
/* synthesis loc="P13"*/,
/* synthesis loc="P16"*/,
/* synthesis loc="P2"*/;
upper part of Address Bus of 190
//A23=A7,A22=A6,A21=A5,A20=A4,A19=A3
//A18=A2,A17=A1,A16=A0
PRELIMINARY
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output
nCS_EX
the
/* synthesis loc="P17"*/,//enables memory on
//Expansion Module
nmemen1 /* synthesis loc="P18"*/,//enables memory on
the
//Development Platform
nmemen2 /* synthesis loc="P19"*/,
nmemen3 /* synthesis loc="P20"*/,
nmemen4 /* synthesis loc="P21"*/,
nEM_EN /* synthesis loc="P24"*/,//enables LED and
the
//general-purpose port.
nDIS_FL /* synthesis loc="P25"*/,
nL_RD
/* synthesis loc="P23"*/
;
wire nCS_EX,
nmemen1,
nmemen2,
nmemen3,
nmemen4;
//wire MOD_DIS =
((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0
));//if any
//of the signals is Low,
//Flash on the Module will be
//disabled if nDIS_FL is High
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wire nEXP_EN = ~((nCS0==0)&(A7==0)&(A6==1));//
expansion module
//Flash enabled if this is 0
//wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS);
wire nDIS_FL = nFL_DIS & nEXP_EN; //if either of them
is 0 Flash is
//disabled
assign nCS_EX = (nEX_FL_DIS) ? nEXP_EN :
~(nEX_FL_DIS);
assign nL_RD =
~((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==
0)|(nEM_EN==0)|(nCS_EX==0));
assign nmemen4 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h17));
assign nmemen3 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h16));
assign nmemen2 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h15));
assign nmemen1 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h14));
assign nEM_EN =
~((nCS2==0)&({A7,A6,A5,A4,A3,A2,A1,A0}==8'h80));
endmodule
U15 Address Decoder
`define
anode
8'h00
`define
cathode 8'h01
`define
latch
8'h02
®
// FOR eZ80 Development Platform Rev B
General Array Logic Equations
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// This PAL generates signals that control Expansion
Module
// access, LED and the general-purpose port.
// This device is a GAL22LV10-5JC (5ns tpd) or
equivalent with
// Package = 28 pin PLCC
//
//
module l92_em_pal(
nDIS_EM,
nEM_EN,
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
nRD,
nCS,
nWR,
nMEMRQ,
nIORQ,
nEM_RD,
nEM_WR,
nAN_WR,
nCT_WR,
nDIS_ETH
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);
input
nEM_EN
A0
A1
A2
A3
A4
A5
A6
A7
nIORQ
nRD
nCS
nWR
nMEMRQ
nDIS_EM /* synthesis loc="P3"*/,
/* synthesis loc="P4"*/,
/* synthesis loc="P5"*/,
/* synthesis loc="P6"*/,
/* synthesis loc="P10"*/,
/* synthesis loc="P11"*/,
/* synthesis loc="P12"*/,
/* synthesis loc="P13"*/,
/* synthesis loc="P27"*/,
/* synthesis loc="P26"*/,
/* synthesis loc="P2"*/,
/* synthesis loc="P7"*/,
/* synthesis loc="P25"*/, //CS3 for CS9800
/* synthesis loc="P9"*/,
/* synthesis loc="P16"*/;
output
nEM_RD /* synthesis loc="P17"*/,
nEM_WR /* synthesis loc="P18"*/,
nCT_WR /* synthesis loc="P19"*/,
nAN_WR /* synthesis loc="P20"*/,
nDIS_ETH /* synthesis loc="P21"*/;
parameter anode=8'h00;
parameter cathode=8'h01;
parameter latch=8'h02;
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wire [7:0] address={A7,A6,A5,A4,A3,A2,A1,A0};
assign nEM_WR =
~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==latch
));
assign nEM_RD =
~((nDIS_EM==1)&(nRD==0)&(nEM_EN==0)&(address==latch
));
assign nAN_WR =
~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==anode
));
assign nCT_WR =
~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==catho
de));
assign nDIS_ETH = ~(nCS);
endmodule
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General Array Logic Equations
PRELIMINARY
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Customer Feedback Form
If you note any inaccuracies while reading this User Manual, please copy and complete this form,
then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions!
eZ80190 Development Kit
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Software Version
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Address
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