Download PDF file - finechips

CaImMAC1616
S3CC11B/FC11B
Extension Nibbles
Extension nibbles MA0E and MA1E in MSR1 register offer protection against 32-bit overflows. When the result of a
36-bit adder output crosses bit 31, it sets VMi flag of MSR1 register (MA register Overflow flag). Upto 15 overflows or
underflows are possible using the extension nibble, after which the sign is lost beyond the MSB of the extension
nibble, setting MV flag of MSR1 (Memorized Overflow flag) and latching the value.
Registers MA0E and MA1E can not be accessed independently. Those registers are read or written as a part of
MSR1 register, during MSR1 register read or write instruction.
Overflow Protection in MA Registers
The multiplier accumulator saturation instruction (ESAT instruction) sets the destination MA register to the plus or
minus maximum value, if selected MA register overflows (VMi bit of MSR1 register is set). Saturation values are
7FFFFFFFh (positive overflow) or 80000000h (negative overflow) for the MA register and extension nibble is signextended.
Another saturation condition is when moving from MAiH register through XB bus. This saturation mode is enabled
when selected MA register overflows (VMi bit at MSR1 register is set), and overflow protection bit is enabled (OPM
bit at MSR1 register is set). In this case the saturation logic will substitute a limited data value having maximum
magnitude and the same sign as the source register. The MA register value itself is not changed at all. Saturation
values are 7FFFh (positive overflow) or 8000h (negative overflow).
The last saturation condition is when enabling saturation on multiplier accumulators during arithmetic calculations
by setting the OPMA bit of MSR1 register. When overflow from the high portion of an MAi accumulator to the
extension bits occurs during MAi arithmetic operation and the OPMA bit is set, the accumulator is limited to a fullscale 32-bit positive (7FFFFFFFh) or negative (80000000h) value.
— Saturation by Instruction
: “ESAT” Instruction & VMi
— Sturation by MA Read
: Read MAiH & VMi & OPM
— Saturation by Arithmetic Operation
: Arithmetic Instruction on MAi & VMi & OPMA
15
0
Xi/Yi
X0/X1/Y0/Y1
Xi/Yi
31
1615
P
(PH)
35
MA0/MA1
32 31
PL
1615
0
MAi
MSR1_MAi
MA Guard Region
(MAiH)
Figure 21-3. MAU Registers Configuration
21-6
0
P
MAiL