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INTERRUPT STRUCTURE
S3F84UA/F84U8_UM_REV1.10
Table 5-1. Interrupt Vectors
Vector Address
Decimal
Value
Hex
Value
256
100H
206
Interrupt Source
Request
Reset/Clear
Interrupt
Level
Priority in
Level
H/W
Basic timer overflow
Reset
–
√
CEH
Timer A match/capture
IRQ0
0
208
D0H
Timer A overflow
210
D2H
Timer B match
212
D4H
216
√
1
√
IRQ1
–
√
Timer C match/overflow
IRQ2
–
√
D8H
Timer D0 match/capture
IRQ3
0
218
DAH
Timer D0 overflow
1
220
DCH
Timer D1 match/capture
2
222
DEH
Timer D1 overflow
3
228
E4H
SIO interrupt
230
E6H
Watch timer overflow
232
E8H
UART 0 data transmit
234
EAH
236
√
√
√
√
√
√
√
√
0
√
1
√
0
√
UART 0 data receive
1
√
ECH
UART 1 data transmit
2
√
238
EEH
UART 1data receive
3
√
240
F0H
P3.0 external interrupt
0
√
242
F2H
P3.1 external interrupt
1
√
244
F4H
P3.2 external interrupt
2
√
246
F6H
P3.3 external interrupt
3
√
248
F8H
P3.4 external interrupt
0
√
250
FAH
P3.5 external interrupt
1
√
252
FCH
P3.6 external interrupt
2
√
254
FEH
P3.7 external interrupt
3
√
IRQ4
IRQ5
IRQ6
IRQ7
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has
priority over one with a higher vector address. The priorities within a given level are fixed in hardware.
5-6
S/W