Download User`s Manual Dual Processor System Controller

Programming Model
FSMError
This bit signifies that the Main Finite State Machine in the MC has somehow reached an illegal
state. Results in a system reset.
PingPongError
This bit signifies that a serious error has occurred in the MC’s Ping-Pong buffer management.
Results in a system reset.
DPSError
This bit signifies that the DPS has somehow made an error in it’s handshake with the MC
regarding the Read or Write buffers in the BMX (i.e. - either it has acknowledged before the
BMX Read buffer was written or it acknowledged twice for one Read or it has written a second
time before the Write buffer has been emptied.) Results in a system reset.
MCError
This bit signifies that the MC has somehow made an error in it’s handshake with the DPS
regarding the Read or Write buffers in the BMX (i.e. - either it has overwritten the BMX Read
buffer or has prematurely read the BMX Write buffer or the BMX buffer FSMs have reached an
illegal state.) Results in a system reset.
MissedRefrError
This bit signifies that a refresh request has not been honored and that memory could be
corrupted. This could occur for example if a coherent write is issued and for some reason, the
handshake that the MC is waiting for signifying that the BMX Write Buffer has been filled,
never occurs. The MC will be stuck waiting and thus miss its refresh cycles. A separate
watchdog triggers this error. Results in a system reset.
PingPongError, DPSError, MCError, and MissedRefrError are all registers which once set,
remain set until either a system reset or they are individually reset by writing a one into them.
In any case, they are here mainly for debug and should never be set during normal operation.
Any one of these will have the MC request that the E-Bus Interface signal a fatal error and reset
the system.
RefrPhiMC
This bit will take the place of the RAS_Phi<0> bit (see Section 4.3.5.8) in the case of a Refresh
operation. This was necessary so that on reads we have the ability to drop RAS immediately.
Not having this bit would have precluded our ability to do CAS before RAS Refreshes.
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Dual Processor System Controller ASIC Specification
Sun Proprietary
February 1997