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Table 8-2
8.2.2.4
Interrupt Receiver State Register (Continued)
Level
Number of Interrupts
Source
6
6
Timer 0, Timer 1
PCI_B0_INTA#, PCI_B1_INTA#
PCI_B2_INTA#, PCI_B3_INTA#
5
6
OB Graphics, UPA64S Int
PCI_A0_INTB#, PCI_A1_INTB#
PCI_A0_INTC#, PCI_A1_INTC#
4
6
Keyboard Int, Mouse Int
PCI_B0_INTB#, PCI_B1_INTB#
PCI_B2_INTB#, PCI_B3_INTB#
3
6
SCSI Int, Ethernet Int
PCI_B0_INTC#, PCI_B1_INTC#
PCI_B2_INTC#, PCI_B3_INTC#
2
4
Parallel Port, Spare Int
PCI_A0_INTD#, PCI_A1_INTD#
1
5
Power Management
PCI_B0_INTD#, PCI_B1_INTD#
PCI_B2_INTD#, PCI_B3_INTD#
Synchronization with DMA writes
When the end of a DMA write operation is signalled to software via an interrupt,
U2P guarantees that all the DMA write data will actually be written to memory
before the interrupt is seen. In order for this to happen, the MDU and PBM blocks
communicate for any interrupt that is coming from a PCI source. Just before the
MDU block dispatches any PCI interrupt request, it notifies the appropriate PBM
block that an interrupt is pending. If there is any buffered DMA write data in the
PBM, it will stall the MDU until that write data has been sent to the UPA block of
U2P. New DMA write data that comes in while waiting for old data to flush will not
cause additional stalling.
Onboard IO devices are considered to be PCI bus B sources.
8.2.3
Interrupt Table
Table 8-3 summarizes all of the interrupts that U2P handles. For each interrupt, the
source, type, priority and any synchronization of the interrupt is listed. For external
interrupts, the value of the INT_NUM bus from the external concentrator that will
cause that interrupt is listed (this will not in general match the INO). Also included
is the name of the pin on the RIC ASIC which will cause the correct INT_NUM to be
Chapter 8
Mondo Dispatch Unit
8-9