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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4)
Serial interface operation enable/disable specification bit (W)
Shift register
operation
CSIE
Serial clock
counter
IRQCSI
flag
SO/SB0 and
SI/SB1 pins
0
Shift operation
disabled
Cleared
Held
Used only for port 0
1
Shift operation
enabled
Count operation
Can be set.
Used in each mode as well
as for port 0
Signal from address comparator (R)
COINote
Condition for being cleared (COI = 0)
When the data in the slave address
register (SVA) does not match the data
in the shift register
Condition for being set (COI = 1)
When the data in the slave address register
(SVA) matches the data in the shift
register
Note COI can be read only before serial transfer is started or after serial transfer is completed. An
undefined value may result during transfer.
COI data written by an 8-bit manipulation instruction is ignored.
Wake-up function specification bit (W)
WUP
0
Sets IRQCSI each time serial transfer is completed in each mode.
1
Used in the SBI mode only to set IRQCSI only when an address received after bus release
matches the data in the slave address register (wake-up state). SB0 or SB1 goes to highimpedance state.
Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode,
the BUSY signal is output until the next falling edge of the serial clock (SCK) appears after
release of BUSY is directed. Before setting WUP = 1, be sure to confirm that pin SB0 (or
SB1) is high after releasing BUSY.
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