Download uPD750108 User`s Manual

CHAPTER 4 INTERNAL CPU FUNCTIONS
Figure 4-14. Data Saved to the Stack Memory (Mk II Mode)
PUSH instruction
CALL, CALLA, or CALLF instruction
Interrupt
Stack
Stack
Stack
SP – 6
SP – 6
PC11 - PC8
Note 1
0
SP – 5
0
0
PC11 - PC8
Note 2
PC12
0
SP – 5
0
Note 1
Note 2
0
PC12
SP – 2 Lower bits of pair register
SP – 4
PC3 - PC0
SP – 4
PC3 - PC0
SP – 1 Upper bits of pair register
SP – 3
PC7 - PC4
SP – 3
PC7 - PC4
SP
SP – 2
*
MBE RBE
*
Note 3
SP – 1
*
*
*
*
SP
SP – 2 IST1 IST0 MBE RBE
PSW
SP – 1 CY SK2 SK1 SK0
SP
Figure 4-15. Data Restored from the Stack Memory (Mk II Mode)
SP
POP instruction
RET or RETS instruction
RETI instruction
Stack
Stack
Stack
Lower bits of pair register
SP
PC11 - PC8
Note 1
0
0
SP
PC11 - PC8
Note 1
Note 2
0
SP + 1
SP + 2
SP + 2
PC3 - PC0
SP + 2
PC3 - PC0
SP + 3
PC7 - PC4
SP + 3
PC7 - PC4
SP + 4
*
*
0
SP + 1
0
SP + 1 Upper bits of pair register
PC12
MBE RBE
Note 3
SP + 5
SP + 6
*
*
*
*
0
Note 2
PC12
SP + 4 IST1 IST0 MBE RBE
PSW
SP + 5 CY SK2 SK1 SK0
SP + 6
Notes 1. For the µPD75P0116, PC13 is entered instead of 0.
2. For the µPD750104, 0 is entered instead of PC12.
3. PSW bits other than MBE and RBE are not saved or restored.
Remark * indicates an undefined bit.
User’s Manual U11330EJ2V1UM00
63