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CDP1802A, CDP1802AC, CDP1802BC
Pinouts
36 INTERRUPT
SC0
6
35 MWR
MRD
7
34 TPA
BUS 7
8
33 TPB
INTERRUPT
5
DMA-OUT
37 DMA OUT
SC1
6
5
4
3
2
1 44 43 42 41 40
XTAL
38 DMA IN
4
VDD
3
Q
NC
CLEAR
CLOCK
39 XTAL
WAIT
40 VDD
2
CLEAR
1
WAIT
Q
CLOCK
DMA-IN
44 LEAD PLCC
(PACKAGE TYPE Q)
TOP VIEW
SC1
40 LEAD PDIP (PACKAGE SUFFIX E)
40 LEAD SBDIP (PACKAGE SUFFIX D)
TOP VIEW
SC0
7
39
MWR
MRD
8
38
TPA
BUS 7
9
37
TPB
BUS 6
10
36
MA7
9
32 MA7
BUS 5 10
31 MA6
BUS 4 11
30 MA5
BUS 5
11
35
MA6
BUS 3 12
29 MA4
NC
12
34
NC
BUS 2 13
28 MA3
BUS 4
13
33
MA5
BUS 1 14
27 MA2
BUS 3
14
32
MA4
BUS 0 15
26 MA1
BUS 2
15
31
MA3
BUS 1
16
30
MA2
BUS 0
17
29
MA1
25 MA0
MA0
EF1
EF2
21 EF4
EF3
22 EF3
EF4
N0 19
VSS 20
18 19 20 21 22 23 24 25 26 27 28
NC
23 EF2
VSS
N1 18
N0
24 EF1
N1
N2 17
N2
VCC 16
VCC
BUS 6
ADDRESS BUS
CDP1852
INPUT PORT
CS2
CS1
N0 MA0-7
MRD
CDP1802
8-BIT CPU
MA0-7
MRD
CDP1833
1K-ROM
MWR
DATA
N1
CS1
CDP1852
CS2
OUTPUT
PORT CLOCK
TPA
TPB DATA
MRD
CDP1824
32 BYTE RAM
MWR
TPA
CEO
DATA
FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM
3-4
MA0-4
CS