Download EFM01 - CESYS GmbH

FPGA design
WE_O
WE_O
ADR_O[31:0]
ADR_O[31:0]
DAT_O[31:0]
DAT_O[31:0]
A>>2
A>>2
A>>2
A>>2
D
D
D
DAT_I[31:0]
DAT_I[31:0]
ACK_I
ACK_I
WISHBONE MASTER
STB_O
STB_O
WISHBONE MASTER

CLK
CLK
Figure 9:
and
8: WISHBONE transactions with WriteRegister()
ReadRegister() and
WriteBlock()
ReadBlock()
The WISHBONE signals in these illustrations and explanations are shown as simple bit
types or bit vector types, but in the VHDL code these signals could be encapsulated in
extended data types like arrays or records.
Example:
...
port map
(
...
ACK_I => intercon.masters.slave(2).ack,
...
Port ACK_I is connected to signal ack of element 2 of array slave, of record masters, of
record intercon.
Design “efm01_perf”
This design is intended to demonstrate behavior of low level slave FIFO controller entity
fx2_slfifo_ctrl. It handles the FX-2 slave FIFO interface. It can be synthesized in
two modes, data loopback mode and infinite data source/sink mode with 16 bit counting
data source. Ports of fx2_slfifo_ctrl connected to FX-2 are labeled with prefix
fx2_ and ports connected to user logic are labeled with prefix app_. Sometimes the
UG110 (v1.2) April 07, 2014
www.cesys.com
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