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APPENDIX D LIST OF CAUTIONS
STOP mode
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware
that operates on the low-speed Ring-OSC clock).
p.235
STOP mode,
HALT mode
The following sequence is recommended for operating current reduction of the p.235
A/D converter when the standby function is used: First clear bit 7 (ADCS) and
bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D
conversion operation, and then execute the HALT or STOP instruction.
STOP mode
If the low-speed Ring-OSC oscillator is operating before the STOP mode is
set, oscillation of the low-speed Ring-OSC clock cannot be stopped in the
STOP mode (refer to Table 14-1).
p.235
OSTS:
Oscillation
stabilization time
select register
To set and then release the STOP mode, set the oscillation stabilization time
as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization
time set by OSTS
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The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
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The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER
18 OPTION BYTE.
p.236
Hard
Soft
p.234
Chapter
Soft
Chapter 14
Page
The LSRSTOP setting is valid only when “Can be stopped by software” is set
for the low-speed Ring-OSC oscillator by the option byte.
Hard
Chapter 15
−
Cautions
Hard
Standby
function
Details of
Function
Soft
Classification
(14/18)
Function
Reset
function
Settings and
operating
statuses in HALT
mode
Because an interrupt request signal is used to clear the standby mode, if there p.237
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set.
Settings and
operating
statuses in STOP
mode
Because an interrupt request signal is used to clear the standby mode, if there p.240
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set. Thus, in the STOP
mode, the normal operation mode is restored after the STOP instruction is
executed and then the operation is stopped for 34 µs (TYP.) (after an
additional wait time for stabilizing the oscillation set by the oscillation
stabilization time select register (OSTS) has elapsed when crystal/ceramic
oscillation is used).
−
For an external reset, input a low level for 2 µs or more to the RESET pin.
p.244
During reset signal generation, the system clock and low-speed Ring-OSC
clock stop oscillating.
p.244
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KB1+ p.244
is reset if a low level is input to the RESET pin after reset is released by the
POC circuit and before the option byte is referenced again. The reset status is
retained until a high level is input to the RESET pin.
Timing of reset by
overflow of
watchdog timer
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
p.245
The watchdog timer is also reset in the case of an internal reset of the
watchdog timer.
p.247
Preliminary User’s Manual U17446EJ1V0UD
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