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UM10601
NXP Semiconductors
Chapter 8: LPC800 Pin interrupts/pattern match engine
The pattern match logic continuously monitors the eight inputs and generates interrupts
when any one or more minterms (product terms) of the specified boolean expression is
matched. A separate interrupt request is generated for each individual minterm.
In addition, the pattern match module can be enabled to generate a Receive Event
(RXEV) output to the ARM core when the entire boolean expression is true (i.e. when any
minterm is matched).
The RXEV output is also be routed to GPIO_INT_BMAT pin. This allows the GPIO module
to provide a rudimentary programmable logic capability employing up to eight inputs and
one output.
The pattern match function utilizes the same eight interrupt request lines as the pin
interrupts, so these two features are mutually exclusive as far as interrupt generation is
concerned. A control bit is provided to select whether interrupt requests are generated in
response to the standard pin interrupts or to pattern matches. Note that, if the pin
interrupts are selected, the RXEV request to the CPU can still be enabled for pattern
matches.
Remark: Pattern matching cannot be used to wake the part up from power-down modes.
Pin interrupts must be selected in order to use the pins for wake-up.
8.5.2.2 Boolean expressions
The pattern match module is constructed of eight bit-slice elements. Each bit slice is
programmed to represent one component of one minterm (product term) within the
boolean expression. The interrupt request associated with the last bit slice for a particular
minterm will be asserted whenever that minterm is matched.
(See bit slice drawing Figure 8).
The pattern match capability can be used to create complex software state machines.
Each minterm (and its corresponding individual interrupt) represents a different transition
event to a new state. Software can then establish the new set of conditions (that is a new
boolean expression) that will cause a transition out of the current state.
Example:
Assume the expression: (IN0)~(IN1)(IN3)^ + (IN1)(IN2) + (IN0)~(IN3)~(IN4) is specified
through the registers PMSRC (Table 91) and PMCFG (Table 92). Each term in the
boolean expression, (IN0), ~(IN1), (IN3)^, etc., represents one bit slice of the pattern
match engine.
• In the first term (IN0)~(IN1)(IN3)^, bit slice 0 monitors for a high-level on input (IN0),
bit slice 1 monitors for a low level on input (IN1) and bit slice 2 monitors for a
rising-edge on input (IN3). If this combination is detected, that is if all three terms are
true, the interrupt associated with bit slice 2 will be asserted.
• In the second term (IN1)(IN2), bit slice 3 monitors input (IN1) for a high level, bit slice
4 monitors input (IN2) for a high level. If this combination is detected, the interrupt
associated with bit slice 4 will be asserted.
• In the third term (IN0)~(IN3)~(IN4), bit slice 5 monitors input (IN0) for a high level, bit
slice 6 monitors input (IN3) for a low level, and bit slice 7 monitors input (IN4) for a low
level. If this combination is detected, the interrupt associated with bit slice 7 will be
asserted.
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 24 January 2013
© NXP B.V. 2013. All rights reserved.
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