1
Download 8XC196NT Microcontroller User`s Manual
Transcript
8XC196NT USER’S MANUAL The EPA0–EPA3 pending bits are located in INT_PEND (Figure 5-7 on page 5-17). The pending bits for the multiplexed interrupts (those that share EPAx) are located in EPA_PEND (Figure 10-14) and EPA_PEND1 (Figure 10-15). If an interrupt is masked, software can still poll the interrupt pending registers to determine whether an event has occurred. Address: Reset State: EPA_PEND 1FA2H 0000H When hardware detects a pending EPAx interrupt, it sets the corresponding bit in the EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared. 15 8 EPA4 EPA5 EPA6 EPA7 EPA8 EPA9 OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVR8 OVR9 7 0 Bit Number 15:10 Function Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is cleared when the EPA interrupt priority vector register (EPAIPV) is read. Figure 10-14. EPA Interrupt Pending (EPA_PEND) Register Address: Reset State: EPA_PEND1 1FA6H 00H When hardware detects a pending EPAx interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared. 7 0 — — — — Bit Number COMP0 COMP1 OVRTM1 OVRTM2 Function 7:4 Reserved; always write as zeros. 3:0 Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is cleared when the EPA interrupt priority vector register (EPAIPV) is read. Figure 10-15. EPA Interrupt Pending 1 (EPA_PEND1) Register 10-28
