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Freescale Semiconductor, Inc.
Application Note
Programming Voltage Supply Considerations
Programming Voltage Supply Considerations
Programming
Voltage Supply
Envelope
The key to preventing damage to the FLASH array or corruption of the
data contained in the memory is the programming voltage envelope
shown in Figure 9. Many of the problems that customers experience
with FLASH devices are due to a failure to ensure that their voltage
sources always meet these requirements.
Freescale Semiconductor, Inc...
The most important single thing to remember from this diagram is that
VFP and VDD should always be at the same level, except during an
actual program or erase cycle. Corruption of FLASH data is often
encountered when VFP is allowed to exceed VDD during the power-up
and power-down phases.
Conversely, if VFP is allowed to fall below .35 volts lower than VDD at any
time, damage to the FLASH array can occur.
30 ns MAXIMUM
13.5 V
12.6 V
VFP ENVELOPE
11.4 V
VDD ENVELOPE
COMBINED VDD AND VFP
tER
5.5 V
4.5 V
4.15 V
0V
–0.30 V
POWER
UP
NORMAL
READ
PROGRAM
ERASE
POWER
DOWN
Figure 9. Programming Voltage Envelope
NOTE:
Although Figure 9 shows a lower boundary of 4.15 volts on VFP during
the normal read phase, VFP always must be no more than .35 volts
below VDD. For example, If the operating voltage of VDD in the system is
5.2 volts, VFP can be no lower than 4.85 volts.
AN1836
21
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