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S3C2500 (Preliminary Spec) GDMA CONTROLLER 12.6.2 SINGLE AND FOUR DATA BURST MODE (DCON[3:1] = 001, [4] = 0, [5] = 1) xGDMA_Req & xGDMA_Ack signals are active high. In four data burst mode, GDMA transfers four data and GDMA Transfer Count Register (DTCR) value decreases by four. But if the value of transfer count register is not a multiple of 4 times transfer size, the last misaligned data can be transferred by one data. Recommand deasserted time HCLK xGDMA_Req Address Data DTCR NOTE: ~ ~ xGDMA_Ack Programmable by DCON[16:13] SA0 SA1 SA2 SA3 DA0 DA1 DA2 DA3 SD0 SD1 SD2 SD3 DD0 DD1 DD2 DD3 N N-4 Address order is source address0 -> source address1 -> source address 2 -> source address3 -> destination address0 -> destination address1 -> destination address2 -> destination address3, and Data order is source data0 -> source data1 -> source data2 -> source data3 -> destination data0 -> destination data1 -> destination data2 -> destination data3. Figure 12-12. Single and Four Data Burst Mode Timing 12-21
