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Chapter 5 I/O Bridges
5–1.
All PHB implementations must be compliant with the PCI Local Bus
Specification, revision level 2.1 [14].
5–2.
All requirements defined in Chapter 3, “System Address Map,” on
page 23 for HBs must be implemented by all PHBs in the platform.
5–3.
HB0 must be a PHB (PHB0).
5–4.
PHB implementations which include buffers or queues for DMA, Load,
and Store operations must make sure that these are transparent to the
software, with a few exceptions which are allowed by the PCI architecture, by the PowerPC architecture, and in Section 4.2.2.1, “Memory Coherence,” on page 57.
5–5.
A Load or Store to either the Peripheral Memory Space or the Peripheral
I/O Space of a PHB must never be passed to the I/O bus before a previous Store to either the Peripheral Memory Space or the Peripheral I/O
Space of that same PHB (that is, multiple Stores to the I/O bus generated
by one PHB must be kept in order and a Load must not pass a Store).
5–6.
A Load to either the Peripheral Memory Space or the Peripheral I/O
Space of a PHB must never be passed to the I/O bus before a previous
Load to either the Peripheral Memory Space or the Peripheral I/O Space
of that same PHB when both of those Loads go to the exact same address.
5–7.
Data from a DMA read completion must be allowed to complete prior to
Load or Store operation which was previously queued in the PHB, in order to prevent a possible deadlock.
5–8.
Load data buffered in a PHB must not prevent a subsequent DMA write
request from being posted into the PHB or from making progress
through the PHB, in order to prevent a possible deadlock on the PCI bus.
5–9.
A DMA write or read request from an I/O device to the processor side of
the PHB must never be passed to the processor side of the PHB before
the data from a previous I/O DMA write operation has been flushed to
the processor side.
5–10. A previous DMA read request accepted by a PHB but not yet completed
must not prevent a subsequent DMA write request from being posted
into the PHB or from making progress through the PHB, in order to prevent a possible deadlock on the PCI bus.
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