Download M16C/6B Group User`s Manual: Hardware

M16C/6B Group
14. A/D Converter (64-Pin Version Only)
A/D Control Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
ADCON2
0 0
After Reset
0000X00Xb
Bit Name
Bit Symbol
—
(b0)
Address
03D4h
Function
RW
No register bit. If necessary, set to 0. Read as undefined value.
—
(b2-b1)
—
(b3)
CKS2
—
(b7-b5)
Reserved bits
—
Set to 0
RW
No register bit. If necessary, set to 0. Read as undefined value.
—
Frequency select bit 2 (2)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4
1: Selects fAD divided by 3, fAD divided by 6
RW
Reserved bits
Set to 0
RW
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. φAD frequency is selected by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in
the ADCON1 register, and the CKS2 bit in the ADCON2 register.
φAD
CKS2
CKS1
CKS0
0
0
0
fAD divided by 4
0
0
1
fAD divided by 2
0
0
1
1
0
1
fAD
1
1
0
1
1
0
1
1
1
fAD divided by 6
fAD divided by 3
A/D Register i (i = 0 to 7)
(b15)
b7
(b8)
b0 b7
0
b0
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address
03C1h to 03C0h
03C3h to 03C2h
03C5h to 03C4h
03C7h to 03C6h
03C9h to 03C8h
03CBh to 03CAh
03CDh to 03CCh
03CFh to 03CEh
After Reset
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
Function
RW
Eight low-order bits of A/D conversion result
RO
Two high-order bits of A/D conversion result
RO
No register bits. If necessary, set to 0. Read as undefined value.
—
Reserved bit
RO
Set to 0
NOTE:
1. Use the MOV instruction to write to this register.
Figure 14.3
Registers ADCON2 and AD0 to AD7
R01UH0197EJ0120 Rev.1.20
Jul 21, 2011
Page 180 of 331