Download Atheros AR9331

PRELIMINARY
6.17.31 Tx Frame Counter (MAC_PCU_TX_FRAME_CNT)
Offset: 0x181080EC
Access: Hardware = Read/Write
Software = Read/Write
Reset Value: 0x0
Bit
Name
31:0
TX_FRAME_CNT
The Tx frame counter counts the number of
cycles the TX_FRAME signal is active.
Description
Counts the number of cycles the TX_FRAME signal is active
6.17.32 Rx Frame Counter (MAC_PCU_RX_FRAME_CNT)
Offset: 0x181080F0
Access: Hardware = Read/Write
Software = Read/Write
Reset Value: 0x0
Bit
Name
31:0
RX_FRAME_CNT
The receive frame counter counts the number
of cycles the RX_FRAME signal is active.
Description
Counts the number of cycles the RX_FRAME signal is active
6.17.33 Rx Clear Counter (MAC_PCU_RX_CLEAR_CNT)
Offset: 0x181080F4
Access: Hardware = Read/Write
Software = Read/Write
Reset Value: 0x0
Bit
Name
31:0
RX_CLEAR_CNT
The receive clear counter counts the number of
cycles the RX_CLEAR signal is not active.
Description
Counts the number of cycles the RX_CLEAR signal is low
6.17.34 Cycle Counter (MAC_PCU_CYCLE_CNT)
Offset: 0x181080F8
Access: Hardware = Read/Write
Software = Read/Write
Reset Value: 0x0
Bit
Name
31:0
CYCLE_CNT
The cycle counter counts the number of clock
cycles.
Description
Counts the number of clock cycles
6.17.35 Quiet Time 1 (MAC_PCU_QUIET_TIME_1)
Offset: 0x181080FC
Access: Hardware = Read-Only
Software = Read/Write
Reset Value: 0x0
Bit
Name
31:18
RES
17
Description
Reserved
QUIET_ACK_CTS_ENABLE If set, then the MAC sends an ACK or CTS in response to a received frame
16:0
168
168
The Quiet Time registers implement the quiet
time function specified in the proposed 802.11h
extension supporting radar detection.
RES
•
•
Reserved
AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms
December 2010
Atheros Communications, Inc.
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