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PRELIMINARY
6.22.22 MDIO Control
Address: 0x0098
Access: Read/Write
Reset: 0x0
This register is used to control the functions of
the MDIO interface.
Bit
Bit Name
Description
31
MDIO_BUSY
Writing a one to this bit represents the internal MDIO interface as busy. This
bit should be set when the CPU reads or writes to the PHY register through the
internal MDIO interface, and should be cleared after the hardware finishes this
command
30
MDIO_
MASTER_EN
Writing a 1 to this bit enables the MDIO master which is used to configure the
PHY register. MDC should change to the internal MDC to PHY
29:28
RES
27
MDIO_CMD
Reserved. Must be written with zero. Contains zeros when read.
This bit represents the commands given for the MDIO
0
Write
1
Read
26
MDIO_SUP_ PRE
25:21
PHY_ADDR
These bits represent the PHY address
20:16
REG_ADDR
These bits represent the PHY register address
15:0
MDIO_DATA
When write, these bits are data written to the PHY register. When read, these
bits are read out from the PHY register
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Writing a 1 to this bit enables the supposed preamble
AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms
December 2010
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