Download ModelSim SE User`s Manual

VHDL matching 11-314
wave window display 11-316
waveforms 11-301
write report 11-320
compare by region 11-311
compare commands 11-323
compare simulations 7-137
compare waveforms 7-137, 8-228
comparison modes 11-303
comparison wizard 11-318
Compilation and Simulation
Verilog 5-73–5-126
VHDL 4-55–4-67
Compiler directives 5-106
IEEE Std 1364-2000 5-106
XL compatible compiler directives 5-106
Compiling
invoking the VHDL compiler 4-57
locating source errors 8-251
setting default options 8-252
setting options in projects 2-35
setting order in projects 2-34
Verilog
incremental compilation 5-76
optimizing performance 5-90
XL ’uselib compiler directive 5-81
XL compatible options 5-79
Verilog compile options 8-254
VHDL 4-57
VHDL compile options 8-252
with the graphic interface 8-250
with VITAL packages 4-67
Component declaration
generating VHDL from Verilog 6-134
with vgencomp 6-134
Concatenation of signals 7-147
ConcurrentFileLimit .ini file variable B-399
configuration simulator state variable B-408
context menus
coverage_source window 10-296
described 8-154
Library page 3-45
Signal window 8-198
Structure pages 7-140
continuous comparison 11-303, 11-310
convert real to time 4-71
convert time to real 4-70
coverage report command 10-300
coverage_summary window 10-292
cursors
link to Dataflow window 8-171
ModelSim SE User’s Manual
Wave window 8-239
D
Dataflow window (see also, Windows) 8-171
Dataset Browser 7-142
datasets 7-137, 11-302
managing 7-142
reference 11-305
restrict dataset prefix display 7-143
simulator time resolution 7-138
specifying for compare 11-305
test 11-305
DatasetSeparator .ini file variable B-399
Default compile options 8-252
DefaultForceKind .ini file variable B-399
DefaultRadix .ini file variable B-399
DefaultRestartOptions .ini file variable B-399, B-405
Defaults
restoring B-392
Delay
detecting infinite zero-delay loops E-436
interconnect 5-86
modes for Verilog models 5-97
SDF files 12-325
specifying stimulus delay 8-197
DelayFileOpen .ini file variable B-399
deleting library contents 3-44
Delta
collapse deltas in the List window 8-179
referencing simulator iteration
as a simulator state variable B-408
Delta cycles E-436
delta simulator state variable B-408
Dependent design units 4-57
Descriptions of HDL items 8-208
Design hierarchy
viewing in Structure window 8-210
Design library
assigning a logical name 3-47
creating 3-43
for VHDL design units 4-57
mapping search rules 3-48
resource type 3-42
working type 3-42
Design units 3-42
viewing hierarchy 8-155
Directories
moving libraries 3-49
See also, Libraries
Index - 470