1
Download VINETIC
Transcript
VINETIC® Application Circuits VHRA VDDA C1S C 1S VBATLA VBATH VBATLB C 1S C1S VDD18 VDD18 VDD18 C 1S C1V BGND AGND BGND BGND BGND D D D D D C1V C 1V VDD18 C 1V VDD33 VDD33 VDD33 C1V C1V C1V AGND AGND AGND AGND AGND AGND AGND VDD18A VDD18AB VDD18 VDD18P VDD33A VDD33AB VDD33 VHRA VDDA VBATLA VBATH VBATLB ACPA ACNA DCPA DCNA C1A C2A Overvoltage Protection RSTAB 30 R PROT 20 TIPfuseable resistor ACPA ACNA DCPA DCNA C1A C2A TIPA C DC C STAB Tip TSLIC-E TSLIC-S U1 CITACA ITA BGND Ring R PROT 20 fuseable resistor R STAB 30 CDCNA CDCPA CPRE ITA R IT2A Parallel or serial Interface VINETIC-x VCMITA only channel A and SLIC interface pins connected for this example R ILA CSTAB RING PCM Interface ITACA R IT1A (Channel A, B) only channel A connected for this example Channel A RINGA ILA ILA GPIO0 ... GPIO7 VCMAB VCMSA PEB 4365 PEB 4364 BGND A AGND A BGND AGND CREF IO0A ... IO4A 8 5 VREFAB CREFAB PEB 33xy GNDAB CEXTA C EXT AGND AGND GND A GND GNDP AGND AGND AGND ezm14042V_T_ES Figure 15 Application Circuit Internal Ringing (balanced) for TSLIC-E/-S Preliminary Product Overview 66 Rev. 2.0, 2004-05-11
