Download Tamarisk 640 Electrical Interface Control Document

Tamarisk
®
640
Electrical ICD
Data is driven on BDSI_D9 through BDSI_D0 (10 bits). The data is binary format. BDSI_PCLK,
provides the single ended clock for the D/A conversion at 27 MHz. Example timing is shown in
Figure 14 and Figure 15 for PAL mode, and Figure 16 and Figure 17 for NTSC mode.
1728 Clocks per Line
37
ns
BDSI_PCLK(27MHz)
BDSI_DATA(9:0)
1727
1728
1
2
3
4
5
6
7
9
1403
1404
1405
1406
1726
1727
1728
324 Clocks of Horizontal
Blanking
1404 Clocks of Pixels per line
Figure 14: Parallel RS-170 PAL Video Horizontal Timing Diagram
25 Lines
Vertical
Blanking
25 Lines
Vertical
Blanking
Odd Field Lines
BDSI_DATA(9:0)
Row
1
Row
480
Even Field Lines
H Blanking
H Blanking
ROW
573
Row
7
Row
5
Row
3
Row
2
ROW
575
Row
4
Row
6
ROW
576
ROW
574
Row
8
240
240
BDSI_PCLK(27MHz)
Figure 15: Parallel RS-170 PAL Video Vertical Timing Diagram
1716 Clocks per Line
37
ns
BDSI_PCLK(27MHz)
BDSI_DATA(9:0)
1715
1716
1
2
3
4
5
6
7
9
1407
1408
1409
1410
1714
1715
1716
308 Clocks of Horizontal
Blanking
1408 Clocks of Pixels per line
Figure 16: Parallel RS-170 NTSC Video Horizontal Timing Diagram
22.5 Lines
Vertical
Blanking
22.5 Lines
Vertical
Blanking
Odd Field Lines
H Blanking
BDSI_DATA(9:0)
Row
480
Row
1
Row
3
Even Field Lines
H Blanking
Row
5
Row
7
240
Row
477
Row
479
Row
2
Row
4
Row
6
Row
8
Row
478
Row
480
240
BDSI_PCLK(27MHz)
Figure 17: Parallel RS-170 NTSC Video Vertical Timing Diagram
In YUV_SuperFrame mode the Parallel Digital Video Interface is formatted with 2560 bytes per
line and 480 lines per frame. The format of Parallel Digital Video Interface is shown in Figure 18
and Figure 19. Each line contains 640 Y values (one per pixel) interleaved with 320 Cb and 320
Cr values (Cb and Cr are calculated over 2 adjacent pixels) followed by the Pre-AGC data for the
20