Download Atari ST System-on-Chip in VHDL (Author: Lyndon Amsdon) [undated]

signals within the FPGA and how difficult it could be in very high speed FPGA designs
[31].
5.19
DMA IP Core
At this point the DMA IP Core was added. The requirement for the DMA to take over
and master the system bus required quite a large change to the way the components were
connected together at the top level. Instead of just the CPU driving the control signals for
bus cycles ( AS , R/ W , UDS and LDS ) the Glue also needs to be able to drive these
signals. Even on a DMA bus cycle, it is the Glue that drives the control signals and does
the bus arbitration with the CPU. The MMU also helps out by providing the address and
DMA counter. It’s at this point that you realise how closely linked all the custom
semiconductors in the Atari ST are. The control signals from the CPU and Glue are now
fed through a multiplexer.
The DMA IP core is implemented and the signals for bus arbitration between the CPU
and Glue are joined, with a test made to make sure the system still functions as it did
before.
Without anything currently connected to the ACSI DMA bus, no further tests
can be done.
Just after adding this component IP core the RaggedStone board developed a fault.
While trying to identify devices on the JTAG boundary scan, the RaggedStone kept on
reporting an infinite number of ‘unknown devices’. The three devices in the chain
(Xilinx Spartan, XCF02 configuration PROM and XCF04 configuration PROM) were
separated and scanned individually. The fault was identified as the XCF02 configuration
PROM and luckily it was not the FPGA. The faulty XCF02 was simply removed and a
new one soldered in place.