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Circuit Description-7D15
megahertz Voltage Controlled Oscillator (VCO) and
decade counter provides the 10 ns and 100 ns Clock
signal . The Voltage Controlled Oscillator is stabilized with
a phase-locked loop circuit, in which the 100 megahertz
output is divided by 100 and compared with the One
Megahertz Standard . The frequency difference from the
Phase Detector is a do error voltage and is presented to the
Voltage Controlled Oscillator to correct any drift.
After amplification and level selection, the signals are
shaped in the A and B Shapers. The signals are then
connected to the A Arm and B Arm circuitry (byway of the
Slope circuits) . This circuitry can, with the proper command, inhibit the signal from any further travel . A LO or
ground connection to the A ARM connector will inhibit the
B signal while a HI command at the B ARM connectorwill
inhibit the A signal . These signals, if not inhibited, are
connected to the gating circuitry.
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GATE
For simplicity, the Gate block is discussed in each
mode of operation . A block diagram, showing the main
signal flow, is given for each mode .
FREQUENCY MODE
Refer to Fig . 3-1 for signal flow . The frequency to be
measured is connected to the B input through the B
circuitry ; then to the main gate . The 10 ms Frequency
Standard is connected through the A Arm circuit to the
Gate Generator and the Arm Gate Generator . The 10 ms
pulse sets the Arm Gate Generator and the Gate
Generator HI . This enables the AND gate and opens the
Main Gate . Opening the Main Gate allows the B signal to
be counted. The next 10 ms pulse sets the Arm Gate
Generator LO, which causes the AND Gate to go LO,
turning the Main Gate off. A LO at the output at the AND
Averaging Signal Path
Channel B Signal
0
10ms Clock or Reference Signal
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Fig. 3-1. Signal flow for FREC! and Frequency Ratio modes.
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