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PDP-502MX, PDP-502MXE
PLL output HD for A/D sampling &
clock SYNC reference
A
K2432
DIVOUT
K2029
HD_PLL
AMP/AD/PLL IC
IC2701
(CXA3106Q)
PLL input HD
K2030
HOLD controlling signal for comparing
PLL phase comparison.
HOLD_PLL
HOLD signal
generation circuit for
PLL control
1_2CLK
XCLK
PLL unlock information
(Hi: When PLL is not locked)
K2408
ULK_PLL
HD_DSEL
Vertical line number count value (11-bit data)
Data is updated every 1 V sync.
B
LINE(0:10)
Line
Number
Counter
Signal for detecting abnormal SYNC signal (Hi: in detecting)
SYNC STATE
Count value in the period of 1H by 16MHz clock (11-bit data)
Data is updated at the rate of HD1/8 dividing
H_COUNT(0:10)
HD Freq
Counter
Timing signal for capturing horizontal frequency
count value (HD 1/8 dividing)
K2019
HD_U
Signal Frequency DET
U-COM
IC2201
( PD2060A )
*Input signal detection
(stability)
*No signal input detection
*Detecting vertical frequency
*Controlling V_STD
(detecting frequency value)
K2018
VD_U
Vertical SYNC signal for
input signal detection
K2027
Signal for detecting vertical frequency limit
Lo: Vertical frequency value is higher than
standard value (In PC input : fixed Hi)
V_STD
Serial data
REQ_Su
HOLD_Su
Sending
*Data of vertical frequency
*Data of horizontal frequency
*Data of total numbers of lines
*Information on inapplicable
frequency
C
Inverted PLL unlock information (Lo: When PLL is not locked)
HD_DSEL
XCLK
1_2CLK
U-COM ASSY
Serial Control sig
PLD_CE
DATA
CLK
SER-->PARA
CONV
K2031
VD_DSEL
DIGITAL VIDEO ASSY
VD SYNC signal sent to Digital Assy
D
CLP1
CLP2
HBLK1
VBLK2
Clamp & Blanking signal output from
Digital Assy
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