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In the mixer, the 21.42 MHz second IF is divided into two paths (0 path and 90 path) and
then mixed with the 90 phase dierent 21.4 MHz signals. Therefore, the 90 phase dierent
20 kHz signals are converted. The 90 path 20 kHz lags the 0 path 20 kHz by 90 s. Then the
two phase shifters shift the 90 path 20 kHz forward by 90 . Therefore, the 90 path and the
0 path signals are in phase. Then the third IF signal is generated by adding the two 20 kHz
signals that are in phase.
When 21.38 MHz signal is applied to the mixer. The 90 path mixer output 20 kHz forwards
that of 0 path by 90 . Therefore, the 90 path phase sifter output 20 kHz forwards that of 0
path by 180 . These two signals are canceled by being added to each other.
Sample/Hold and A/D Converter
The 3rd IF is sampled and held in the Sample/Hold circuit. The hold signal is applied to the
A/D converter through the A/D multiplexer and then converted to a digital value. The A/D
multiplexer multiplexes the hold signal and the DC bus.
The DC bus is a single multiplexed line that networks 26 nodes within the analyzer. When the
DC bus is connected to the A/D converter, the A/D converter is used to measure the voltage at
a selected node within the analyzer. For more information about the DC bus measurement, see
Chapter 10.
The analyzer has a 16 bit A/D converter capable of sampling at 100 ks/s. In this application, it
samples at the rate of 80 ks/s. The sequencer consists of four GALs (gate array logic) ICs that
are used as follows:
Timing generator for the sample/hold the A/D converter.
Timing generator/Gate shaper for the real time gated analysis.
Timer driver/Input multiplexer driver/Frequency increment driver (controlling A5 FRAC N
OSC).
Decoder for the control signal from the A1 CPU.
Gains X, Y, and Z
The gains X (0 dB/6 dB/12 dB), Y (0 dB/6 dB/12 dB/18 dB), and Z (0 dB/2 dB/4 dB/18 dB) are
variable ampliers.
These ampliers are used to optimize the IF gain (total gain through the 1st/2nd/3rd IF signal
path) in order to use the A/D converter's widest possible dynamic range. The analyzer
coarsely measures device impedance to determine the ampliers' gains, then measures device
impedance with optimum gain setting.
Theory of Operation
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