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Master Bus Operation
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Freescale Semiconductor, Inc...
driven high for a read cycle, and the master size signals (MSIZ[1:0]) indicate transfer size.
The ColdFire2/2M asserts the master transfer start (MTSB) signal during C1 to indicate the
beginning of a bus cycle. MKILLB does not assert during this cycle so the access will go
external via M-Bus.
Clock 2 (C2)
During the first half of C2, the ColdFire2/2M processor negates MTSB. The selected device
uses the MRWB and MSIZ signals to place the data on the master read data bus
(MRDATA[31:0]) and assert the master input enable (MIE) signal. Concurrently, the
selected device asserts the master transfer acknowledge (MTAB) signal. At the end of C2,
the ColdFire2/2M processor samples the level of MTAB and latches the current value on
MRDATA[31:0]. If MTAB is asserted, the transfer terminates. If MTAB is not asserted, the
ColdFire2/2M ignores the data and inserts wait states instead of terminating the transfer.
The ColdFire2/2M continues to sample MTAB on successive rising edges of CLK until it is
asserted. The selected device negates the MIE and MTAB signals in the first half of the next
CLK cycle.
Clock 3 (C3)
Another read cycle begins in C3; however this read cycle will be to internal integrated
memory. During the first half of C3, the ColdFire2/2M places valid values on the master
address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and MTM[2:0]
signals identify the specific access type. The master read/write (MRWB) signal is driven high
for a read cycle, and the master size signals (MSIZ[1:0]) indicate transfer size. The
ColdFire2/2M asserts the master transfer start (MTSB) signal during C3 to indicate the
beginning of a bus cycle. MKILLB asserts late in the cycle. The combination of the assertion
of both (MTSB and MKILLB signifies that the access will occur internally in integrated
memory and the M-Bus transaction is not needed. The internal access will complete in one
cycle; therefore another access can begin immediately on the following cycle.
Clock 4 (C4)
A write cycle starts in C4. During the first half of C4, the ColdFire2/2M places valid values
on the master address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and
MTM[2:0] signals identify the specific access type. The master read/write (MRWB) signal is
driven low for a write cycle, and the master size signals (MSIZ[1:0]) indicate transfer size.
The ColdFire2/2M asserts the master transfer start (MTSB) signal during C4 to indicate the
beginning of a bus cycle. MKILLB does not assert during this cycle so the access will go
external via M-Bus.
Cycle 5 (C5)
During the first half of C5, the ColdFire2/2M negates MTSB. The selected device uses the
MRWB and MSIZ signals to take the data off the master write data bus (MWDATA[31:0].
Concurrently, the selected device asserts the master transfer acknowledge (MTAB signal.
At the end of C5, if MTAB is asserted, the transfer terminates. If MTAB is not asserted, the
ColdFire2/2M inserts wait states instead of terminating the transfer. The ColdFire2/2M
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ColdFire2/2M User’s Manual
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