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Chapter 7
XEPLD
This chapter describes how to use XEPLD, the Xilinx software for
designing Xilinx EPLDs. Specifically, it describes how to write your
design files to take advantage of EPLD architectural features, convert
your design to PLUSASM format, combine multiple modules with or
without a schematic, fit your design to a Xilinx EPLD device, save the
pinout, create a programming file, and create a simulation model.
Device Architecture
Before you create an XEPLD design, you should be familiar with the
device architecture of Xilinx EPLDs. For complete details on EPLD
architecture, see the device data sheets. Some of the architectural
features of EPLDs are the following.
●
Logic grouped into function blocks. There are two types of
function blocks: high-density and fast. Each function block has
nine macrocells.
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A universal interconnect matrix (UIM) with predictable, constant
delays. The UIM allows routing between any input pin or
macrocell feedback and any function block input, which means
that, if the design fits into the function blocks, it will route. The
UIM also ANDs such input signals with no additional delay.
●
Arithmetic carry logic
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A mixture of I/O pins, input pins, and output pins, with several
global clock inputs and other global control signals
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All inputs optionally registered or latched at the pad
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XOR gates for efficient counters, adders, and T flip-flop emulation
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