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Download XtremeDSP Development Kit User Guide
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XtremeDSP Development Kit User Guide Interface COMM General Bus Signal Name Dime-II Connector PIN No Signal User FPGA (2V250 FG456) User FPGA (2V1000 User FPGA User FPGA (2V2000 (2V3000 User FPGA (2V3000/ Pin No FG456) FG676) FG676) 6000 PIN No Pin No Pin No FF1152) Pin No ADIO<15> LBUS<15> PB18 H4 H4 K6 K6 F3 ADIO<16> LBUS<16> PB19 H3 H3 K5 K5 G3 ADIO<17> LBUS<17> PB20 H2 H2 K4 K4 E4 ADIO<18> LBUS<18> PB21 H1 H1 K3 K3 F4 ADIO<19> LBUS<19> PB22 K2 K2 M4 M4 D3 ADIO<20> LBUS<20> PB24 K1 K1 M3 M3 E3 ADIO<21> LBUS<21> PB25 K4 K4 M6 M6 AA4 ADIO<22> LBUS<22> PB26 K3 K3 M5 M5 AB4 ADIO<23> LBUS<23> PB27 L5 L5 N7 N7 AC3 ADIO<24> LBUS<24> PB28 L4 L4 N6 N6 AC4 ADIO<25> LBUS<25> PB29 L3 L3 N5 N5 D2 ADIO<26> LBUS<26> PB30 L2 L2 N4 N4 D1 ADIO<27> LBUS<27> PB31 M5 M5 P7 P7 E2 ADIO<28> LBUS<28> PB33 N1 N1 R3 R3 E1 ADIO<29> LBUS<29> PB34 N2 N2 R4 R4 F2 ADIO<30> LBUS<30> PB35 P6 P6 T8 T8 F1 ADIO<31> LBUS<31> PB36 P5 P5 T7 T7 G2 BUSY ADJOUT<0> PD29 B19 B19 D21 D21 N32 EMPTY ADJOUT<1> PD30 A19 A19 C21 C21 P32 RDl_WR ADJOUT<2> PD31 C22 C22 E24 E24 T30 AS_DSl ADJOUT<3> PD32 C21 C21 E23 E23 U30 RENl_WENl ADJOUT<4> PD33 E20 E20 G22 G22 U27 INTl ADJOUT<5> PD34 E19 E19 G21 G21 U26 RSTl ADJOUT<6> PD35 D22 D22 F24 F24 U29 Table 27 - Interface to User FPGA Comms Signals Also DSP_CLK should be connected to CLK1(sometimes referred to as CLKB) Interface COMM General Bus Signal Name Signal Dime-II Connector PIN No User FPGA (2V250 FG456) User FPGA (2V1000 User FPGA User FPGA (2V2000 (2V3000 User FPGA (2V3000/ FG456) FG676) FG676) 6000 Pin No PIN No Pin No Pin No FF1152) Pin No DSP_CLK CLK1 PC31 V11 V11 Y13 Y13 AG17 Table 28 - Interface to User FPGA Clock Requirements NT107-0132 Issue 9 23-05-2003 www.nallatech.com 129
