Download PLSyn User's Guide

4-8
Simulating Programmable Logic Designs
Using the “Sample Window”
Control
See page 4-3 for information on
how to get to the setup dialog
box for your simulator.
The Sample Window value (specified in the simulation setup
dialog box) defines the interval during which the simulator
considers input changes to occur at the same time.
Set this value when signals, considered part of the same input
vector, arrive at the boundary of the programmable logic at
slightly different times. This is useful, for example, in mixed
analog/digital designs.
Example: How the Simulator
Creates Test Vectors
Case 1
Consider the following case,
PLSYN_U1
I1
I2
1
3
O1
2
AND2
with inputs and outputs as follows.
Table 4-2 Test Vectors for
Case 1
Time Sample
Taken
I1
10
0
0
L
11
1
0
L
20
1
1
H
30
0
1
L
I2
O1
I1
I2
O1
0
Note In JEDEC files, 0, and 1
are input values; L and H are
output values.
10
20
30
With Sample Window set to zero, the simulator creates test
vectors by recording the value of all inputs and outputs
whenever any input changes. The vector consists of all prior
input values, along with the current output value. In other words,
the simulator assumes that any input change propagates to the
output by the time the next input change occurs. Table 4-2
shows the test vectors that the simulator creates using this logic.