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Register Name: IR_RXCTL Offset: 0x10 Bit Read/Write Default Value: 0x0000_0000 Default Description 1: Invert receiver signal 1:0 / / / 6.6.3.6. IR RECEIVER ADDRESS REGISTER Register Name: IR_RXADR Offset: 0x14 Default Value: 0x0000_0000 Bit Read/Write Default Description 31:9 / / / RAM Receiver Address Match 8 R/W 0: Does not need match address (RA). When an new packet is received, the address, control and data fields are filled into RX FIFO. 0 1: Should match packet address to RA bits when an new packet is received. If address matched, the control and data fields are filled into RX FIFO excluding the address field. The value of this bit can be changed when the RXEN bit is cleared. RA 7:0 R/W Receiver Address 0 The value of this bit can be changed when the RXEN bit is cleared. 6.6.3.7. IR RECEIVER COUNTER REGISTER Register Name: IR_RXCNT Offset: 0x18 Default Value: 0x0000_0000 Bit Read/Write Default Description 31:12 / / / 11:0 R 0 A20 User Manual (Revision 1.3) RPL Receiver Packet Length Copyright © 2014 Allwinner Technology Co., Ltd. All Rights Reserved. Page 669 / 853