Download IPUG78 - SERDES Framer Interface Level 5 (SFI

Lattice Semiconductor
SFI-5 IP Core
SFI-5 FPGA Block Diagram
Figure 2. SFI-5 FPGA Block Diagram
txdata
16
2
16
SERDES
Sixteen
16-Bit
Transmit
Channels
16
16
16
16
16
16
16
16
2
16 Tx Channels
Quads 0-3
(8/16-Bit
SERDES-Only
Mode)
2
2
16 Data
Channels
2
tclk_[3:0] x 4 quads
refclk
txdsc
Deskew
Channel
Generator
16
Deskew
Tx SERDES
2
Deskew
Channel
tclk_0
SFI-5 Tx
IP Core
refclk
sysclk_tx
155.5 MHz
622 MHz
PLL
Div 4
sysclk_rx
SFI-5 Rx
IP Core
rxrefclk
rx_serdes_out
16
rxdata
16
SERDES
2
Delay
16
16
Sixteen
16-Bit
Receive
Channels
2
16
Delay
16
Delay
16
16
Delay
16
16 Rx Channels
Quads 0-3
(8/16-Bit
SERDES-Only
Mode)
2
16 Data
Channels
2
16
Delay
2
rclk_[3:0] x 4 quads
Per Channel
Comparator
rxrefclk
rx_chan_dly
1
Deskew
Channel
Framer
rxdsc
16
Delay
dsc_dly
4
Deskew
Rx SERDES
Quad 4
rclk_0
ref_pclk
2
Deskew
Channel