Download Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

2
UG-01087
2015.05.04
Altera PLL IP Core Parameters - General Tab
Altera PLL IP Core Parameters - General Tab
Table 1: Altera PLL IP Core Parameters - General Tab
Parameter
Legal Value
Description
Device Speed Grade
Stratix V: 1–4, Specifies the speed grade for a device. The lower the
Arria V: 3–6, number, the faster the speed grade.
Cyclone V: 6–
8
PLL Mode
Integer-N PLL Specifies the mode used for the Altera PLL IP core. The
or Fractional- default mode is Integer-N PLL.
N PLL
Reference Clock Frequency
Altera Corporation
—
Specifies the input frequency for the input clock, refclk, in
MHz. The default value is 100.0 MHz. The minimum and
maximum value is dependent on the selected device. The
PLL reads only the numerals in the first six decimal places.
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
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