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Index
Minimize GLB levels for all paths
(advanced) 124
Parameter file 123
Settings 118
Single PT function packing for routability
(advanced) 125
Strategy 120
Timing Analyzer 123
Use extended routing 122
Use global reset 120
Use internal tristate IO driver
(advanced) 124
Constraint Editor
Assigning Power Level 113
for MACH 109
Group Assignment 111
invoke 109
JEDEC File Options 112
Location Assignment 110
make 110
main window 109
Output Slew Rate Control 114
Pin Reservation 112
Constraint Manager
Assign Attribute Values 108
Design Browser 107
for ispLSI 106
invoke 106
main window 106
Net Attributes Table 108
Pin Attributes Table 107
Symbol Attributes Table 108
Constraints
MACH/PAL 66
D
D/T synthesis
MACH global optimization option 130
Design
hierarchy 30, 67
ispLSI/GAL
compiling/fitting 132
MACH/PAL
compiling/fitting 134
procedures 23
processing 20, 34
targeting a device 18
Design attributes
add to a symbol 48
ispLSI 96
assigning in ABEL-HDL 98
assigning in schematic 97
precedence of 101
processing 99
MACH 102
assigning in ABEL-HDL 103
assigning in schematic 102
syntax in ABEL-HDL 103
Design control properties
ispLSI 51
Design entry
ABEL-HDL 40
EDIF 61
mixed Schematic and ABEL-HDL 87
mixed Schematic and Verilog HDL 95
mixed Schematic and VHDL 94
Schematic 44
Verilog HDL 57
VHDL 53
Detailed Report 160
Device
targeting 18
Device options
ispLSI 125
ISP 125
ISP except Y2 125
Lowpower 126
Security 125
TOE_AS_IO 126
Y1 as reset 126
Device selection 29
dialog box 29
E
EDIF
create for ispLSI 56, 59
import mechanism for MACH/PAL 66
import netlist 61
property files for MACH/PAL 64
Effort
ispLSI compiler property 120
Environment and configuration
change 34
Equation simulation
run 144
Equation Simulator
for MACH/PAL 144
simulation model 145
view 145
simulation report
control 146
ispDesignExpert User Manual
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