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Timing Analyzer Reports
Setup and Hold Report
For setup and hold information, the first column is the name of flip-flop or latch. The
second column is the port name that drives the data pin of the flip-flop or latch. The
third column is the port name that drives the clock pin of the flip-flop or latch. The
fourth column is the setup value, and the fifth column is the hold value.
The following is an example of a Setup and Hold Report (design.tsu).
Setup and Hold Report:
--------------------Design Name: CNT4
Part Name: ispLSI2032E-180LT48
This report lists the setup/hold requirements for all the boundary
registers in the design
Required Setup and Hold
Register Name
Data
Clock
Setup(ns)
Hold(ns)
==------------------------------------------------------------------------------------GLB_QI2
LD
CLK
8.50
-1.00
GLB_QI2
PS
CLK
8.50
-1.00
GLB_QI2
CD
CLK
8.50
-1.00
GLB_QI2
D2
CLK
8.50
-5.50
GLB_QI2
EN
CLK
8.50
-5.50
GLB_QI2
CI
CLK
8.50
-5.50
GLB_QI1
LD
CLK
8.50
-1.00
GLB_QI1
PS
CLK
8.50
-1.00
GLB_QI1
CD
CLK
8.50
-1.00
GLB_QI1
D1
CLK
8.50
-5.50
GLB_QI1
EN
CLK
8.50
-5.50
GLB_QI1
CI
CLK
8.50
-5.50
GLB_QI0
LD
CLK
8.50
-5.50
GLB_QI0
PS
CLK
8.50
-5.50
GLB_QI0
CD
CLK
8.50
-5.50
GLB_QI0
D0
CLK
8.50
-5.50
GLB_QI0
EN
CLK
8.50
-5.50
GLB_QI0
CI
CLK
8.50
-5.50
GLB_QI3
LD
CLK
4.00
-1.00
GLB_QI3
PS
CLK
4.00
-1.00
GLB_QI3
CD
CLK
4.00
-1.00
GLB_QI3
EN
CLK
4.00
-1.00
GLB_QI3
D3
CLK
4.00
-1.00
GLB_QI3
CI
CLK
4.00
-1.00
==-----------------------------------------------------------------------------------
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