Download Altera Cyclone II FPGA board User Manual - FPGA-DEV

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Altera Cyclone II FPGA board
User Manual
Disclaimer
This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any
particular purpose is either made or implied. No claims will be accepted for damages howsoever arising as a
result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is
not intended for use in any medical appliance, device or system in which the failure of the product might
reasonably be expected to result in personal injury. This document provides preliminary information that may be
subject to change without notice.
Copyright © 2007, Valerij Matrose. All rights reserved.
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Content
Content ....................................................................................................................................... 2
Introduction ................................................................................................................................ 3
Description of the FPGA board.................................................................................................. 3
Block diagram ........................................................................................................................ 3
FPGA board components - top side ....................................................................................... 4
FPGA board components - bottom side ................................................................................. 4
Altera Cyclone II FPGA......................................................................................................... 5
Configuration CPLD .............................................................................................................. 5
Flash memory......................................................................................................................... 5
miniSD-Card socket ............................................................................................................... 5
SDRAM memory socket ........................................................................................................ 5
USB controller........................................................................................................................ 5
Ethernet controller.................................................................................................................. 6
Crystal oscillator .................................................................................................................... 6
User I/O .................................................................................................................................. 6
Reload button ......................................................................................................................... 6
Expansion connectors............................................................................................................. 6
Power supply .......................................................................................................................... 7
Physical dimensions and expansion header positions ............................................................ 7
Setting-up operations.................................................................................................................. 8
FPGA design software ........................................................................................................... 8
USB drivers installation ......................................................................................................... 8
FPGA pin allocation file ........................................................................................................ 8
FPGA configuration ............................................................................................................... 8
FPGA configuration via USB interface ............................................................................. 8
FPGA configuration from the flash memory ..................................................................... 9
FPGA configuration via JTAG .......................................................................................... 9
JTAG chain ...................................................................................................................... 10
Flash memory programming ................................................................................................ 10
NIOS II – example SOPC system ............................................................................................ 11
Memory test.......................................................................................................................... 11
Ethernet test.......................................................................................................................... 11
USB test................................................................................................................................ 11
CD content................................................................................................................................ 11
Document revisions and changes ............................................................................................. 12
Trademarks............................................................................................................................... 12
Schematics and component diagrams ...................................................................................... 13
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Introduction
Thank you for your interest in Cyclone II based FPGA board! This development board for
an experienced user combines many powerful features at very fair price. The possible
application range covers stand alone experiments on the one side and operation as a part of a
commercial product on the other side. Features make this FPGA board unique among other
development boards are:
•
•
•
•
•
•
•
Small size of the FPGA board (only 96x68 mm) makes it possible to use it in the
end application as a daughter board,
172 Cyclone II I/O pins are exclusively available at the expansion connectors,
More than a half of these I/Os are connected to common connectors with
2.54 pitch and high duty gold plated precision contacts,
Two controllers for the world most used data buses (Ethernet and USB) already
soldered on FPGA board,
One SODIMM SDRAM memory socket for up to 256 Mbytes SDRAM module,
16 Mbytes flash memory,
Integrated power conditioning.
Description of the FPGA board
Block diagram
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FPGA board components - top side
power LED
4x SMD connector
power supply
connector
3x user LEDs
USB
connector
JTAG connector
miniSD-Card
socket
3.3V regulator
reload button
LAN
connector
user button
conf. state LED
flash memory
Cyclone II FPGA
FPGA board components - bottom side
2x precisionconnectors with
2.54mm pitch
SDRAM socket
1.2V switch
regulator
USB controller
configuration
CPLD
25MHz oscillator
Ethernet controller
DIP switches
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Altera Cyclone II FPGA
The used Altera Cyclone II FPGA EP2C35F672C8N contains in total 33,216 LE
(LE=LUT+DFF), 483 kbit memory, 35 embedded multipliers and 4 PLLs.
Configuration CPLD
The CPLD can configure FPGA with one of 8 selectable configuration files, which can be
programmed into flash memory.
Flash memory
The 16 MByte large flash memory device can hold up to 8 FPGA configuration files and
application specific data. The flash device is connected through 16 bit wide data bus to FPGA.
miniSD-Card socket
Flash cards for the miniSD-Card Socket are available today with capacities up to 4 GByte.
SDRAM memory socket
SODIMM socket accepts laptop SDRAM memory modules with capacity up to
256 MByte. The data bus to the FPGA is 64 bit wide, which results in 1 GByte/sec maximum
total data rate.
USB controller
The integrated high speed USB controller CY7C68013 communicates with 480Mbits/sec
with a PC or another proper USB host. Preprogrammed E²PROM already contains firmware
for 8051 based microcontroller of the CY7C67013. The firmware configures the endpoints as
follows:
endpoint
EP2
EP4
EP6
EP8
direction
out
out
in
in
FIFO count x block size
2 x 512 Byte
2 x 512 Byte
2 x 512 Byte
2 x 512 Byte
The general programmable interface of USB controller (FPGA↔USB) is configured
as 16 bit wide slave FIFO interface. The FIFO interface is clocked with 25 MHz, which
allows net transfer of 50 Mbyte/sec. between FPGA and USB controller.
The firmware-programmed vendor and product IDs are reserved for development
intentions only:
idVendor
0x04B4
idProduct
0x1004
You must change these IDs if you use the FPGA board as a part of a commercial product!
You can use delivered FPGA configuration tool for FPGA configuration over USB interface
without any JTAG adapter.
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Ethernet controller
The FPGA board provides 100/10MBit Ethernet support via Davicom DM9000A Ethernet
controller chip. This makes in fact a very simple and FPGA logic resources saving connection
to Ethernet networks possible.
Crystal oscillator
The 25 MHz reference clock is generated by crystal oscillator Q1. This clock signal is
provided to FPGA, FIFO interface of USB controller and Ethernet controller. The usage of a
reference clock makes sure, that all components can communicate with FPGA absolutely
synchronous in one single clock domain.
User I/O
A debounced push button can be used for direct user input detection. The released user
button is identified by logic low (0 volt) and pressed one by logic high (3.3 volt).
For simple outputs three user LEDs are provided on the FPGA board. Each LED is driven
directly by a pin of the FPGA. Driving related pin to a logic low (0 volt) turns the LED on.
Reload button
Pushing the reload button (SW1) clears the configuration data inside FPGA. Immediately
after releasing the reload button the FPGA is reconfigured by CPLD with a configuration
contained in flash if the DIP switch (4) in the ON position.
Expansion connectors
User circuits can be connected to FPGA through two expansion connectors on the bottom
of the board (J6 and J7 with 2.54 mm pitch) and through four surface mounted connectors on
the top of the board (J2-J7). Four different signal types are available at expansion connectors:
1. FPGA-I/Os - FPGA in- and outputs, the signal direction is application specific
and defined by the user,
2. FPGA-I/Os or PLL output - same as type one, additionally these pins can be
used as PLL clock output,
3. FPGA- or PLL clock inputs - input only FPGA pins, allow direct clock
sourcing to PLL circuits,
4. Power supply connectors - +5V, +3.3V and power ground.
The following table lists the availability and count of the first three pin types at different
expansion connectors:
conn. / signal type
J2
J3
J4
J5
J6
J7
Σ
1
20
20
19
21
43
42
165
2
0
0
1
0
0
1
2
3
1
1
1
0
1
1
5
Note: All these 172 FPGA I/Os are exclusively available at expansion connectors, they are not
shared with any other FPGA board device or circuit.
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Power supply
The FPGA board is power supplied through the CON1 connector. The centre of the power
supply plug must be positive (+5 volt) and the barrel must be negative (ground). As an
alternative, you can use power pins 2, 4 (both positive) and ground pins of expansion
connector J6 to supply power to the FPGA board. The power supply must provide a regulated
voltage of 5 volt (±10%, min. 1 ampere).
The FPGA Board components require either 1.2 volt supply (FPGA core) or 3.3 volt
supply (FPGA-I/Os, SDRAM, USB, Ethernet, flash, etc.). These voltages are provided by a
high efficient switch regulator (1.2 volt) and linear regulator (3.3 volt). Both regulators
deliver currents up to 3 ampere.
The real current requirement depends on the following factors:
• Configuration loaded into FPGA,
• SDRAM memory usage,
• Current drawn by user expansion circuits supplied through FPGA board.
Important: There is no power supply reverse-polarity protection circuit on FPGA board!
Wrong power supply polarity will damage FPGA board components!
Physical dimensions and expansion header positions
All dimensions are in millimetres
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Setting-up operations
FPGA design software
Altera Cyclone II EP2C35 FPGA is supported by the free Altera Quartus II Web
Edition design software. Please visit www.altera.com for further information and download.
USB drivers installation
Install Cypress USB drivers before using the FPGA board USB interface. Execute the
„~\usb\SETUP_FX2LP_DVK_1004.exe“ for installation. Many tools, firmware examples and
documents needed for successful and fast development of own CY7C68013 firmware and PC
applications are installed too.
FPGA pin allocation file
All pin allocations of the FPGA are contained in „~\fpga\pin_assignments.qsf“.
FPGA configuration
You can configure the Cyclone II FPGA in three different ways:
• Via USB interface,
• With content from the flash memory,
• Via JTAG interface.
Let’s have a look on every of these possibilities.
FPGA configuration via USB interface
As earlier mentioned, the E²PROM is preprogrammed with a small firmware for the 8051
MCU of the USB controller. This firmware uses internal endpoint 1 for FPGA configuration
data reception. After reception, the configuration data is shifted by 8051 MCU in serial
manner (PS mode) into FPGA.
Please follow the lower instructions for the FPGA configuration via USB:
1. Shove DIP switch (4) in OFF position:
2.
3.
4.
5.
Clear current configuration by pressing reload button,
Connect PC and FPGA board through USB cable,
Start FPGA configuration tool,
Choose the raw bit configuration file (*.rbf).
The configuration procedure starts immediately after file selection dialog is closed and lasts
about 5 seconds. A success message confirms finished FPGA configuration. At the same time
the yellow LED turns on.
Note: Once FPGA configuration procedure starts, await a success or failure message before
next attempt.
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FPGA configuration from the flash memory
The flash memory can contain up to 8 selectable configuration files for standalone FPGA
configuration. The configuration starts after the power supply is applied to the FPGA board
and the highest DIP switch (4) is in ON position. The lower DIP switches (1..3) determine
address range in the flash memory which is used for loading configuration data. The loaded
configuration data is shifted in serial manner into FPGA (PS mode). The lower 8 MByte of
flash memory are segmented in address ranges as follows:
# configuration
address range
0
0x00.0000-0x0f.ffff
1
0x10.0000-0x1f.ffff
2
0x20.0000-0x2f.ffff
3
4
5
6
0x30.0000-0x3f.ffff
0x40.0000-0x4f.ffff
0x50.0000-0x5f.ffff
0x60.0000-0x6f.ffff
7
0x70.0000-0x7f.ffff
switch position
…
…
…
…
Each memory segment is large enough for storage exactly one FPGA configuration. Unused
segments can be used for any other purposes.
Note: Configure the FPGA from the flash memory only when a flash segment with a valid
configuration data is selected!
FPGA configuration via JTAG
The pin configuration of JTAG connector complies with the Altera specifications. You
can use both the original Altera USB Blaster and the compatible one from terasIC.
(www.terasic.com.tw).
Note: The usage of a JTAG adapter is the only way to:
• In circuit debugging of a NIOS II system,
• Using the Signal Tap II logic analyzer,
• Programming flash memory.
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JTAG chain
The JTAG chain carried out at JTAG connector consist of Xilinx configuration CPLD and
Altera Cyclone II FPGA. The configuration CPLD is already programmed; there is no need
for any modifications of its function. If you use a JTAG adapter in conjunction with Altera
Software please note: The Altera Software reports the configuration CPLD as an unknown
device. It’s not a malfunction or a bug; it does not impact usage of Altera Software!
Flash memory programming
The programming of flash memory requires a JTAG adapter, a working NIOS II design
(contained in „~\fpga\nios2_sys_test\...“) and installed NIOS II IDE Software. Following
steps have to be done to program the flash memory with a configuration file at address 0x0:
1. Start “Quartus II Programmer” application from NIOS II IDE
(Tools→Quartus II Programmer)
2. Configure FPGA with „~\fpga\nios2_sys_test\nios2_sys_test.sof“ file
(Auto Detect→double click at file field of EP2C35→Select file→Start)
3. Start „Flash Programmer“ application from NIOS II IDE (Tools→Flash Programmer)
and select the desired FPGA configuration file and destination address range (offset):
4. Push „Program Flash“. The Flash Programmer window will automatically close. All
output messages will appear at console window of NIOS II IDE.
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NIOS II – example SOPC system
The enclosed CD contains an example NIOS II system for Quartus II v7.2 (CDROM path
„~\fpga\nios2_sys_test\...“). This example system was developed to check the function of all
components contained at the FPGA board. The results of the check subroutines are indicated
via the user LEDs. The top level entity file of the example NIOS II system is
„~\fpga\nios2_sys_test\top_level.vhd“
Memory test
Memory test tests the connection and integrity of flash and SDRAM memories. For a
successful SDRAM test insert a 256 MByte memory module into SDRAM socket. The user
LED 1 (D4) turns on, if SDRAM test succeeds. The user LED 2 (D5) indicates a succeeded
flash memory test.
Note: Memory test erases all contents in flash and SDRAM memory!
Ethernet test
After Ethernet controller initialisation every received data package generates a processor
interrupt. The interrupt service routine reads the Ethernet packet data from DM9000A and
sends its content immediately back to sender. Every call of interrupt service routine changes
the state of the user LED 3. The target IP address of the Ethernet controller is set by
initialisation routine to „01.60.6E.11.02.0F“.
Note: You can use Ethernet packet sniffer and generator like CommView from TamoSoft
to generate and receive Ethernet packets.
USB test
A VHDL component is instantiated in NIOS II example system for USB controller test.
This component is not connected to NIOS II example system. It consist of two 512 Byte large
FIFOs and realises a simple echo application. One FIFO serves endpoints EP2 and EP6, the
other EP4 and EP8. Content of packets received through EP2 endpoint is read via FIFO
interface and stored in assigned FIFO. After that, the data is send back through EP6 endpoint.
The same procedure is applied to endpoints EP4 and EP8.
Note: You can test the quality of the USB connection with Cypress tool CyBulk.
CD content
~\cpld\...
~\data_sheets\...
~\docs\...
~\fpga\...
- configuration CPLD programming file
- data sheets of used components
- this file
- IP component for connection of Ethernet controller to NIOS II
- FPGA pin allocation file
~\fpga\nios2_sys_test...
- NIOS II example system
~\usb\...
- USB drivers and documentations of Cypress USB controller
~\usb\firmware\...
- firmware sources of USB controller
~\usb\programmer\...
- source codes of Windows FPGA programming tool
~\usb\programmer\Release\...- Windows FPGA programming tool
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Document revisions and changes
revision / date
1.00 / 10.11.2007
Changes
initial version
Trademarks
Cyclone II, NIOS II, Signal Tap II and Quartus II are trademarks of Altera Corporation.
CyBulk is a trademark of Cypress.
ComView is a trademark of TamoSoft.
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Schematics and component diagrams
13
5
C87
100nF
4
C88
10uF
C89
100nF
C90
100nF
C91
100nF
C72
100nF
C73
10uF
3
C74
10uF
C92
100nF
C75
10uF
Vcc +3.3V Vcc +2.5V
C93
100nF
C94
100uF
EPIN
Vcc +3.3V
C95
100nF
C76
100nF
C77
100nF
2
3
37
26
55
Vcc +3.3V
C78
100nF
C96
100nF
C79
100nF
Size
A3
Date:
Vccint
Vccint
Vccio
Vccio
Wednesday, April 18, 2007
Y19
AA21
W20
Vcc +1.2V
C80
100nF
C97
100nF
C17
1uF
C81
100nF
Sheet
1
C18
10nF
Vcc +1.2V
1
M1
MOUNT HOLE
1
M2
MOUNT HOLE
1
M3
MOUNT HOLE
1
M4
MOUNT HOLE
1
of
Y20
AA19
VCC_PLL3
GND_PLL4 VCCA_PLL4
GND_PLL4
GND_PLL4 VCCD_PLL4
L4
ferrite bead
IC3-7
EP2C35F672
Vcc +1.2V
AB6
AB9
AB13
AF3
AF11
V12
W9
H7
G8
2
VCCO_8
VCCO_8
VCCO_8
VCCO_8
VCCO_8
VCCO_8
VCCO_8
AB14
AB17
AB22
AD20
AF16
AF24
V15
W18
C16
10nF
GND_PLL3 VCCA_PLL3
GND_PLL3
GND_PLL3 VCCD_PLL3
Vcc +1.2V
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
G7
E4
F8
C15
1uF
IC3-6
EP2C35F672
VCC_PLL2
AA22
AD26
P22
R18
T26
V19
H20
G19
L3
ferrite bead
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
C14
10nF
GND_PLL2 VCCA_PLL2
GND_PLL2
GND_PLL2 VCCD_PLL2
Vcc +1.2V
C26
F22
J19
L26
M18
N22
C13
1uF
IC3-5
EP2C35F672
Y7
AA8
Vcc +1.2V
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
G20
E21
F19
GND_PLL1 VCCA_PLL1
GND_PLL1
GND_PLL1 VCCD_PLL1
IC3-4
EP2C35F672
VCC_PLL1
A16
A24
C20
D22
E14
E17
H18
J15
A3
A11
E6
E9
E13
H9
J12
Y6
W7
Y8
L2
ferrite bead
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
C1
F5
L1
M9
N5
AB5
AD1
P5
R9
T1
V8
C42
10uF
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
GND
Vcc +1.2V
GND
GND
GND
GND
3
7
1
3
IC5-2
XC9572XL-VQ64
AVcc
AVcc
Vcc +3.3V
C41
10uF
AGND
AGND
55
11
17
27
32
43
C40
100nF
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
C39
100nF
GND
GND
GND
GND
GND
GND
K10
K11
K12
K13
K14
K15
L11
L16
L17
L18
M10
M11
M16
M17
N10
N17
P10
R10
R11
R16
T11
T16
U11
U13
U14
U15
U16
V16
C38
100nF
C12
10nF
14
21
41
54
C71
100nF
C37
100nF
5
C70
100nF
C36
100nF
Vcc
Vcc +3.3V
C59
10uF
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
C11
1uF
GND
C69
100nF
C35
10nF
C10
220uF/10V
IC9-2
NC7SZ14
C68
100nF
C58
10uF
EP2C35F672
C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Vcc +3.3V
57
C67
100nF
C57
1uF
C34
10nF
C9
100uF/6V
6
10
C66
100nF
C56
1uF
C33
10nF
8
C65
100nF
C55
1uF
C32
10nF
C8
100nF
3
C86
10uF
C64
100nF
C54
100nF
C31
10nF
C7
100nF
Vout
Vcc
Vcc +3.3V
C63
100nF
C53
100nF
C30
10nF
C6
100uF/6V
Vin
Vcc +3.3V
GND
C62
100nF
C52
100nF
C29
10nF
IC2
LD1085D2T
IC4-2
CY7C68013A
C51
100nF
C28
10nF
C5
220uF/10V
L12
L13
L14
L15
M12
M13
M14
M15
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R12
R13
R14
R15
T12
T13
T14
T15
A2
A12
A15
A25
AB7
AB11
AB16
AB19
AC4
AD9
AD14
AD18
AE1
AE26
AF2
AF12
AF15
AF25
B1
B26
C14
C18
D4
D24
E7
E11
E16
E19
H5
H13
H14
H22
K20
L5
L22
M1
M26
N8
N19
P8
P19
R1
R21
R26
T5
U8
U19
W5
W13
W14
W22
Y9
Y17
IC3-2
GND
GND
4
IC8-2
24LC32
56
12
26
28
41
53
C61
100nF
C27
10nF
C4
220uF/2V
4
C85
100nF
C26
10nF
C3
100nF
9
2
C60
100nF
C50
10nF
2
TXGND TXVCC25
RXGND RXVCC25
RXGND
BGGND
23
30
42
C25
10nF
22uH
DVCC
DVCC
DVCC
C49
10nF
D2
30BQ015
Vcc +5V
6
5
47
48
C84
100nF
4
Vcc +1.2V
DM9000E
C24
10nF
L1
DGND
DGND
DGND
C48
10nF
Feedback
IC7-2
C47
10nF
2
15
33
45
C83
100nF
C2
100nF
Output
1
Vcc +3.3V
C46
1nF
C23
10nF
Vin
EN
C45
1nF
C22
10nF
4
C21
10nF
Vcc
C1
68uF/6.3V
IC1
LM2596S-ADJ
GND
R1
1k0
ON/OFF
1
3
6
5
2
Vcc +5V
2
1
2
CON1
POWER 5V
3
Q1-2
CFPS-73
G5
D8
F1
C44
1nF
VCC
VIO
VIO
C43
1nF
C20
10nF
GND
GND
GND
1
2
21
22
35
36
55
56
75
76
91
92
107
108
119
120
139
140
C19
10nF
E8
H7
H2
4
D1
PWR LED
IC6-2
S29GL128N
Vcc
D
GND
GND
B
CON3-2
SDRAM SO-DIMM
GND
Vcc 11
GND
Vcc 12
GND
Vcc 27
GND
Vcc 28
GND
Vcc 45
GND
Vcc 46
GND
Vcc 63
GND
Vcc 64
GND
Vcc 81
GND
Vcc 82
GND
Vcc 101
GND
Vcc 102
GND
Vcc 113
GND
Vcc 114
GND
Vcc 129
GND
Vcc 130
GND
Vcc 143
GND
Vcc 144
1
6
3
CON4-2
Mini SD-Card
5
1
Vcc +1.2V
3
L5
ferrite bead
VCC_PLL4
Vcc +1.2V
Document Number
2/2
1
D
Vcc +3.3V
C
Vcc +3.3V
C82
10uF
B
Vcc +3.3V
A
A
Title
Altera Cyclone II Board
Rev
1.1
IO_81
IO_83
IO_71
IO_73
IO_75
IO_77
IO_79
2
1
Vcc +3.3V
J3
VESA CON 41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
IO_21
IO_22
IO_23
IO_24
IO_25
IO_26
IO_27
CLK9_I
IO_28
IO_29
IO_30
IO_31
IO_32
IO_33
IO_34
IO_35
IO_36
IO_37
IO_38
IO_39
IO_40
IO_80
IO_82
IO_70
IO_72
IO_74
IO_76
IO_78
IO_60
IO_62
IO_64
IO_66
IO_68
IO_51
IO_53
IO_55
IO_57
CLK11_I
D
IO_41
IO_43
IO_45
IO_47
IO_49
CLK1_I
IO_1
IO_2
IO_3
IO_4
IO_5
IO_6
IO_7
IO_8
IO_9
IO_10
IO_11
IO_12
IO_13
IO_14
IO_15
IO_16
IO_17
IO_18
IO_19
IO_20
Vcc +3.3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
J2
VESA CON 41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J6 RM 2.54
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Vcc +5V
Vcc +3.3V
IO_61
IO_63
IO_65
IO_67
IO_69
3
IO_52
IO_54
IO_56
IO_58
IO_59
4
IO_42
IO_44
IO_46
IO_48
IO_50
5
D
D2
D3
LED
STAT_n
D1
DCLK
DATA0
CFGCLK
D0
/OE
/CE
A20
8
9
10
11
12
13
15
16
17
18
19
20
23
IO_2_1
IO_5_1
IO_6_1
IO_8_1
IO_3_1
IO_4_1
IO_9_1/GCK1
IO_11_1/GCK2
IO_14_1/GCK3
IO_10_1
IO_15_1
IO_17_1
IO_12_1
BLOCK_3
57
56
52
51
50
49
48
47
46
45
44
43
30
28
53
29
D7
A11
A15
A19
A16
A14
A22
A13
A12
A9
A8
TCK
TDI
FPGA_TDI
TMS
A0
A5
A1
A21
A6
A18
A2
A3
A4
A7
A17
A10
/RESET
/WE
22
24
25
27
31
32
33
34
35
36
38
39
40
42
IO_2_3
IO_5_3
IO_8_3
IO_9_3
IO_3_3
IO_4_3
IO_11_3
IO_6_3
IO_14_3
IO_15_3
IO_17_3
IO_10_3
IO_12_3
IO_16_3
TCK
TDI
TDO
TMS
5
6
N6
N7
N3
R7-4
10k
4
R7-3
10k
3
Vcc +3.3V
P20
P21
N4
DCLK
CONFIG
DATA0
STATUS
CONF_DONE
TDO
TDI
TMS
TCK
MSEL0
MSEL1
CE
R22 STAT_n
R23 DONE
M7
M8
L8
M6
R8
1k0
R9
1k0
TDI
Vcc +3.3V
2
4
6
8
10
IO_36
IO_37
IO_39
IO_38
IO_40
SD_BA1
DQ55
DQ54
SD_A7
SD_A11
SYSCLK
13
SLOE
PKTEND
35
39
WAKEUP
44
FLAGC
FLAGB
31
30
29
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
Vcc +3.3V
SLRD
SLWR
D-
DQ31
SLRD
IO_82
FD9
24LC32
1
A0
2
A1
3
A2
SDA
SCL
WP
MINI USB
8
3
9
4
CON2
5
DIP3
DCLK
DATA0
DONE
33
34
36
40
Data+
C98
100nF
Data-
IFCLK
SLOE
PKTEND
RST
CLKOUT
RSRV
42
54
14
Vcc +3.3V
WAKEUP
FLAGC
FLAGB
FLAGA
XTAL1
XTAL2
4
Y1
R13
27k
5
24MHz
C99
15pF
IO_76
FD13
FD12
IO_77
IO_81
DQ30
SD_CMD
FD11
FD10
SLWR
Vcc +3.3V
5
6
7
+5V
1
2
FD15
FD14
FD13
PA0/INT0
FD12
PA1/INT1
FD11
PA3/WU2
FD10 PA7/FLAGD/SLCS
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
D+
FD0
SDA
SCL
16
15
GND
GND
GND
GND
GND
SLRD
SLWR
SDA
SCL
9
8
7
6
1
C100
15pF
C105
1uF
C
SD_DET
CON4-1
Mini SD-Card
SD_CLK
SD_CMD
DAT3
DAT2
DAT1
DAT0
5
2
1
7
8
9
CLK
DETECT
CMD
CD/DAT3 CMN
DAT2
DAT1
DAT0
12
13
Q1-1
25MHz
IO_79
SYSCLK
Vcc +3.3V
R14 47R
22
24
25
26
27
28
29
31
10
11
12
13
14
16
17
18
CMD
INT
/IOR
/IOW
/CS
32
34
35
36
37
/RST
40
41
7
TX+
1
3
3
7
4
RX-
10
11
8
R15
6k8
46
SD
R21
180R
9
2
Vcc +2.5V
RX+
R16
50R
R17
50R
R18
50R
R19
50R
12
19
20
21
EEDIO
EECK
EECS
C101
100nF
44
XTAL1
C102
100nF
43
XTAL2
PW_RST
TEST
1
8
TXBGRES
CMD
INT
IOR
IOW
CS
R20
180R
CON5
RJLBC-060TC1
DM9000E
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
1nF
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
S2
IC7-1
P25 SYSCLK
P26
P23 FD3
P24
R25 DAT2
R24 WAKEUP
R20
T22 FD4
T23 FADR1
R17
P17
T24 PKTEND
T25 DAT1
T18
T17
T21
T20
U26 IO_164
U25 IO_165
U23 SLOE
U24 FADR0
R19 FD2
T19
U20
U21
V26 IO_163
V25 IO_162
V24 FLAGC
V23 FD6
W26 IO_160
W25 IO_161
W23 SD_DET
W24 FLAGB
U22 FD5
Y25 IO_159
Y26 IO_158
AA26 IO_156
AA25 IO_157
Y23
Y24
AB25 IO_155
AB26 IO_154
AC26 IO_152
AC25 CMD
V22 FD7
AB23 /IOR
AB24 /IOW
AA23 /CS
AA24
Y22
W21 LED_3
V21 PLL4_OUT
V20
Y21 LED_1
AD24 SD9
AD25 SD8
AE24 IO_84
AE25 /RST
AC23 SD10
S1
CFGCLK
TD+
IO_78
FD8
SD_CLK
FD0
3
TD-
DQ20
IO_71
DQ49
DQ19
IO_33
IO_34
DQ51
DQ50
IO_35
DQ52
IO_73
DQ53
IO_32
DQ48
SD_A12
CKE1
IO_70
DQ18
IO_72
IO_66
IO_69
IO_30
IO_31
DQ15
IO_29
/CAS
CKE0
DQ16
IO_68
DQ17
DQ13
IO_28
DQ14
IO_59
IO_67
/CS1
DQ10
IO_27
DQ11
DQ12
CLK11_I
IO_58
DQ9
/SD_WE
/CS0
IO_57
/RAS
IO_23
IO_24
DQ8
DQ47
IO_25
IO_26
CLK9_I
CLK9/LVDSCLK4P/INPUT(3)
CLK8/LVDSCLK4N/INPUT(3)
IO/LVDS74P/DPCLK9
IO/LVDS74N
IO
IO/LVDS75P
IO/LVDS75N
IO/LVDS76P
IO/LVDS76N
IO/LVDS77P
IO/LVDS77N
IO/LVDS78P
IO/LVDS78N
IO/LVDS79P
IO/LVDS79N
IO/VREFB4N1
IO/LVDS80P
IO/LVDS80N
IO/LVDS81P
IO/LVDS81N
IO/LVDS82P
IO/LVDS82N
IO/LVDS83P
IO/LVDS83N
IO/LVDS84P
IO/LVDS84N
IO/LVDS85P/DPCLK8
IO/LVDS85N
IO/LVDS86P
IO/LVDS86N
IO/LVDS87P
IO/LVDS87N
IO/LVDS88P
IO/LVDS88N
IO/LVDS89P
IO/LVDS89N
IO/LVDS90P
IO/LVDS90N
IO/LVDS91P
IO/LVDS91N
IO/LVDS92P
IO/LVDS92N
IO/VREFB4N0
IO
IO/LVDS93P
IO/LVDS93N
IO/LVDS94P
IO/LVDS94N
IO/LVDS95P
IO/LVDS95N
IO/LVDS96P/CDPCLK6
IO/LVDS96N
IO/LVDS97P
IO/LVDS97N
IO/LVDS98P
IO/LVDS98N
IO/LVDS99P
IO/LVDS99N
A13
B13
B14
A14
D14
F14
G14
F13
G13
C15
B15
B16
C16
D15
E15
D16
H15
H16
A17
B17
G15
F15
F16
G16
A18
B18
C17
D17
G17
F17
H17
J17
F18
G18
D18
E18
A19
B19
D19
C19
A20
B20
E20
D20
K16
J16
K17
J18
A21
B21
B22
A22
A23
B23
D21
C21
C22
C23
CLK6/LVDSCLK3P/INPUT(3)
CLK7/LVDSCLK3N/INPUT(3)
IO/LVDS127P/DPCLK6
IO/LVDS127N
IO/LVDS128P
IO/LVDS128N
IO
IO/LVDS129P
IO/LVDS129N
IO/LVDS130P
IO/LVDS130N
IO/LVDS131P
IO/LVDS131N
IO/LVDS132P
IO/LVDS132N
IO/VREFB6N0
IO
IO/LVDS133P
IO/LVDS133N
IO/LVDS134P
IO/LVDS134N
IO/LVDS135P
IO/LVDS135N
IO/LVDS136P
IO/LVDS136N
IO/LVDS137P
IO/LVDS137N
IO/LVDS138P
IO/LVDS138N
IO/LVDS139P/CDPCLK4
IO/LVDS139N
IO/LVDS140P
IO/LVDS140N
IO
IO/LVDS141P
IO/LVDS141N
IO/LVDS142P
IO/LVDS142N
IO/LVDS143P
IO/LVDS143N
IO/LVDS144P
IO/LVDS144N
IO/LVDS145P
IO/LVDS145N
IO/VREFB6N1
IO/LVDS146P
IO/LVDS146N
IO/LVDS147P
IO/LVDS147N
IO/LVDS148P
IO/LVDS148N
IO/PLL4_OUTP
IO/PLL4_OUTN
IO
IO/LVDS149P
IO/LVDS149N
IO/LVDS150P/NCEO
IO/LVDS150N/INIT_DONE
IO
52
51
50
49
48
47
46
45
25
24
23
22
21
20
19
18
38
39
LED2
LED1
B
SYSCLK
Vcc +3.3V
SW1
RELOAD
R22
10k
R23
4
1
3
2
CFG_n
100R
C103
100nF
Vcc +3.3V
FLAG
IC9-1
NC7SZ14
4
SW2
FLAG
R24
10k
R25
4
1
3
2
2
100R
C104
100nF
Vcc +3.3V
LED_1
8
1 1
R26-1 330R
LED_2
J5
VESA CON 41
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
1
3
5
7
9
IC3-1
EP2C35F672
FD15
FD14
FD13
FD12
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
R12
2k2
IC8-1
FIFOADR1
FIFOADR0
RD+
CLK2/LVDSCLK1P/INPUT(3)
CLK3/LVDSCLK1N/INPUT(3)
IO/LVDS26P/DPCLK1
IO/LVDS26N
IO/LVDS25P
IO/LVDS25N
IO/LVDS24P
IO/LVDS24N
IO/LVDS23P
IO/LVDS23N
IO/LVDS22P
IO/LVDS22N
IO/LVDS21P
IO/LVDS21N
IO/LVDS20P
IO/LVDS20N
IO/VREFB1N0
IO/LVDS19P
IO/LVDS19N
IO/LVDS18P
IO/LVDS18N
IO/LVDS17P
IO/LVDS17N
IO/LVDS16P
IO/LVDS16N
IO/LVDS15P
IO/LVDS15N
IO/LVDS14P
IO/LVDS14N
IO/LVDS13P
IO/LVDS13N
IO/LVDS12P
IO/LVDS12N
IO/DQ3L4
IO/LVDS11P/CDPCLK1
IO/LVDS11N
IO
IO/LVDS10P
IO/LVDS10N
IO/LVDS9P
IO/LVDS9N
IO/LVDS8P
IO/LVDS8N
IO/LVDS7P
IO/LVDS7N
IO
IO/VREFB1N1
IO/LVDS6P
IO/LVDS6N
IO/LVDS5P
IO/LVDS5N
IO/LVDS4P
IO/LVDS4N
IO/LVDS3P
IO/LVDS3N
IO/LVDS2P
IO/LVDS2N
IO/LVDS1P
IO/LVDS1N
IO/LVDS0P
IO/LVDS0N
IO
IO/PLL1_OUTP
IO/PLL1_OUTN
J1
JTAG
TCK
TDO
TMS
TDO
FPGA_TDI
TMS
TCK
R10
1k0
A
P2
P1
P3
P4
R2
A1
R3
A2
R4
D8
R5
T10
T9
P7
D9
P6
A3
T2
A5
T3
R6
R7
A6
T4
A7
U2
A4
U1
U9
U10
A18
U3
A20
U4
A17
V1
/RY
V2
T7
D10
T6
A21
V4
A10
V3
/WE
W2
/RESET
W1
U6
U7
/CE
U5
A19
W4
A14
W3
A8
Y1
D0
V5
D1
V6
A9
AA2
A12
AA1
A16
Y3
D12
Y4
R8
T8
IO_131
V7
D11
W6
A13
AB2
A22
AB1
D7
AA4
A11
AA3
D15
AC2
/BYTE
AC1
D5
AA5
D2
Y5
D13
AD2
IO_109
AD3
D6
AE2
IO_108
AE3
A15
AB3
D3
AB4
D4
AC3
PLL1_OUT AA7
D14
AA6
7
DCLK
CFG_n
DATA0
R7-2
10k
8
R7-1
10k
2
1
Vcc +3.3V
IC3-3
EP2C35F672
SD_A0
DQ1
IO_55
DQ2
SD_A1
DQ41
DQ42
SD_A5
IO_65
IO_64
DQ43
DQ44
SD_A2
IO_56
DQ45
DQ46
IO_21
IO_22
C5
C6
A4
B4
A5
B5
B6
A6
C4
D5
K9
J9
E8
H8
H10
G9
F9
D7
C7
D6
B7
A7
D8
C8
F10
G10
D9
C9
B8
A8
H11
H12
F11
E10
B9
A9
C10
D10
B10
A10
G11
D11
E12
D12
J13
J14
F12
G12
J10
J11
C11
B11
C12
B12
D13
C13
IO_17_4
IO_15_4
IO_12_4
IO_10_4
IO_14_4
IO_6_4
IO_11_4
IO_4_4
IO_3_4
IO_8_4
IO_5_4
IO_2_4
BLOCK_4
B
BLOCK_1
BLOCK_2
CLK2_I
FLAG
/OE
A0
FD1
DQ61
DQ62
IO_80
DQ26
DAT0
DQ63
IO_83
FD15
FD14
DQ27
DAT3
IO_74
38
37
RD-
D4
D6
IO_17_2
IO_15_2
IO_14_2/GTS1
IO_12_2
IO_11_2/GTS2
IO_10_2
IO_9_2/GSR
IO_8_2
IO_6_2
IO_5_2
IO_2_2
IO_4_2
IO_3_2
7
6
5
4
2
1
64
63
62
61
60
59
58
IC5-1
XC9572XL-VQ64
DIP0
DIP1
DIP2
DIP3
DONE
D15
/BYTE
D5
330R
SMD LED
CLK1_I
7
LED_3
6
2
D4
SMD LED
D5
SMD LED
D6
SMD LED
2 1
R26-2 330R
IO_102
IO_101
IO_100
IO_99
IO_98
IO_97
CLK13_I
IO_96
IO_95
IO_94
IO_93
IO_92
IO_91
IO_90
PLL4_OUT
IO_89
IO_88
IO_87
IO_86
IO_85
IO_84
/CS1
DQ24
DQ25
FADR1
FADR0
2
3 1
R26-3 330R
2
A
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
LED
DQ21
CLK
SD_BA0
DQMB7
DQ22
DQ23
DQ28
DQ57
DQ58
SD_A6
SD_A8
SD_A9
DQMB6
DQ56
SD_A10
DQ29
DQMB3
DQMB2
DQ60
DQ59
IO_75
J4
VESA CON 41
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
R6
10k
R4
1
IO_163
IO_165
D3
2
IO_41
IO_51
IO_42
IO_1
F20
F21
E22
D23
G21
G22
H21
E23
E24
B24
B25
C25
C24
D26
D25
J22
E26
E25
F24
F23
J21
J20
F25
F26
N18
P18
G23
G24
K22
G25
G26
H23
H24
J23
J24
H25
H26
H19
K18
K19
K21
K23
K24
L21
L20
J25
J26
L23
L24
L25
L19
K25
K26
M22
M23
M19
M20
N20
M21
M24
M25
N23
N24
N25
N26
Vcc +3.3V
IO_162
IO_164
4
3
2
1
Vcc +3.3V
IO_2
IO_44
IO_153
IO_155
IO_157
IO_159
IO_161
/CS0
IO_152
IO_154
IO_156
IO_158
IO_160
R3 10k
SW DIP-4
IO_52
CLK13/LVDSCLK6P/INPUT(3)
CLK12/LVDSCLK6N/INPUT(3)
IO/LVDS176P/DPCLK4
IO/LVDS176N
IO/DQ4B5/DQ5B14
IO/LVDS175P
IO/LVDS175N
IO/LVDS174P
IO/LVDS174N
IO/LVDS173P
IO/LVDS173N
IO/LVDS172P
IO/LVDS172N
IO/LVDS171P
IO/LVDS171N
IO/VREFB7N1
IO/LVDS170P
IO/LVDS170N
IO/LVDS169P
IO/LVDS169N
IO/LVDS168P
IO/LVDS168N
IO/LVDS167P
IO/LVDS167N
IO/LVDS166P
IO/LVDS166N
IO/LVDS165P/DPCLK5
IO/LVDS165N
IO/LVDS164P
IO/LVDS164N
IO/LVDS163P
IO/LVDS163N
IO/LVDS162P
IO/LVDS162N
IO/LVDS161P
IO/LVDS161N
IO/LVDS160P
IO/LVDS160N
IO/LVDS159P
IO/LVDS159N
IO/LVDS158P
IO/LVDS158N
IO/VREFB7N0
IO
IO/LVDS157P
IO/LVDS157N
IO/LVDS156P
IO/LVDS156N
IO/LVDS155P
IO/LVDS155N
IO/LVDS154P/CDPCLK3
IO/LVDS154N
IO/LVDS153P
IO/LVDS153N
IO/LVDS152P
IO/LVDS152N
IO/LVDS151P
IO/LVDS151N
5
6
7
8
R5
10k
R11
2k2
IC4-1
CY7C68013A
IO/PLL2_OUTN
IO/PLL2_OUTP
IO/LVDS100P
IO/LVDS100N
IO/LVDS101P
IO/LVDS101N
IO
IO/LVDS102P
IO/LVDS102N
IO/LVDS103P
IO/LVDS103N
IO/LVDS104P
IO/LVDS104N
IO/LVDS105P
IO/LVDS105N
IO/VREFB5N0
IO/LVDS106P
IO/LVDS106N
IO/LVDS107P
IO/LVDS107N
IO/LVDS108P
IO/LVDS108N
IO/LVDS109P
IO/LVDS109N
IO/LVDS110P
IO/LVDS110N
IO/LVDS111P
IO/LVDS111N
IO
IO/LVDS112P/CDPCLK5
IO/LVDS112N
IO/LVDS113P
IO/LVDS113N
IO/LVDS114P
IO/LVDS114N
IO/LVDS115P
IO/LVDS115N
IO
IO/LVDS116P
IO/LVDS116N
IO
IO/LVDS117P
IO/LVDS117N
IO/LVDS118P
IO/LVDS118N
IO/LVDS119P
IO/LVDS119N
IO/VREFB5N1
IO/LVDS120P
IO/LVDS120N
IO
IO/LVDS121P
IO/LVDS121N
IO/LVDS122P
IO/LVDS122N
IO/LVDS123P
IO/LVDS123N
IO/LVDS124P
IO/LVDS124N
IO/LVDS125P
IO/LVDS125N
IO/LVDS126P/DPCLK7
IO/LVDS126N
CLK4/LVDSCLK2P/INPUT(3)
CLK5/LVDSCLK2N/INPUT(3)
CLK13_I AF14
AE14
IO_96
AE15
SD7
AD15
IO_130 AC14
IO_128 AA13
Y13
IO_127 AA14
Y14
Y15
AA15
IO_144 AB15
IO_129 AC15
SD5
AE16
SD6
AD16
IO_146 AC16
W15
W16
IO_95
AF17
IO_94
AE17
SD3
AC17
SD4
AD17
IO_147 AA16
Y16
IO_93
AF18
SD2
AE18
IO_92
AF19
IO_91
AE19
IO_148 AB18
SD1
AC18
W17
V17
IO_149 AA17
AA18
SD0
AD19
IO_151 AC19
IO_90
AF20
IO_150 AE20
SD15
AB20
IO_153 AC20
AF21
IO_89
AE21
Y18
AA20
U17
U18
V18
W19
IO_88
AF22
IO_87
AE22
INT
AC21
SD14
AD21
SD11
AD23
SD13
AD22
SD12
AC22
LED_2 AB21
IO_86
AF23
IO_85
AE23
Vcc +3.3V
IO_143
IO_145
IO_147
IO_149
IO_151
DIP3
DIP2
DIP1
DIP0
IO_142
IO_144
IO_146
IO_148
IO_150
SW3
IO_126
IO_98
IO_145
IO_97
CAS
RAS
WE
SCL
SDA
IO_125
66
65
67
142
141
IO_133
IO_135
IO_137
IO_139
IO_141
/CAS
/RAS
/SD_WE
CS1
CS0
IO_132
IO_134
IO_136
IO_138
IO_140
71
69
IO_53
IO_12
IO_11
IO_9
IO_10
IO_50
IO_49
IO_48
IO_47
IO_8
IO_7
IO_6
IO_5
IO_45
IO_46
IO_3
IO_4
IO_43
CLK2_I
IO_126
IO_128
IO_130
IO_131
/CS1
/CS0
CKE1
CLK1
CKE0
CLK0
DQ3
DQ33
DQ32
DQ0
IO/ASDO
IO/NCSO
IO/LVDS49P/CRC_ERROR
IO/LVDS49N/CLKUSR
IO/PLL3_OUTP
IO/PLL3_OUTN
IO/LVDS48P
IO/LVDS48N
IO/LVDS47P
IO/LVDS47N
IO/LVDS46P
IO/LVDS46N
IO/LVDS45P
IO/LVDS45N
IO
IO/VREFB2N0
IO/LVDS44P
IO/LVDS44N
IO
IO/LVDS43P
IO/LVDS43N
IO/LVDS42P
IO/LVDS42N
IO/LVDS41P
IO/LVDS41N
IO
IO/LVDS40P
IO/LVDS40N
IO/LVDS39P
IO/LVDS39N
IO/LVDS38P/CDPCLK0
IO/LVDS38N
IO/LVDS37P
IO/LVDS37N
IO/LVDS36P
IO/LVDS36N
IO/LVDS35P
IO/LVDS35N
IO/LVDS34P
IO/LVDS34N
IO/LVDS33P
IO/LVDS33N
IO/LVDS32P
IO/LVDS32N
IO/VREFB2N1
IO/LVDS31P
IO/LVDS31N
IO/LVDS30P
IO/LVDS30N
IO
IO/LVDS29P
IO/LVDS29N
IO
IO/LVDS28P
IO/LVDS28N
IO/LVDS27P/DPCLK0
IO/LVDS27N
CLK0/LVDSCLK0P/INPUT(3)
CLK1/LVDSCLK0N/INPUT(3)
IO_124
IO_125
IO_127
IO_129
PLL1_OUT
/RY
IO_54
DQ5
IO_14
IO_13
E3
D3
B2
B3
E5
F6
C2
C3
G5
G6
F3
F4
D2
D1
F7
J5
J8
J7
H6
E2
E1
K6
K5
G4
G3
J6
K8
K7
F2
F1
G1
G2
H3
H4
J3
J4
H2
H1
J2
J1
K4
K3
K1
K2
L4
N9
P9
L7
L6
L9
L2
L3
L10
M4
M5
M3
M2
N2
N1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
A4
68
74
62
61
DQ36
DQ38
IO_18
IO_19
DQ37
DQMB0
IO_17
DQMB4
DQ6
DQ7
DQ34
DQ35
IO_16
IO_15
DQMB1
DQ4
Vcc +3.3V
RY/BY
CKE1
CLK
CKE0
CLK
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
J7
CONN PLUG 32x2
/CE
C
Vcc +3.3V
DQMB7
DQMB6
DQMB5
DQMB4
DQMB3
DQMB2
DQMB1
DQMB0
138
136
134
132
128
126
124
122
100
98
96
94
90
88
86
84
54
52
50
48
44
42
40
38
20
18
16
14
10
8
6
4
137
135
133
131
127
125
123
121
99
97
95
93
89
87
85
83
53
51
49
47
43
41
39
37
19
17
15
13
9
7
5
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
118
116
26
24
117
115
25
23
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
IO_114
IO_113
IO_143
IO_102
IO_112
IO_111
IO_101
IO_100
IO_136
IO_124
IO_110
IO_99
CE
WE
OE
WP/ACC
RESET
BYTE
DQMB7
DQMB6
DQMB5
DQMB4
DQMB3
DQMB2
DQMB1
DQMB0
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
IO_138
IO_141
IO_140
IO_142
R2
10k
110
106
70
112
111
109
105
104
103
34
32
30
33
31
29
IO_134
IO_137
Vcc +3.3V
SD_BA1
SD_BA0
SD_A12
SD_A11
SD_A10
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
SD_A3
SD_A2
SD_A1
SD_A0
IO/LVDS50N/DEV_CLRN
IO/LVDS50P
IO/LVDS51P
IO/LVDS51N
IO/LVDS52P
IO/LVDS52N
IO/LVDS53P/CDPCLK7
IO/LVDS53N
IO/LVDS54P
IO/LVDS54N
IO/LVDS55P
IO/LVDS55N
IO/VREFB3N1
IO
IO/LVDS56P
IO/LVDS56N
IO
IO/LVDS57P
IO/LVDS57N
IO
IO/LVDS58P
IO/LVDS58N
IO/LVDS59P
IO/LVDS59N
IO/LVDS60P
IO/LVDS60N
IO/LVDS61P
IO/LVDS61N
IO/LVDS62P/DPCLK11
IO/LVDS62N
IO/LVDS63P
IO/LVDS63N
IO/LVDS64P
IO/LVDS64N
IO/LVDS65P
IO/LVDS65N
IO/LVDS66P
IO/LVDS66N
IO/LVDS67P
IO/LVDS67N
IO
IO/VREFB3N0
IO/LVDS68P
IO/LVDS68N
IO/LVDS69P
IO/LVDS69N
IO/LVDS70P
IO/LVDS70N
IO/LVDS71P
IO/LVDS71N
IO/LVDS72P
IO/LVDS72N
IO/LVDS73P/DPCLK10
IO/LVDS73N
CLK11/LVDSCLK5P/INPUT(3)
CLK10/LVDSCLK5N/INPUT(3)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IO_132
IO_116
IO_115
IO_103
IO_139
IO_135
F2
A5
G2
B4
/RESET B5
/BYTE
F7
G7
F6
G6
F5
G4
F4
G3
F3
E6
H6
E5
H5
H4
E4
H3
E3
IO_118
IO_133
/CE
/WE
/OE
DQ15/A-1
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
IO/LVDS200N/DEV_OE
IO/LVDS200P
IO/LVDS199P
IO/LVDS199N
IO/LVDS198P
IO/LVDS198N
IO/LVDS197P/CDPCLK2
IO/LVDS197N
IO/LVDS196P
IO/LVDS196N
IO/LVDS195P
IO/LVDS195N
IO/VREFB8N1
IO
IO/LVDS194P
IO/LVDS194N
IO
IO/LVDS193P
IO/LVDS193N
IO/LVDS192P
IO/LVDS192N
IO
IO/LVDS191P
IO/LVDS191N
IO/LVDS190P
IO/LVDS190N
IO/LVDS189P
IO/LVDS189N
IO/LVDS188P/DPCLK2
IO/LVDS188N
IO/LVDS187P
IO/LVDS187N
IO/LVDS186P
IO/LVDS186N
IO/LVDS185P
IO/LVDS185N
IO/LVDS184P
IO/LVDS184N
IO/LVDS183P
IO/LVDS183N
IO
IO/VREFB8N0
IO/LVDS182P
IO/LVDS182N
IO/LVDS181P
IO/LVDS181N
IO/LVDS180P
IO/LVDS180N
IO/LVDS179P
IO/LVDS179N
IO/LVDS178P
IO/LVDS178N
IO/LVDS177P/DPCLK3
IO/LVDS177N
CLK15/LVDSCLK7P/INPUT(3)
CLK14/LVDSCLK7N/INPUT(3)
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
AE4
AF4
AC5
AC6
AD4
AD5
AE5
AF5
AD6
AD7
V10
V9
AC7
W8
W10
Y10
AB8
AC8
AD8
AE6
AF6
AA9
AA10
AB10
AA11
Y11
AE7
AF7
AE8
AF8
W11
W12
AC9
AC10
AE9
AF9
AD10
AC11
AE10
AF10
AB12
AC12
AD11
AE11
V14
V13
V11
U12
AA12
Y12
AD12
AE12
AE13
AF13
AC13
AD13
B8
C5
D4
D5
C4
B3
E7
D7
C7
A7
B7
D6
C6
A6
B6
A3
C3
D3
B2
A2
C2
D2
E2
IO_107
IO_106
IO_122
IO_120
IO_123
IO_121
IO_105
IO_104
IO_119
IO_117
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CON3-1
SDRAM SO-DIMM
IO_123
IO_122
IO_121
IO_120
IO_119
IO_118
IO_117
IO_116
IO_115
IO_114
IO_113
IO_112
IO_111
IO_110
IO_109
IO_108
IO_107
IO_106
IO_105
IO_104
IO_103
IC6-1
S29GL128N
RJ45 CON
SD_A4
DQ40
IO_20
SD_A3
IO_60
IO_61
IO_63
IO_62
DQMB5
DQ39
Vcc +3.3V
Title
Altera Cyclone II Board
Size
Custom
Date:
5
4
3
2
Document Number
1/2
Monday, April 23, 2007
1
Rev
1.1
Sheet
1
of
1