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About the X6 XMC Modules
The P16 connector pinout is shown in the hardware chapter.
GTX Connections to P16
Pinouts for the P16 connector showing the transmit and receive pair locations are given in the Connectors section. The
following table gives the Rocket I/O pin allocations on the Virtex-6 that connect to each of the P16 signals.
Link
Lane P16 Pins
P16 Signal
Virtex-6 FG1156 Pin
Number
Virtex-6 GTX Signal Identifier
0
0
A1/B1
TXP0/N0
AP1/AP2
GTXTXP0_112/GTXTXN0
0
0
A11/B11
RXP0/N0
AP5/AP6
GTXRXP0_112/GTXRXN0
0
1
D1/E1
TXP1/N1
AN3/AN4
GTXTXP1_112/GTXTXN1
0
1
D11/E11
RXP1/N1
AM5/AM6
GTXRXP1_112/GTXRXN1
0
2
A3/B3
TXP2/N2
AM1/AM2
GTXTXP2_112/GTXTXN2
0
2
A13/B13
RXP2/N2
AL3/AL4
GTXRXP2_112/GTXRXN2
0
3
C3/D3
TXP3/N3
AK1/AK2
GTXTXP3_112/GTXTXN3
0
3
D13/E13
RXP3/N3
AJ3/AJ4
GTXRXP3_112/GTXRXN3
1
0
A5/B5
TXP4/N0
AH1/AH2
GTXTXP0_113/GTXTXN0
1
0
A15/B15
RXP4/N0
AG3/AG4
GTXRXP0_113/GTXRXN0
1
1
D5/E5
TXP5/N1
AF1/AF2
GTXTXP1_113/GTXTXN1
1
1
D15/E15
RXP5/N1
AF5/AF6
GTXRXP1_113/GTXRXN1
1
2
A7/B7
TXP6/N2
AD1/AD2
GTXTXP2_113/GTXTXN2
1
2
A17/B17
RXP6/N2
AE3/AE4
GTXRXP2_113/GTXRXN2
1
3
C7/D7
TXP7/N3
AB1/AB2
GTXTXP3_113/GTXTXN3
1
3
D17/E17
RXP7/N3
AC3/AC4
GTXRXP3_113/GTXRXN3
Table 18. P16 GTX Assignments and Use
GTX Electrical Characteristics
The GTX lanes are high speed serial port connections to the Virtex-6. These are specialized serial ports intended for use as
communications ports and include many advanced features for data transmission and reception at speeds up to 5 Gbps. They
are generally not useful for any other purpose.
The GTX lanes must be AC-couple at the transmitter end. Receive (RX) lanes to the X6 must be AC-coupled at the
transmitter. Transmit lanes are AC-coupled on the X6. IO standard is CML.
X6-RX User's Manual
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