Download TE0720 User Manual

TE0720 User Manual
Revision: 0.2
PHY LED Control
The Ethernet PHY LEDs are not directly available on the B2B Connectors.
The SC can however remap the PHY LED signals.
By default the NOSEQ pin is converted to an output pin after the boot process and PHY LED0 is mapped to
this B2B pin. During the boot process it is also possible to change this behaviour.
PHY LED0, LED1 and LED2 are also made available to be used in the FPGA fabric where they can be
routed to any free FPGA pins.
Signal
Name
B2B
/FPGA
LED
#
NOSEQ
JM1.
LED0
PHY default function
After boot process PHY LED0 is mapped to
NOSEQ
XIO4
M15
LED0
1G/100M: ON=Link, Blink=Activity, OFF=No
Link
XIO5
N15
LED1
XIO6
P16
LED2
100M/10M: ON=Link, Blink=Activity, OFF=No
Link
Note: must be enabled in software
SC rev 0.2 default mapping of Ethernet LED's to B2B and or FPGA Pins
Marvell PHY LED pins are multipurpose pins with shared and configurable functions.
Default behavior
If Marvell PHY LED control register is not changed during boot process then PHY power up default LED
settings apply. Please consult Marvell datasheet for exact features.
PHY LED Demo Design
This demo is for TE0701, for other carrier or custom base board please change user LED mappings as
needed.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PHY_LED_TEST is Port (
PHY_LED0_IN : in STD_LOGIC; -- forwarded signal from PHY LED[0] output
PHY_LED1_IN : in STD_LOGIC; -- forwarded signal from PHY LED[1] output
PHY_LED2_IN : in STD_LOGIC; -- forwarded signal from PHY LED[1] output
PHY_LED0_OUT : out STD_LOGIC; -- USER I/O Signal in PMOD J5
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