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Preliminary User’s Manual
IMAPCAR2 Video I/F Board
Hardware
Document No. U19880EE1V0UM00
Date Published: July 2009
© NEC Electronics (Europe) GmbH
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The information in this document is current as of July 2009. The information is subject to
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check with an NEC Electronics sales representative for availability and additional
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that may appear in this document.
•
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•
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•
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Preliminary User’s Manual U19880EE1V0UM00
2
Table of Contents
1
Introduction.......................................................................................................................................5
2
Specification .....................................................................................................................................5
3
General overview and block diagrams .............................................................................................6
4
3.1
Video Board IF overview............................................................................................................6
3.2
Power Supply block diagram .....................................................................................................7
3.3
Reset block diagram ..................................................................................................................8
3.4
Clock block diagram...................................................................................................................9
3.5
PCB overview...........................................................................................................................10
Board description ...........................................................................................................................13
4.1
5
Switch description ....................................................................................................................13
4.1.1
SW1 – NTSC decoder ......................................................................................................13
4.1.2
SW6 – user FPGA general purpose SW ..........................................................................14
4.1.3
SW7 - user FPGA general purpose SW ...........................................................................14
4.1.4
SW8 – NTSC encoder ......................................................................................................15
4.1.5
SW9 – general purpose SW for graphic FPGA ................................................................15
4.1.6
SW10 – general purpose SW for graphic FPGA ..............................................................16
4.1.7
SW_HRESET....................................................................................................................16
4.1.8
SW_PRESET....................................................................................................................16
4.2
Jumper description...................................................................................................................17
4.3
LED description........................................................................................................................18
4.4
Connector description ..............................................................................................................20
4.4.1
Video I/O connector (CN1/CN6) .......................................................................................20
4.4.2
Supervisor connector (CN2/CN7) .....................................................................................21
4.4.3
Video I/O connector 2 (CN3/CN9) ....................................................................................22
4.4.4
Plug-in phone jack for CH0 differential motion (J1) ..........................................................23
4.4.5
Plug-in phone jack for CH0 differential motion (J2) ..........................................................23
4.4.6
Plug-in phone jack for CH0 differential motion (J3) ..........................................................24
4.4.7
Plug-in phone jack for CH0 differential motion (J4) ..........................................................24
4.4.8
NTSC input RCA Jack (J5) ...............................................................................................25
4.4.9
NTSC output RCA Jack (J6).............................................................................................25
4.4.10
JTAG connector ................................................................................................................25
4.4.11
Power supply terminal stand (CN8) ..................................................................................26
Hardware component .....................................................................................................................27
5.1
FPGA .......................................................................................................................................27
5.1.1
Image System Block .........................................................................................................27
5.1.2
Communication system block ...........................................................................................31
5.1.3
Reset block .......................................................................................................................32
5.1.4
Pin assignment .................................................................................................................33
Preliminary User’s Manual U19880EE1V0UM00
3
6
5.2
FPGA ROM configuration ........................................................................................................39
5.3
High speed status random access memory.............................................................................39
5.4
LVDS........................................................................................................................................39
5.5
NTSC decoder/encoder ...........................................................................................................40
5.6
RS485 transceivers..................................................................................................................41
5.7
Equipment connection cable....................................................................................................41
Revision history ..............................................................................................................................42
Preliminary User’s Manual U19880EE1V0UM00
4
IMAPCAR2 Video I/F Board
1
Introduction
The Video I/F board is to interface external imagers and display with the
IMAPCAR2 evaluation board.
2
Specification
The Video I/F board is composed by the following main components:
FP G A
X ilinx X C 3S 2000-4FG G 676C (676pinB G A )
X ilinx X C F08P V O G 48C (48pinTS O P )
S partan3
R O M for FP G A config
LV D S
TH ine TH C V 213(48pinTQ FP ) Transm itter
TH ine TH C V 214(48pinTQ FP ) R eceiver
･18 bits ×20M H z fixation use
･18 bits ×20M H z fixation use
R S485
Linear Technology LTC 2850IM S 8(8pinM SO P ) Transceiver
･20M bps
N TS C /P A L
O K I M L86V 7655(100pinTQ FP )
O K I M L86V 7666(100pinTQ FP )
･N TSC /P A L encoder
･N TSC /P A L decoder
SR A M
N EC μP D 444016LG 5-A 8-7JF-A (44pinTS O P )
･4M bit(256K w ord×16bit)
D ip S W
C O P A L C H S -10TB (20pinTS O P )
C O P A L C H S -8TB (16pinTSO P )
･S W 1
･S W 6/7/8/9/10
P ush S W
FU JIS O K U S M T3-01-Z(S M D 7X 6)
･S W _H R ESET/S W _P R ES ET
LED
R O H M S M L-210V TT86 R ED
R O H M S M L-210P TT86 G R EEN
･LED 15
･LED 1～14､LED 16～23
P ow er supply Input pow er supply
･12V (Input range:4.5V -14V ) and +1A or m ore
Preliminary User’s Manual U19880EE1V0UM00
5
IMAPCAR2 Video I/F Board
3
General overview and block diagrams
3.1 Video Board IF overview
R
x
T
x
R
x
T
x
R
x
R
x
T
x
T
x
NTSC
DEC
CN_NTo
CN_NTi
CH3
CH2
CH1
CH0
The following figure is the general overview on the IMAPCAR2 video IF board
NTSC
ENC
FPGA
Video2
connector
FPGA
SRAM
SV connector
Video
connector
IMAPCAR2 board
Preliminary User’s Manual U19880EE1V0UM00
6
IMAPCAR2 Video I/F Board
3.2 Power Supply block diagram
The following figure describes the block diagram of the power supply.
Power Module
DC12V
DC3.3V
PTH08T240WAZ
LVDS
RX/TX
×8
RS485
×4
SRAM
×3
NTSC
DEC
NTSC
ENC
DC-DC Converter
EN5335QI
DC1.2V
FPGA
Linear Regulator
PQ1U181M2ZP
DC2.5V
×2
JTAG
Soket
Regulator(LDO)
PQ1U181M2ZP
PROM
DC1.8V
Preliminary User’s Manual U19880EE1V0UM00
7
IMAPCAR2 Video I/F Board
3.3 Reset block diagram
The following system describes the reset management of the entire system
(including the IMAPCAR2-300 evaluation board)
IMAPCAR2 board
SV board
VIDEO IO board
G _SRESET G _HRESET -
CAR 2
ＲＥＳＥＴ
Flash
Writer
MA 3
SJ 2
FPGA
USB
C 2_RESET -
Delay
Circuit
汎用Port
ＲＥＳＥＴ
Delay
Circuit
SRESET -
SW H RESET
FPGA
SW H RESET
DONE
+3.3V
+3.3V
Voltage
monitoring
Delay
Circuit
open
ＪＴＡＧ
DONE
DONE
Voltage
monitoring
PROG _B
SW P RESET
ＪＴＡＧ
FPGA
SW H RESET
+3.3V
C 2_RESET -
Voltage
monitoring
PROG _B
SW P RESET
ＲＥＳＥＴ
ＲＥＳＥＴ
PROG _B
SW P RESET
ＪＴＡＧ
ＪＴＡＧ
G _PRESET -
Green line
: Power reset.
Red line
: hard reset.
Blue Line
: Soft Reset
The following figure describes the reset schematic for the IMAPCAR2 video I/F
board reset.
3.3V
3.3V
VIDEO SIDE
FPGA
DONE
RESET IC
GROBAL_PRESET
XP_PROG
PROG_B
3.3V
SV Connector
SW_PRESET
DX_DONE
FPGA
ROM
2.5V
3.3to2.5V
/ CF
3.3V
GROBAL_HRESET
XP_DONE
3.3V
SW_HRESET
USER SIDE
FPGA
DONE
PROG_B
DX_DONE
FPGA
ROM
/ CF
Preliminary User’s Manual U19880EE1V0UM00
8
IMAPCAR2 Video I/F Board
3.4 Clock block diagram
The following figure describes the block diagram of the system clock.
Preliminary User’s Manual U19880EE1V0UM00
9
IMAPCAR2 Video I/F Board
3.5 PCB overview
The following figure shows a PCB overview
Preliminary User’s Manual U19880EE1V0UM00
10
IMAPCAR2 Video I/F Board
HRESET
PRESET
DC3.3V→
VideoIO
DC2.5V
connector
Power supply
terminal stand
LED2
JTAG
GND
DC12V
connector
SRAM
PROM
DC12V→
DC3.3V
SRAM
SW
SW
UserFPGA
SW
SRAM
SW
SW
LED2 LED8
DC3.3V→
VideoIO2
LED1 LED4
DC1.2V
connector
JTAG connector
(for Graphic-FPGA)
PROM
SV
Graphic-
connector
LED9
FPGA
NTSC
decoder
LVDS Tx
SW
Input
Output
RCA Jack
RCA Jack
LVDS Tx
LVDS Tx
LVDS Tx
Plug-in phone jack for LVDS
Preliminary User’s Manual U19880EE1V0UM00
11
IMAPCAR2 Video I/F Board
VideoIO
connector
DC3.3V→
DC1.8V
VideoIO2
connector
SV connector
RS485
NTSC
LVDS
LVDS
LVDS
LVDS
Preliminary User’s Manual U19880EE1V0UM00
12
IMAPCAR2 Video I/F Board
4
Board description
4.1 Switch description
4.1.1
No
SW1 – NTSC decoder
Name
1
2
Initial
Configuration
OFF
[3 :1] : GAINS 2-0
OFF
3
OFF
4
OFF
[5-4] :MODE 1-0
5
OFF
6
OFF
[7-6] : MODE3-2
7
ON
8
M[8]
OFF
9
M[9]
OFF
10
Not used
OFF
Description
Amplifier gain setting
SW1.3-1 is active only if SW1.8：OFF
[SW1.3-1] Gain values (x times)
[OFF：OFF：OFF] 0.55
[OFF：OFF：ON ] 0.70
[OFF：ON ：OFF] 0.93
[OFF：ON ：ON ] 1.21
[ON ：OFF：OFF] 1.60
[ON ：OFF：ON ] 2.09
[ON ：ON ：OFF] 2.65
[ON ：ON ：ON ] 3.45
※SW ON•"1"、OFF•"0"
Input mode
- Register $00/MRA[0]=0 (default value)
SW1.5：OFF•NTSC / ON•PAL
- Invalid when register $02/MRC[7]=1(NTSC/PAL auto recognition)
SW1.4: OFF ->ITU-R BT.601 / ON -> Square Pixel
Setting for NTSC 4fsc is available only by register $00/MRA[5:3].
※SW ON•"1"、OFF•"0"
External output pin configuration
- Register $00/MRA[0]=0 (default value)
[SW1.7-6]
[OFF：OFF] ITU-R BT.656(10bit Y/CbCr)
[OFF：ON ] 10bit Y/CbCr (10bit Y/CbCr+Sync.)
[ON ：OFF] 20bit Y/CbCr (10bit Y + 10bit CbCr+Sync.)
[ON ：ON ] 24bit RGB/YCbCr (RGB orYCbCr 8+8+8bit+Sync.)
- Register $10/CHRCB[1]=0：24bitRGB / 1：24bitYCbCr
※SW ON•"1"、OFF•"0"
Selecting method to set the amplifier gain and input terminal
OFF: External pin mode
Amplifier gain setting: use SW1.3-1
Input terminal setting: use pin92-94 INS[2:0]
ON: Register mode
Amplifier gain setting: use register $1E/ADC2[6:4]
Input terminal setting: use register $1D/ADC1[2:0]
※SW ON•"1"、OFF•"0"
I2C Slave address selection
OFF：1000 001X (X: 0=Write 1=Read)
ON ：1000 011X (X: 0=Write 1=Read)
※SW ON•"1"、OFF•"0"
Preliminary User’s Manual U19880EE1V0UM00
13
IMAPCAR2 Video I/F Board
4.1.2
SW6 – user FPGA general purpose SW
No
Name
1
2
3
4
5
6
7
8
Not used
Reserved
Reserved
Not used
Not used
Not used
Not used
Not used
4.1.3
Initial
Configuration
Description
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
SW7 - user FPGA general purpose SW
No
Name
1
2
3
4
5
6
7
8
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Initial
Configuration
Description
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Preliminary User’s Manual U19880EE1V0UM00
14
IMAPCAR2 Video I/F Board
4.1.4
SW8 – NTSC encoder
Initial
No
Name
1
2
3
[3 :1] MOD2-0
OFF
OFF
OFF
4
IPAL
OFF
5
IRGB
OFF
6
IPRG
OFF
7
I444
OFF
8
OPRD
OFF
4.1.5
No
Input mode control
※SW ON•"1"、OFF•"0"
For more data, please see ML86V7655 data-sheet
PAL/NTSC mode select
※SW ON•"1"、OFF•"0"
ON ：PAL、 OFF：NTSC
RGB/YCbCr Input select
※SW ON•"1"、OFF•"0"
ON ：RGB Input、 OFF：YCbCr input
Progressive / Interlaced input select
※SW ON•"1"、OFF•"0"
ON ：Progressive input, OFF：interlaced input
4:2:2/4:4:4 input select
※SW ON•"1"、OFF•"0"
ON ：4:4:4 input、 OFF：4:2:2 input
Progressive / Interlaced output select
※SW ON•"1"、OFF•"0"
ON ：Progressive output, OFF：interlaced output
SW9 – general purpose SW for graphic FPGA
Name
1
Initial
OFF
2
OFF
Not used
Not used
Not used
Not used
Not used
Not used
Description
Configuration
Select Mode
3
4
5
6
7
8
Description
Configuration
[SW9.2-1] ※SW ON•"0"、OFF•"1"
[ ON , ON ]
： Mode 0
[ ON , OFF ] ： Mode 1
[ OFF , ON ] ： Mode 2
[ OFF , OFF ] ： Mode 3
For details of each mode, please refer to figure 5.1.1 to 5.1.4
When connecting 1394 board, mode is changed to mode 2 forcedly.
OFF
OFF
OFF
OFF
OFF
OFF
Preliminary User’s Manual U19880EE1V0UM00
15
IMAPCAR2 Video I/F Board
4.1.6
SW10 – general purpose SW for graphic FPGA
No
Name
1
2
3
4
5
6
7
8
reserved
reserved
reserved
reserved
Not used
Not used
Not used
reserved
4.1.7
Initial
Configuration
Description
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
SW_HRESET
It is a button switch for board reset.
By pushing this switch, the following device will be reset and the FPGA will be
reconfigured as well.
4.1.8
•
NTSC decoder,
•
NTSC encoder, and
•
FPGA internal circuit
SW_PRESET
It is a button switch for hard reset.
By pushing this switch, the following device will be reset.
•
NTSC decoder,
•
NTSC encoder, and
•
FPGA internal circuit
Preliminary User’s Manual U19880EE1V0UM00
16
IMAPCAR2 Video I/F Board
4.2 Jumper description
•
Power supply (12V) is supplied through the JP1: VideoIO connector.
Please make it to OPEN when it is unnecessary.
o
Initial condition (when the board is shipped by NEC): SHORT.
•
Power supply (12V) is supplied through the JP2: VideoIO2 connector.
Please make it to OPEN when it is unnecessary.
o
Initial condition (when the board is shipped by NEC):SHORT.
•
Power supply (12V) is supplied through the JP3: SV connector.
Please make it to OPEN when it is unnecessary.
o
•
Initial condition (when the board is shipped by NEC):SHORT.
External connecting the I2C bus of JP4: IC13 (NTSC decoder) and IC14
(NTSC encoder) becomes possible.
o
Initial condition (when the board is shipped by NEC):OPEN.
Preliminary User’s Manual U19880EE1V0UM00
17
IMAPCAR2 Video I/F Board
4.3 LED description
The following table describes the LEDS related to user FPGA
No
Color
Name
State after
reset
LED1
Green
PLL Lock status
On
LED2
LED3
LED4
LED5
LED6
LED7
LED8
Green
Green
Features
PLL Lock : ON
PLL unlock : OFF
Off
Off
Off
Off
Off
Off
Off
Green
Green
Green
Green
Green
The following table describes the LEDS related to user NTSC device
No
Color
LED9
Green
LED10
Green
LED11
Green
LED12
Green
LED13
Green
LED14
Green
Name
LVDS RX（IC1) PLL LOCK
ON：PLL locked
OFF：PLL unlocked
LVDS RX（IC4) PLL LOCK
ON：PLL locked
OFF：PLL unlocked
LVDS RX（IC7) PLL LOCK
ON：PLL locked
OFF：PLL locked
LVDS RX（IC8) PLL LOCK
ON：PLL locked
OFF：PLL unlocked
NTSC decoder
(ML86V7666) STATUS1
ON：PLL locked
OFF：PLL unlocked
NTSC decoder
(ML86V7667) STATUS2
ON：PAL
OFF：NTSC
State after
reset
Features
Off
LED9 indicates the status of receiving from J1
connector.
Off
LED10 indicates the status of receiving from J2
connector.
Off
LED11 indicates the status of receiving from J3
connector.
Off
LED12 indicates the status of receiving from J4
connector.
Off
For more details, please check ML86V7666 user’s
manual
Off
For more details, please check ML86V7667 user’s
manual
Preliminary User’s Manual U19880EE1V0UM00
18
IMAPCAR2 Video I/F Board
The following table describes the LEDS related to graphic FPGA
No
LED15
LED16
LED17
LED18
LED19
LED20
LED21
LED22
Color
Red
Green
Green
Green
Green
Green
Green
Green
Name
State after
reset
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Off
Off
Off
Off
Off
Off
Off
Off
Features
The following table describes the LEDS related to FPGA reconfiguration
completion
No
Color
Name
Normal
State
LED23
Red
FPGA configuration completion
ON : config OK
OFF : config not OK
ON
Features
Check if the FPGA configuration is finished correctly
Preliminary User’s Manual U19880EE1V0UM00
19
IMAPCAR2 Video I/F Board
4.4 Connector description
4.4.1
Video I/O connector (CN1/CN6)
Manufacturer:
SAMTEC
Model:
A1
B1
QTH-060-05-L-D-A/QSH-060-01-L-D-A
A30 A31
A60
A60
A31 A30
A1
B30 B31
CN1
B60
B60
B31 B30
CN6
B1
Meaning of the IO field value is seen from Video IF board side.
D escription
S ignal N am e
P IO _V IO [4]
O D D EV EN I[0]
H S YN C I_B [0]
SC LK I[0]
ch0_idata[0]/SR I[0]
C A R 2 V IN C h0 ch0_idata[2]/SR I[2]
ch0_idata[4]/SR I[4]
ch0_idata[6]/SR I[6]
ch0_idata[8]/SR I[8]
ch0_idata[10]/S R I[10]
ch0_idata[12]
ch0_idata[14]
P IO _V IO [5]
O D D EV EN I[1]
H S YN C I_B [1]
SC LK I[1]
ch1_idata[0]/SR I[12]
C A R 2 V IN ch1 ch1_idata[2]/SR I[14]
ch1_idata[4]/SR I[16]
ch1_idata[6]/SR I[18]
ch1_idata[8]/SR I[20]
ch1_idata[10]/S R I[22]
ch1_idata[12]
ch1_idata[14]
P IO _V IO [10]
O D D EV EN I[2]
H S YN C I_B [2]
SC LK I[2]
ch2_idata[0]/SR I[24]
ch2_idata[2]/SR I[26]
C A R 2 V IN ch2 ch2_idata[4]/SR I[28]
ch2_idata[6]/SR I[30]
ch2_idata[8]/SR I[32]
ch2_idata[10]/S R I[34]
ch2_idata[12]/S R I[36]
ch2_idata[14]/S R I[38]
P IO _V IO [11]
O D D EV EN O 0
C A R 2 V O U Tcom m onH S YN C O 0_B
SC LK O 0
ch0_odata[0]/S R O [0]
ch0_odata[2]/S R O [2]
C A R 2 V O U T ch0
ch0_odata[4]/S R O [4]
ch0_odata[6]/S R O [6]
ch1_odata[0]/S R O [8]
ch1_odata[2]/S R O [10]
C A R 2 V O U T ch1
ch1_odata[4]/S R O [12]
ch1_odata[6]/S R O [14]
ch2_odata[0]/S R O [16]
ch2_odata[2]/S R O [18]
C A R 2 V O U T ch2
ch2_odata[4]/S R O [20]
ch2_odata[6]/S R O [22]
C S I0_R X/P IO _V IO [13]
C S I0_TX /P IO _V IO [15]
C S I0_C LK /P IO _V IO [17]
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
-
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
#7 I2C _S D A
I2C _SD A /P IO _V IO [19]
IO
56
P
56
#7 I2C _S C L
I2C _SC L/P IO _V IO [21]
IO
57
N
57
I
12V
12V
-
-
58
59
60
P
N
P
58
59
60
-
P ow er supply
-
S ignal nam e
D escription
U A R T0_R X /P IO _V IO [0]
U A R T0_TX/P IO _V IO [2]
V S YN C I_B [0]
S C LK 2I[0]
ch0_idata[1]/S R I[1]
ch0_idata[3]/S R I[3]
C A R 2 V IN C h0
ch0_idata[5]/S R I[5]
ch0_idata[7]/S R I[7]
ch0_idata[9]/S R I[9]
ch0_idata[11]/S R I[11]
ch0_idata[13]
ch0_idata[15]
U A R T1_R X /P IO _V IO [1]
U A R T1_TX/P IO _V IO [3]
V S YN C I_B [1]
S C LK 2I[1]
ch1_idata[1]/S R I[13]
ch1_idata[3]/S R I[15]
C A R 2 V IN ch1
ch1_idata[5]/S R I[17]
ch1_idata[7]/S R I[19]
ch1_idata[9]/S R I[21]
ch1_idata[11]/S R I[23]
ch1_idata[13]
ch1_idata[15]
U A R T2_R X /P IO _V IO [6]
U A R T2_TX/P IO _V IO [8]
V S YN C I_B [2]
S C LK 2I[2]
ch2_idata[1]/S R I[25]
ch2_idata[3]/S R I[27]
ch2_idata[5]/S R I[29]
C A R 2 V IN ch2
ch2_idata[7]/S R I[31]
ch2_idata[9]/S R I[33]
ch2_idata[11]/S R I[35]
ch2_idata[13]/S R I[37]
ch2_idata[15]/S R I[39]
U A R T3_R X /P IO _V IO [7]
U A R T3_TX/P IO _V IO [9]
V S YN C O 0_B
C A R 2 V O U T com m on
S C LK 2O 0
ch0_odata[1]/SR O [1]
ch0_odata[3]/SR O [3]
C A R 2 V O U T ch0
ch0_odata[5]/SR O [5]
ch0_odata[7]/SR O [7]
ch1_odata[1]/SR O [9]
ch1_odata[3]/SR O [11]
C A R 2 V O U T ch1
ch1_odata[5]/SR O [13]
ch1_odata[7]/SR O [15]
ch2_odata[1]/SR O [17]
ch2_odata[3]/SR O [19]
C A R 2 V O U T ch2
ch2_odata[5]/SR O [21]
ch2_odata[7]/SR O [23]
C SI1_R X /P IO _V IO [12]
C SI1_TX /P IO _V IO [14]
C SI1_C LK /P IO _V IO [16]
C am era reset
generalpurpose port
/P IO _V IO [18]
N TS C decoder reset
generalpurpose port
/P IO _V IO [20]
12V
P ow er supply
12V
12V
Preliminary User’s Manual U19880EE1V0UM00
20
IMAPCAR2 Video I/F Board
4.4.2
Supervisor connector (CN2/CN7)
Manufacturer:
C olum n
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
P in nam e
Model:
A1
A30 A31
QTH-060-05-L-D-A/QSH-060-01-L-D-A
A60
A31 A30
A1
A60
B1
B60
I/O
B30 B31
CN2
D escription
A [2]
A [4]
A [6]
A [8]
A [10]
A [12]
A [14]
A [16]
A [18]
A [20]
A [22]
A [24]
A [26]
A [28]
D [0]
D [2]
D [4]
D [6]
D [8]
D [10]
D [12]
D [14]
W R _B
C S 0_B
C S 1_B
C S 2_B
YO B I_B U S R EQ
SV _B U SR EQ
SV _B U SR ES ET
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
I
I
-
C P U bus :W rite signal
R eserve (P FG A connection)
C P U B us :chip select
R eserve (P FG A connection)
R eserve (P FG A connection)
R eserve (P FG A connection)
R eserve (P FG A connection)
30 YO B I_P O R T[3]
-
R eserve (P FG A connection)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
G LO A B A L_H R ES ET IO
P IO _V IO [1]
P IO _V IO [3]
P IO _V IO [5]
P IO _V IO [7]
P IO _V IO [9]
P IO _V IO [11]
P IO _V IO [13]
P IO _V IO [15]
P IO _V IO [17]
P IO _V IO [19]
P IO _V IO [21]
C A R 2_P O R T0[1]
C A R 2_P O R T0[3]
C A R 2_P O R T0[5]
C A R 2_P O R T0[7]
C A R 2_P O R T0[9]
C A R 2_P O R T1[1]
C A R 2_P O R T1[3]
C A R 2_P O R T1[5]
C A R 2_IN TP [1]
C A R 2_C SI_C LK
C A R 2_C SI_TX
C A R 2_C SI_C S
C A R 2_D C O N 10
C A R 2_R EG O N 25
G LO A B A L_S R ES ET I
58 YO B I_P O R T[2]
-
59 12V
60 -
-
SAMTEC
C P U B us :A ddress line
C P U B us :data lines
H ard reset
U nsed
Spares
（FP G A connections）
Spares
（FP G A connections）
Soft reset
Spars
（FP G A connections）
pow er supply
U nsed
B60
C olum n
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
B31 B30
CN7
P in nam e
I/O
A [1]
A [3]
A [5]
A [7]
A [9]
A [11]
A [13]
A [15]
A [17]
A [19]
A [21]
A [23]
A [25]
A [27]
D [1]
D [3]
D [5]
D [7]
D [9]
D [11]
D [13]
D [15]
R D _B
W A IT0_B
W A IT1_B
W A IT2_B
YO B I_B U S B U S Y
S V _B U SB U S Y
S V _B U SS TA T
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
I
O
I
IO
-
30 S V _B U R S T
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
G LO A B A L_P R ES ET
P IO _V IO [0]
P IO _V IO [2]
P IO _V IO [4]
P IO _V IO [6]
P IO _V IO [8]
P IO _V IO [10]
P IO _V IO [12]
P IO _V IO [14]
P IO _V IO [16]
P IO _V IO [18]
P IO _V IO [20]
C A R 2_P O R T0[0]
C A R 2_P O R T0[2]
C A R 2_P O R T0[4]
C A R 2_P O R T0[6]
C A R 2_P O R T0[8]
C A R 2_P O R T1[0]
C A R 2_P O R T1[2]
C A R 2_P O R T1[4]
C A R 2_IN TP [0]
C A R 2_IN TP [2]
C A R 2_C SI_R X
C A R 2_ER R O R O U T
C A R 2_H D R STB
C A R 2_D C O N 19
C A R 2_FA ILD C
58 YO B I_P O R T[1]
-
59 12V
60 12V
-
Preliminary User’s Manual U19880EE1V0UM00
B1
D escription
C P U B us :A ddress line
C P U B us :data lines
C P U bus :R ead signal
R eserve (P FG A connection)
C P U bus :W ait signal
R eserve (P FG A connection)
R eserve (P FG A connection)
R eserve (P FG A connection)
R eserve (P FG A connection)
N .C .
Power reset
U nsed
S pares
（
FP G A connections）
S pares
（
FP G A connections）
pow er supply
21
IMAPCAR2 Video I/F Board
4.4.3
Video I/O connector 2 (CN3/CN9)
Manufacturer:
SAMTEC
Model:
QTH-060-05-L-D-A/QSH-060-01-L-D-A
A1
B1
A30 A31
B30 B31
CN3
A60
A60
A31 A30
A1
B60
B60
B31 B30
CN9
B1
Meaning of the IO field value is seen from 1394 board side.
Features
Spare
IM A P C A R 2 im age IF：C h0
Spare
Spare
Spare
Spare
EC U ,SJ2 control
IM A P C A R 2 Im age input IF:
C h1
A ssign the C P U signals of
EC U /SV
(reserved)
R eserved
R eserved
Spare
Spare
Spare
IM A P C A R 2 im age IF：C h2
Spare
Spare
Spare
Spare
S ignalnam es
Spare
FR A M E_V A ILD _P i
H SYN C _P i
P C LK_P i
D 0_P i
D 2_P i
D 4_P i
D 6_P i
D 8_P i
Spare
Spare
Spare
Spare
C A M _FR M _V A LID
N B D SYN C #
N B D C LK
N B D _D i0
N B D _D i2
N B D _D o0
N B D _D o2
EC U _D 8
EC U _D 10
Spare
Spare
Spare
FR A M E_V A LID _N i
H SYN C _N i
P C LK_N i
D 0_N i
D 2_N i
D 4_N i
D 6_N i
D 8_N i
Spare
Spare
Spare
Spare
FR A M E_V A LID _P o
IM A P C A R 2 Im age output IF sync
signal
H SYN C _P o
C om m on for C h0,1,2
IO
IO
I
I
I
I
I
I
I
I
IO
IO
IO
IO
I
O
O
I
I
O
O
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
IO
IO
IO
IO
O
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
IO
IO
IO
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
I
O
I
I
O
O
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
S ignalN am es
U A R T_R X_P i
U A R T_TX_P i
V SYN C _P i
P C LK2_P i
D 1_P i
D 3_P i
D 5_P i
D 7_P i
D 9_P i
Spare
Spare
Spare
Spare
Spare
N B D EV IN T#
N B D D O E#
N B D _D i1
N B D _D i3
N B D _D o1
N B D _D o3
EC U _D 9
EC U _D 11
Spare
Spare
U A R T_R X_N i
U A R T_TX_N i
V SYN C _N i
P C LK2_N i
D 1_N i
D 3_N i
D 5_N i
D 7_N i
D 9_N i
Spare
Spare
Spare
Spare
Spare
O
39
N
39
O
V SYN C _P o
P C LK_P o
O
40
P
40
O
P C LK2_P o
IM A P C A R 2 Im age output IF
sync signal
C om m on for C h0,1,2
D 0_P o
D 2_P o
D 4_P o
D 6_P o
D 8_P o
FR A M E_V A LID _N o
O
O
O
O
O
O
41
42
43
44
45
46
N
P
N
P
N
P
41
42
43
44
45
46
O
O
O
O
O
O
D 1_P o
D 3_P o
D 5_P o
D 7_P o
D 9_P o
Spare
H SYN C _N o
O
47
N
47
O
V SYN C _N o
P C LK_N o
O
48
P
48
O
P C LK2_N o
IM A P C A R 2 IF:C h0
D 0_N o
D 2_N o
D 4_N o
D 6_N o
D 8_N o
O
O
O
O
O
49
50
51
52
53
N
P
N
P
N
49
50
51
52
53
O
O
O
O
O
D 1_N o
D 3_N o
D 5_N o
D 7_N o
D 9_N o
Spare
Spare
IO
54
P
54
O
R eserved
（
N TSC _R ESET_B )
1394board R ESET output
1394_R ESET_B
O
55
N
55
O
R eserved
（
C A M ER A _R ESET_B ）
R eserved
I2C _SD A
IO
56
P
56
O
O E_P o
R eserved
I2C _SC L
IO
57
N
57
O
O E_N o
IM A P C A R 2 Im age output IF:
C h2
Preliminary User’s Manual U19880EE1V0UM00
Features
R eserved
R eserved
IM A P C A R 2 im age IF：C h0
Spare
Spare
Spare
Spare
Spare
IM A P C A R 2 Im age input IF:
C h1
A ssign the C P U signals of
EC U /SV
(reserved)
R eserved
R eserved
Spare
Spare
R eserved
R eserved
IM A P C A R 2im age IF：C h2
Spare
Spare
Spare
Spare
Spare
IM A P C A R 2 Im age output IF
sync signal
C om m on for C h0,1,2
IM A P C A R 2 Im age output IF:
C h2
Spare
IM A P C A R 2 Im age output IF sync
signal
C om m on for C h0,1,2
IM A P C A R 2 im ahe IF:C h0
R eserved
(R eset signalfor N TSC
encoder/decoder IC .
dedicated signalto V ideo IF
R eserved
(R eset signalfor parallel
cam era.dedicated signalto
V ideo IF board)
C ontrolparalleloutput
‘
0’:1394 board output
‘
1’:V ideo IF board output
C ontrolN TSC output
‘
0’:1394 board output
‘
1’:V ideo IF board output
22
IMAPCAR2 Video I/F Board
4.4.4
Plug-in phone jack for CH0 differential motion (J1)
Manufacturer:
Hirose
Model:
TM24RSG-5A-88
Direction of the signal
Pin
Number
Signal Name
1
CN0_RX+
Input
LVDS differential motion reception line + side
2
CN0_RX-
Input
LVDS differential motion reception line - side
3
UART0A
Input/Output
4
CN0_TX+
Input
LVDS differential motion transmission line + side
5
CN0_TX-
Input
LVDS differential motion transmission line + side
6
UART0B
Input/output
7
DC12V
-
Power supply line (DC12C°
8
GND
-
GND
4.4.5
Description
(from FPGA point of view)
RS485 differential signal + side
RS485 differential signal - side
Plug-in phone jack for CH1 differential motion (J2)
Manufacturer:
Hirose
Model:
TM24RSG-5A-88
Direction of the signal
Pin
Number
Signal Name
1
CN1_RX+
Input
LVDS differential motion reception line + side
2
CN1_RX-
Input
LVDS differential motion reception line - side
3
UART1A
Input/Output
4
CN1_TX+
Input
LVDS differential motion transmission line + side
5
CN1_TX-
Input
LVDS differential motion transmission line + side
6
UART1B
Input/output
7
DC12V
-
Power supply line (DC12C°
8
GND
-
GND
Description
(from FPGA point of view)
RS485 differential signal + side
RS485 differential signal - side
Preliminary User’s Manual U19880EE1V0UM00
23
IMAPCAR2 Video I/F Board
4.4.6
Plug-in phone jack for CH2 differential motion (J3)
Manufacturer:
Hirose
Model:
TM24RSG-5A-88
Direction of the signal
Pin
Number
Signal Name
1
CN2_RX0+
Input
LVDS differential motion reception line + side
2
CN2_RX0-
Input
LVDS differential motion reception line - side
3
UART2A
Input/Output
4
CN2_RX1+
Input
LVDS differential motion transmission line + side
5
CN2_RX1-
Input
LVDS differential motion transmission line + side
6
UART2B
Input/output
7
DC12V
-
Power supply line (DC12C)
8
GND
-
GND
4.4.7
Description
(from FPGA point of view)
RS485 differential signal + side
RS485 differential signal - side
Plug-in phone jack for CH3 differential motion (J4)
Manufacturer:
Hirose
Model:
TM24RSG-5A-88
Direction of the signal
Pin
Number
Signal Name
1
CN3_TX0+
Input
LVDS differential motion reception line + side
2
CN3_TX0-
Input
LVDS differential motion reception line - side
3
UART3A
Input/Output
4
CN3_TX1+
Input
LVDS differential motion transmission line + side
5
CN3_TX1-
Input
LVDS differential motion transmission line + side
6
UART3B
Input/output
7
DC12V
-
Power supply line (DC12C°
8
GND
-
GND
Description
(from FPGA point of view)
RS485 differential signal + side
RS485 differential signal - side
Preliminary User’s Manual U19880EE1V0UM00
24
IMAPCAR2 Video I/F Board
4.4.8
4.4.9
NTSC input RCA Jack (J5)
Manufacturer:
CUI INC
Model:
RCJ-013
RCA Jack:
White
NTSC output RCA Jack (J6)
Manufacturer:
CUI INC
Model:
RCJ-011
RCA Jack:
Black
4.4.10 JTAG connector
Manufacturer:
MOLEX
Model:
87331-142
13
1
14
2
Pin
Number
Signal Name
1
GND
2
VCC_2.5V
3
GND
Ground
4
TMS
Test Mode Select / 2.5V pull-up
5
GND
Ground
6
TCK
Test Clock / 2.5V pull-up
7
GND
Ground
8
TDO
Test Data Output / 2.5V pull-up
9
GND
Ground
10
TDI
11
GND
Ground
12
N.C.
-
13
GND
Ground
13
N.C.
-
Description
Ground
Power supply (2.5V)
Test Data Input / 2.5V pull-up
Preliminary User’s Manual U19880EE1V0UM00
25
IMAPCAR2 Video I/F Board
4.4.11 Power supply terminal stand (CN8)
Manufacturer:
Model:
Sato
ML-950-2
Pin
Number
Signal Name
1
+12V
Power supply (+12V)
2
+12V
Power supply (+12V)
3
GND
Ground
4
GND
Ground
Description
Preliminary User’s Manual U19880EE1V0UM00
26
IMAPCAR2 Video I/F Board
5
Hardware component
5.1 FPGA
Supplier: XILINX
Model XC3S2000-4FGG676C 676pinBGA
5.1.1
Image System Block
(1)Overview
Image System Block is based on Thine IF and NTSC decoder/encoder IF.
Six types of the configuration for the image can be selected by setting the DIP
switch (SW9.1-3).
Mode
Mode 0
Mode 1
3
OFF
OFF
SW9
2
1
OFF OFF
OFF ON
Mode 2
OFF
ON
OFF
Mode 3
OFF
ON
ON
Mode 4
ON
OFF
OFF
Mode 5
ON
OFF
ON
Description
Input 3ch images from the progressive camera to IMAPCAR2
Input 2ch images from the progressive camera (2ch color images) to
IMAPCAR2
Input 2ch images from the progressive camera and the NTSC camera image to
IMAPCAR2
Output the NTSC camera image from the NTSC encoder
Input 1ch images from the progressive camera and the NTSC camera image to
IMAPCAR2.
Output the NTSC camera image from the NTSC encoder.
Output back the NTSC image for cascading the video interface boards (for
transmission)
For cascading the video interface boards (for reception)
Preliminary User’s Manual U19880EE1V0UM00
27
IMAPCAR2 Video I/F Board
Video2 c onnector
(C N3/C N9)
V ideo IF B oard
Image F P G A
T R x0
L VDS ‐in
L VDC ‐out L VD S
RX
Video C onnector
(C N1/C N6)
IMAP C AR 2 board
Us er F P G A
16bit
12bit
16bit
12bit
12bit
S C L K i0
S C L K 2i0
VS Y NC i2
H S Y NC i2
S R i(0:11)
CH0
in
S C L K o1
VS Y NC o1
H S Y NC o1
S R o(12:23)
CH1
out
S C L K i2
S C L K 2i2
VS Y NC i2
H S Y NC i2
S R i(24:39)
CH2
in
S C L K o0
S C L K 0i0
VS Y NC 00
H S Y NC 00
S R 0(0:24)
CH0
Out
L VD S
TX
L VD S
RX
T R x1
L VDS ‐in
L VDC ‐out 12bit
L VD S
TX
R x2
L VDS ‐in
L VDS ‐in L VD S
RX
16bit
16bit
16bit
16bit
24bit
24bit
L VD S
RX
NT S C ‐in T x2
L VDS ‐out
L VDS ‐out
NT S C
D ec
Y /G
C /R
B
L VDS
TX
8bit
L VD S
TX
NT S C ‐out NT S C
E nc
Y /G
C /R
B
D IP ‐S W
S V c onnector (C N2/C N7)
Internal composition of FPGA chart mode 0 (image system)
V ideo2 c onnector
(C N 3/C N9)
Video IF B oard
Image F P G A
T R x0
L VD S ‐in
L VD C ‐out 16bit
L VD S
RX
V ideo C onnector
(C N1/C N 6)
IMAP C AR 2 board
Us er F P G A
8bit
8bit
12bit
8bit
8bit
12bit
S C L K i0
S C L K 2i0
VS Y NC i2
HS Y NC i2
S R i(0:11)
CH0
in
S C L K o1
VS Y NC o1
HS Y NC o1
S R o(12:23)
CH1
out
S C L K i2
S C L K 2i2
VS Y NC i2
HS Y NC i2
S R i(24:39)
CH2
in
S C L K o0
S C L K 0i0
VS Y NC 00
HS Y NC 00
S R 0(0:24)
CH0
Out
L VD S
TX
T R x1
L VD S ‐in
L VD C ‐out L VD S
RX
L VD S
TX
R x2
L VD S ‐in
L VD S ‐in 16bit
16bit
L VD S
RX
L VD S
RX
NT S C ‐in T x2
L VD S ‐out
L VD S ‐out
NT S C
D ec
Y /G
C /R
B
L VDS
TX
16bit
NT S C
E nc
24bit
8bit
L VD S
TX
NT S C ‐out 16bit
Y /G
C /R
B
24bit
D IP ‐S W
S V c onnector (C N 2/C N7)
Internal composition of FPGA chart mode 1 (image system)
Preliminary User’s Manual U19880EE1V0UM00
28
IMAPCAR2 Video I/F Board
V ideo IF B oard
Image F P G A
T R x0
L VD S ‐in
L VDC ‐out 16bit
L VD S
RX
Video2 c onnector
(C N3/C N 9)
Video C onnector
(C N1/C N 6)
IMAP C AR 2 board
Us er F P G A
8bit
12bit
8bit
12bit
16bit
16bit
S C L K i0
S C L K 2i0
VS Y NC i2
HS Y NC i2
S R i(0:11)
CH0
in
S C L K o1
VS Y NC o1
HS Y NC o1
S R o(12:23)
CH1
out
S C L K i2
S C L K 2i2
VS Y NC i2
HS Y NC i2
S R i(24:39)
CH2
in
S C L K o0
S C L K 0i0
VS Y NC 00
HS Y NC 00
S R 0(0:24)
CH0
Out
L VD S
TX
T R x1
L VD S ‐in
L VD C ‐out 16bit
L VD S
RX
L VD S
TX
R x2
L VD S ‐in
L VD S ‐in L VD S
RX
L VD S
RX
NT S C ‐in NT S C
D ec
T x2
L VD S ‐out
L VD S ‐out
LVDS
TX
Y /G
C /R
B
16bit
NT S C
E nc
24bit
8bit
L VD S
TX
NT S C ‐out 16bit
24bit
Y /G
C /R
B
D IP ‐S W
S V c onnector (C N 2/C N7)
III
Internal composition of FPGA chart mode 2 (image system)
V ideo IF B oard
Image F P G A
T R x0
L VD S ‐in
L VDC ‐out L VD S
RX
Video2 c onnector
(C N3/C N 9)
Video C onnector
(C N1/C N 6)
IMAP C AR 2 board
Us er F P G A
12bit
12bit
12bit
12bit
S C L K i0
S C L K 2i0
VS Y NC i2
HS Y NC i2
S R i(0:11)
CH0
in
S C L K o1
VS Y NC o1
HS Y NC o1
S R o(12:23)
CH1
out
S C L K i2
S C L K 2i2
VS Y NC i2
HS Y NC i2
S R i(24:39)
CH2
in
S C L K o0
S C L K 0i0
VS Y NC 00
HS Y NC 00
S R 0(0:24)
CH0
Out
L VD S
TX
T R x1
L VD S ‐in
L VD C ‐out L VD S
RX
L VD S
TX
R x2
L VD S ‐in
L VD S ‐in 16bit
16bit
L VD S
RX
L VD S
RX
8bit
NT S C ‐in NT S C
D ec
T x2
L VD S ‐out
L VD S ‐out
LVDS
TX
Y /G
C /R
B
16bit
NT S C
E nc
24bit
8bit
L VD S
TX
NT S C ‐out 8bit
Y /G
C /R
B
24bit
D IP ‐S W
S V c onnector (C N 2/C N7)
Internal composition of FPGA chart mode 3 (image system)
Preliminary User’s Manual U19880EE1V0UM00
29
IMAPCAR2 Video I/F Board
V ideo2 c onnector
(C N3/C N 9)
V ideo IF B oard
Image F P G A
T R x0
L VD S ‐in
L VD C ‐out 16bit
L VD S
RX
V ideo C onnector
(C N 1/C N 6)
IMAP C AR 2 board
Us er F P G A
12bit
12bit
12bit
12bit
S C L K i0
S C L K 2i0
VS Y NC i2
HS Y NC i2
S R i(0:11)
CH0
in
S C L K o1
VS Y NC o1
HS Y NC o1
S R o(12:23)
CH1
out
S C L K i2
S C L K 2i2
VS Y NC i2
HS Y NC i2
S R i(24:39)
CH2
in
S C L K o0
S C L K 0i0
VS Y NC 00
HS Y NC 00
S R 0(0:24)
CH0
Out
L VD S
TX
16bit
L VD S
RX
T R x1
L VD S ‐in
L VD C ‐out L VD S
TX
16bit
16bit
L VD S
RX
R x2
L VD S ‐in
L VD S ‐in L VD S
RX
8bit
NT S C
D ec
NT S C ‐in T x2
L VD S ‐out
L VD S ‐out
NT S C ‐out J
4
Y /G
C /R
B
8bit
L VD S
TX
16bit
L VD S
TX
8bit
NT S C
E nc
24bit
16bit
Y /G
C /R
B
D IP ‐S W
S V c onnector (C N2/C N 7)
Internal composition of FPGA chart mode 4 (image system)
V ideo2 c onnector
(C N3/C N 9)
V ideo IF B oard
Image F P G A
T R x0
L VD S ‐in
L VD C ‐out L VD S
RX
V ideo C onnector
(C N 1/C N 6)
IMAP C AR 2 board
Us er F P G A
12bit
12bit
12bit
12bit
S C L K i0
S C L K 2i0
VS Y NC i2
HS Y NC i2
S R i(0:11)
CH0
in
S C L K o1
VS Y NC o1
HS Y NC o1
S R o(12:23)
CH1
out
S C L K i2
S C L K 2i2
VS Y NC i2
HS Y NC i2
S R i(24:39)
CH2
in
S C L K o0
S C L K 0i0
VS Y NC 00
HS Y NC 00
S R 0(0:24)
CH0
Out
L VD S
TX
T R x1
L VD S ‐in
L VD C ‐out L VD S
RX
L VD S
TX
R x2
L VD S ‐in
L VD S ‐in L VD S
RX
16bit
L VD S
RX
NT S C ‐in T x2
L VD S ‐out
L VD S ‐out
NT S C
D ec
Y /G
C /R
B
L VD S
TX
NT S C
E nc
16bit
16bit
24bit
8bit
L VD S
TX
NT S C ‐out 16bit
16bit
16bit
Y /G
C /R
B
24bit
D IP ‐S W
S V c onnector (C N2/C N 7)
Internal composition of FPGA chart mode 5 (image system)
Preliminary User’s Manual U19880EE1V0UM00
30
IMAPCAR2 Video I/F Board
5.1.2
Communication system block
(1) Overview
•
Another equipment connected with the plug-in phone jack can be
controlled by the control and the I2C⇔RS485 conversion function of
NTSC encoder/decoder device by I2C.
(However, the RS485⇔I2C conversion function is needed on the
connected equipment side.)
•
It is possible to reset camera IF board by the port control by Host (SV
microcomputer and 1394 boards). This reset is done via the RS485
communication.
Communication route outline is shown below.
V ID E O 2
connectors
V ideo B oard IF
V ID EO
connector
Im age
FP G A
U ser
FP G A
I2C to I2C/RS485
Bridge
C am era board IF
N TS C
D ecoders
I2C
Master
100kbps
I2C
slave
I2C
I2C Master
100kbps
I2C
slave
I2C
C P LD
N TSC
Encoders
P arallel
C am eras
I2C
I2C
M aster
400kbps
I2C to I2C
Bridge
I2C
I2C
M aster
400kbps
I2C
Slave
400kbps
I2C
SV
m icrocotroller
R S 485
R S 485
R J45
connectors
R J45
connectors
R S485
I2C
slave
R ESET
R eset from IM A P C A R 2 board
Internal composition of FPGA chart (I2C/ RS485 communication system)
Preliminary User’s Manual U19880EE1V0UM00
31
IMAPCAR2 Video I/F Board
5.1.3
Reset block
The reset signal is generated in FPGA as follows.
•
HRESET is an equivalent signal to DX_DONE.
VIDEO2
Connector
Video IF Board
Image
FPGA
Communication
System
VIDEO
Connector
User
FPGA
HRESET
SRESET
HRESET
SRESET
Communication
System
Other
Other
Image system
NTSC
Decoder
ND_RESET
NTSC
Encoders
NE_RESET
1394 reset
Image system
NTSC Reset
Preliminary User’s Manual U19880EE1V0UM00
SV
Microcontroller
32
IMAPCAR2 Video I/F Board
5.1.4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
A 24
A 25
A 26
B1
B2
B3
B4
B5
B6
B7
B8
B9
B 10
B 11
B 12
B 13
B 14
B 15
B 16
B 17
B 18
B 19
B 20
B 21
B 22
B 23
B 24
B 25
B 26
Pin assignment
The following tables describes the user FPGA pin assign
GND
2.5V
N E_SD A
N E_SC L
N D _C SYN C _SC A LR
N D _V H V A L_SC A LW
V ID EO 2_B 13
V ID EO 2_B 11
2.5V
V ID EO 2_B 1
N D _S TA TU S 1
N E_R ESET_L
S YS _C LK _P
N E_V S YN C _L
V ID EO 2_A 38
P _TEST_LED 6
P _TEST_SW 16
2.5V
P _TES T_S W 8
P _TES T_S W 2
V ID EO 2_A 55
R ES ER V ED _B 0
R ES ER V ED _B 1
TM S
2.5V
GND
2.5V
GND
N E_H SYN C _L
N E_B LA N K_L
N E_YD 9
N E_YD 8
N E_YD 7
N E_YD 6
N E_YD 5
N E_YD 4
N E_YD 3
N E_YD 2
N E_YD 1
N E_YD 0
V ID EO 2_A 37
P _TES T_LED 7
P _TES T_LED 1
P _TEST_SW 10
P _TES T_S W 9
P _TES T_S W 3
C A R 2_C SI_R X
R eserved
R eserved
TC K
GND
2.5V
C1
C2
C3
C4
C5
C6
C7
C8
C9
C 10
C 11
C 12
C 13
C 14
C 15
C 16
C 17
C 18
C 19
C 20
C 21
C 22
C 23
C 24
C 25
C 26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D 10
D 11
D 12
D 13
D 14
D 15
D 16
D 17
D 18
D 19
D 20
D 21
D 22
D 23
D 24
D 25
D 26
TD I
H S W A P _EN
GND
N E_C D 9
N E_C D 8
N E_C D 7
3.3V
N E_C D 6
N E_C D 5
N E_C D 4
3.3V
N E_C D 3
N E_C D 2
N E_C D 1
V ID EO 2_A 57
3.3V
R eserved
P _TES T_SW 11
P _TES T_SW 6
3.3V
R eserved
R eserved
R eserved
GND
R ESER V ED _C 0
V ID EO 2_A 36
N E_C D 0
N E_B D 9
P R O G _B
GND
N E_B D 8
N E_B D 7
N E_B D 6
N E_B D 5
N E_B D 4
N E_B D 3
N E_B D 2
GND
N E_B D 1
N E_B D 0
GND
R ESER V ED _B 2
P _TES T_SW 14
V ID EO 2_A 56
P _TES T_SW 7
C A R 2_C S I_TX
C A R 2_C SI_C LK
R eserved
GND
TD O
R ESER V ED _C 3
V ID EO 2_A 35
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
N E_STA N D B Y
N D _R ES ET_L
N D _SC L
N D _SD A
N D _C 9
N D _C 8
N D _C 7
N D _C 6
N D _C 5
N D _C 4
N D _C 3
N D _C 2
N D _C 1
N D _C 0
N E_O LR
P _TES T_LED 4
P _TES T_SW 15
R ESER V ED _B 3
P _TES T_SW 4
P _TES T_SW 1
R eserved
R eserved
R ESER V ED _C 1
R ESER V ED _C 2
R ESER V ED _C 4
V ID EO 2_A 34
N D _B 5
N D _B 4
N D _B 3
N D _B 2
N D _Y0
N D _Y1
N D _Y2
N D _Y3
N D _Y4
N D _Y5
N D _Y6
N D _Y7
N D _Y8
N D _Y9
N E_O LG
P _TES T_LED 5
P _TES T_SW 12
V ID EO 2_A 54
P _TES T_SW 5
R ESER V ED _B 4
R eserved
N .C .
R eserved
R eserved
R eserved
V ID EO 2_A 24
G1
G2
G3
G4
G5
G6
G7
G8
G9
G 10
G 11
G 12
G 13
G 14
G 15
G 16
G 17
G 18
G 19
G 20
G 21
G 22
G 23
G 24
G 25
G 26
H1
H2
H3
H4
H5
H6
H7
H8
H9
H 10
H 11
H 12
H 13
H 14
H 15
H 16
H 17
H 18
H 19
H 20
H 21
H 22
H 23
H 24
H 25
H 26
Preliminary User’s Manual U19880EE1V0UM00
N D _H V A LID
N D _V V A LID
3.3V
N D _V SYN C _L
N D _H SYN C _L
N D _O D D _EV EN B
N D _C LK X O
V ID EO 2_B 12
V ID EO 2_B 10
V ID EO 2_B 23
N D _C LKX2O
LV T0_SYN C 0
N E_C LK
G R O B A L_S R ES ET
P _TES T_LED 8
P _TES T_LED 2
P _TES T_S W 13
V ID EO 2_A 46
R eserved
R eserved
R eserved
R eserved
R eserved
3.3V
R eserved
V ID EO 2_A 23
LV T2_SYN C 1
LV T2_SYN C 2
LV T1_SYN C 2
LV T2_SYN C 0
LV T1_SYN C 1
LV T0_SYN C 1
LV T0_SYN C 2
1.2V
3.3V
3.3V
V ID EO 2_B 34
V ID EO 2_B 24
N D _C LK
N E_O LB
N E_O LC
P _TES T_LED 3
3.3V
3.3V
1.2V
R eserved
R eserved
R eserved
R eserved
R eserved
R eserved
V ID EO 2_A 14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
K1
K2
K3
K4
K5
K6
K7
K8
K9
K 10
K11
K 12
K13
K14
K 15
K 16
K 17
K 18
K 19
K20
K21
K22
K23
K24
K25
K 26
2.5V
LV R 1_LO C K
LV R 0_LO C K
LV R 3_LO C K
LV R 2_LO C K
LV T1_SYN C 0
LV T3_S YN C 1
3.3V
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
1.2V
1.2V
3.3V
R eserved
R eserved
R eserved
R eserved
R eserved
R eserved
2.5V
LV R 0_SYN C 0
LV R 0_SYN C 1
LV R 0_SYN C 2
LV R 1_SYN C 0
LV R 1_SYN C 1
LV T3_SYN C 2
LV T3_SYN C 0
3.3V
1.2V
1.2V
GND
GND
3.3V
3.3V
GND
GND
1.2V
1.2V
3.3V
R eserved
R eserved
R eserved
R eserved
R eserved
R eserved
V ID EO 2_A 13
33
IMAPCAR2 Video I/F Board
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
M2
M3
M4
M5
M6
M7
M8
M9
M 10
M 11
M 12
M 13
M 14
M 15
M 16
M 17
M 18
M 19
M 20
M 21
M 22
M 23
M 24
M 25
M 26
LV R 1_S YN C 2
LV R 2_S YN C 0
3.3V
LV R 2_S YN C 1
LV R 2_S YN C 2
LV R 3_S YN C 0
LV R 3_S YN C 1
LV R 3_S YN C 2
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
R eserved
R eserved
R eserved
V ID EO 2_A 12
R eserved
3.3V
R eserved
V ID EO 2_A 11
LV T0_D 5
LV T0_D 4
LV T0_D 3
G ND
LV T0_D 2
LV T0_D 1
LV T0_D 0
LV T0_D E
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
R eserved
R eserved
R eserved
V ID EO 2_A 10
G ND
R eserved
R eserved
V ID EO 2_B 55
N1
N2
N3
N4
N5
N6
N7
N8
N9
N 10
N 11
N 12
N 13
N 14
N 15
N 16
N 17
N 18
N 19
N 20
N 21
N 22
N 23
N 24
N 25
N 26
P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15
P 16
P 17
P 18
P 19
P 20
P 21
P 22
P 23
P 24
P 25
P 26
LV T0_D 13
LV T0_D 12
LV T0_D 11
LV T0_D 10
LV T0_D 9
LV T0_D 8
LV T0_D 7
LV T0_D 6
3.3V
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
3.3V
V ID EO 2_B 54
V ID EO 2_B 37
R eserved
V ID EO 2_B 36
R eserved
R eserved
R eserved
V ID EO 2_B 35
LV R 0_D 16
LV R 0_D 17
LV R 0_C LKO U T
LV T0_C LKIN
LV T0_D 17
LV T0_D 16
LV T0_D 15
LV T0_D 14
3.3V
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
3.3V
V ID EO 2_A 1
V ID EO 2_A 2
V ID EO 2_A 3
V ID EO 2_A 4
V ID EO 2_A 5
V ID EO 2_A 6
V ID EO 2_A 7
V ID EO 2_A 8
R1
R2
R3
R4
R5
R6
R7
R8
R9
R 10
R 11
R 12
R 13
R 14
R 15
R 16
R 17
R 18
R 19
R 20
R 21
R 22
R 23
R 24
R 25
R 26
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
LV R 0_D 9
LV R 0_D 10
LV R 0_D 11
G ND
LV R 0_D 12
LV R 0_D 13
LV R 0_D 14
LV R 0_D 15
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
V ID EO 2_A 9
V ID EO 2_B 2
V ID EO 2_B 3
V ID EO 2_B 4
G ND
V ID EO 2_B 5
V ID EO 2_B 6
V ID EO 2_B 7
LV R 0_D 2
LV R 0_D 3
3.3V
LV R 0_D 4
LV R 0_D 5
LV R 0_D 6
LV R 0_D 7
LV R 0_D 8
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
V ID EO 2_B 8
V ID EO 2_B 9
V ID EO 2_A 15
V ID EO 2_A 16
V ID EO 2_A 17
3.3V
V ID EO 2_A 18
V ID EO 2_A 19
Preliminary User’s Manual U19880EE1V0UM00
U1
U2
U3
U4
U5
U6
U7
U8
U9
U 10
U 11
U 12
U 13
U 14
U 15
U 16
U 17
U 18
U 19
U 20
U 21
U 22
U 23
U 24
U 25
U 26
V1
V2
V3
V4
V5
V6
V7
V8
V9
V 10
V 11
V 12
V 13
V 14
V 15
V 16
V 17
V 18
V 19
V 20
V 21
V 22
V 23
V 24
V 25
V 26
LV T1_D 2
LV T1_D 1
LV T1_D 0
LV T1_D E
LV R 0_D E
LV R 0_D 0
LV R 0_D 1
3.3V
1.2V
1.2V
GND
GND
3.3V
3.3V
GND
GND
1.2V
1.2V
3.3V
V ID EO 2_A 20
V ID EO 2_A 21
V ID EO 2_A 22
V ID EO 2_B 14
V ID EO 2_B 15
V ID EO 2_B 16
V ID EO 2_B 17
2.5V
LV T1_D 8
LV T1_D 7
LV T1_D 6
LV T1_D 5
LV T1_D 4
LV T1_D 3
3.3V
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
1.2V
1.2V
3.3V
V ID EO 2_B 18
V ID EO 2_B 19
V ID EO 2_B 20
V ID EO 2_B 21
V ID EO 2_B 22
V ID EO 2_A 25
2.5V
34
IMAPCAR2 Video I/F Board
W1
W2
W3
W4
W5
W6
W7
W8
W9
W 10
W 11
W 12
W 13
W 14
W 15
W 16
W 17
W 18
W 19
W 20
W 21
W 22
W 23
W 24
W 25
W 26
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
LV T1_D 15
LV T1_D 14
LV T1_D 13
LV T1_D 12
LV T1_D 11
LV T1_D 10
LV T1_D 9
1.2V
3.3V
3.3V
LV R 2_D 4
LV T3_D 0
LV T3_D 7
LV T3_D 15
LV R 3_D 16
LV R 3_D 10
3.3V
3.3V
1.2V
V ID EO 2_A 26
V ID EO 2_A 27
V ID EO 2_A 28
V ID EO 2_A 29
V ID EO 2_A 30
V ID EO 2_A 31
V ID EO 2_A 32
LV R 1_D 16
LV R 1_D 17
3.3V
LV R 1_C LKO U T
LV T1_C LK IN
LV T1_D 17
LV T1_D 16
LV T2_D 13
LV R 2_D 17
LV R 2_D 11
LV R 2_D 3
LV T3_D 1
LV T3_D 8
LV T3_D 16
D IN /D 0/
LV R 3_D 9
LV R 3_D 3
U A R T1_D I
U A R T0_D I
V ID EO 2_A 33
V ID EO 2_B 25
V ID EO 2_B 26
V ID EO 2_B 27
3.3V
V ID EO 2_B 28
V ID EO 2_B 29
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
A A 10
A A 11
A A 12
A A 13
A A 14
A A 15
A A 16
A A 17
A A 18
A A 19
A A 20
A A 21
A A 22
A A 23
A A 24
A A 25
A A 26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
A B 10
A B 11
A B 12
A B 13
A B 14
A B 15
A B 16
A B 17
A B 18
A B 19
A B 20
A B 21
A B 22
A B 23
A B 24
A B 25
A B 26
LV R 1_D 12
LV R 1_D 13
LV R 1_D 14
LV R 1_D 15
N D _STA TU S2
LV T2_D 2
LV T2_D 8
LV T2_D 14
LV R 2_D 16
LV R 2_D 10
LV R 2_D 2
LV T3_D 2
LV T3_D 9
LV T3_D 17
LV R 3_D 15
LV R 3_D 8
LV R 3_D 2
U A R T1_EN
U A R T0_EN
V ID EO 2_B 30
V ID EO 2_B 31
V ID EO 2_B 32
V ID EO 2_B 33
V ID EO 2_A 39
V ID EO 2_A 40
V ID EO 2_A 41
LV R 1_D 7
LV R 1_D 8
LV R 1_D 9
LV R 1_D 10
LV R 1_D 11
LV T2_D 3
LV T2_D 9
LV T2_D 15
LV R 2_D 15
LV R 2_D 9
LV R 2_D 1
LV T3_D 3
LV T3_D 10
LV T3_C LKIN
LV R 3_D 14
LV R 3_D 7
LV R 3_D 1
U A R T1_R O
U A R T0_R O
V ID EO 2_A 42
V ID EO 2_A 43
V ID EO 2_A 44
V ID EO 2_A 45
V ID EO 2_B 38
V ID EO 2_B 39
V ID EO 2_B 40
AC 1
AC 2
AC3
AC 4
AC 5
AC 6
AC7
AC 8
AC 9
A C 10
A C 11
A C 12
A C 13
A C 14
A C 15
A C 16
A C 17
A C 18
A C 19
A C 20
A C 21
A C 22
A C 23
A C 24
A C 25
A C 26
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
A D 10
A D 11
A D 12
A D 13
A D 14
A D 15
A D 16
A D 17
A D 18
A D 19
A D 20
A D 21
A D 22
A D 23
A D 24
A D 25
A D 26
LV R 1_D 4
LV R 1_D 5
M1
G ND
LV R 1_D 6
LV T2_D 4
LV T2_D 10
LV T2_D 16
LV R 2_D 14
LV R 2_D 8
LV R 2_D 0
G ND
LV T3_D 11
IN T_B /
G ND
LV R 3_D 6
LV R 3_D 0
U A R T2_EN
U A R T2_D I
V ID EO 2_B 41
V ID EO 2_B 42
V ID EO 2_B 43
G ND
DO NE
V ID EO 2_B 44
V ID EO 2_B 45
LV R 1_D 1
LV R 1_D 2
G ND
LV R 1_D 3
LV T2_D E
LV T2_D 5
3.3V
LV T2_D 17
LV R 2_D 13
LV R 2_D 7
3.3V
LV T3_D 4
LV T3_D 12
D X_D O N E
LV R 3_D 13
3.3V
LV R 3_D E
U A R T2_R O
V ID EO 2_B 46
3.3V
V ID EO 2_B 47
V ID EO 2_B 48
V ID EO 2_B 49
G ND
V ID EO 2_B 50
C C LK
Preliminary User’s Manual U19880EE1V0UM00
A E1
A E2
A E3
A E4
A E5
A E6
A E7
A E8
A E9
A E10
A E11
A E12
A E13
A E14
A E15
A E16
A E17
A E18
A E19
A E20
A E21
A E22
A E23
A E24
A E25
A E26
A F1
A F2
A F3
A F4
A F5
A F6
A F7
A F8
A F9
A F10
A F11
A F12
A F13
A F14
A F15
A F16
A F17
A F18
A F19
A F20
A F21
A F22
A F23
A F24
A F25
A F26
2.5V
GND
M0
LV R 1_D 0
LV T2_D 0
LV T2_D 6
LV T2_D 11
LV T2_C LKIN
LV R 2_D 12
LV R 2_D 6
LV R 2_D E
LV T3_D 5
LV T3_D 13
LV R 3_C LKO U T
LV R 3_D 12
LV R 3_D 5
U A R T3_EN
U A R T3_D I
V ID EO 2_B 51
V ID EO 2_B 52
V ID EO 2_B 53
V ID EO 2_A 47
V ID EO 2_A 48
V ID EO 2_A 49
GND
2.5V
GND
2.5V
M2
LV R 1_D E
LV T2_D 1
LV T2_D 7
LV T2_D 12
LV R 2_C LKO U T
2.5V
LV R 2_D 5
LV T3_D E
LV T3_D 6
LV T3_D 14
LV R 3_D 17
LV R 3_D 11
LV R 3_D 4
U A R T3_R O
2.5V
V ID EO 2_A 50
V ID EO 2_A 51
V ID EO 2_A 52
V ID EO 2_A 53
V ID EO 2_B 56
V ID EO 2_B 57
2.5V
GND
35
IMAPCAR2 Video I/F Board
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
A 24
A 25
A 26
B1
B2
B3
B4
B5
B6
B7
B8
B9
B 10
B 11
B 12
B 13
B 14
B 15
B 16
B 17
B 18
B 19
B 20
B 21
B 22
B 23
B 24
B 25
B 26
G ND
2.5V
A 11
A 17
A 24
D3
D9
D 14
2.5V
C A R 2_P O R TO 1
C A R 2_P O R TO 8
C A R 2_P O R TI5
SYS_C LK
YO B I_P O R T2
P IO _V IO 0
C H 0_ID 1
C H 0_ID 6
2.5V
V SYN C I_B 1
C H 1_ID 2
P IO _V IO 8
C H 2_ID 6
O D D EV EN O 0
TM S
2.5V
G ND
2.5V
G ND
A 10
A 16
A 23
D0
D6
D 15
C S_B 1
C A R 2_P O R TO 0
C A R 2_P O R TO 7
C A R 2_P O R TI4
R ESER V ED _A 0
R ESER V ED _B 0
P IO _V IO 2
C H 0_ID 0
C H 0_ID 9
C H 0_ID 15
H SYN C I_B 1
C H 1_ID 5
O D D EV EN I2
C H 2_ID 9
V SYN C O 0_B
TC K
G ND
2.5V
C1
C2
C3
C4
C5
C6
C7
C8
C9
C 10
C 11
C 12
C 13
C 14
C 15
C 16
C 17
C 18
C 19
C 20
C 21
C 22
C 23
C 24
C 25
C 26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D 10
D 11
D 12
D 13
D 14
D 15
D 16
D 17
D 18
D 19
D 20
D 21
D 22
D 23
D 24
D 25
D 26
TD I
H SW A P _EN
G ND
A 15
A 22
D1
3.3V
D 12
W A IT_B 1
YO B I_P O R T3
3.3V
C A R 2_P O R TI3
C A R 2_C SI_TX
R ES ER V ED _B 1
P IO _V IO 4
3.3V
C H 0_ID 8
C H 0_ID 14
SC LK2I1
3.3V
V SYN C I_B 2
C H 2_ID 8
H SYN C O 0_B
G ND
C H 1_O D 4
P IO _V IO 12
A3
A7
P R O G _B
G ND
A 21
A 28
D7
D 13
C S_B 0
YO B I_B U SR EQ
C A R 2_P O R TO 6
G ND
C A R 2_C SI_R X
YO B I_P O R T1
G ND
C H 0_ID 3
C H 0_ID 11
P IO _V IO 5
SC LKI1
C H 1_ID 4
H SYN C I_B 2
C H 2_ID 11
G ND
TD O
C H 1_O D 7
P IO _V IO 13
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
A2
A6
A9
A 14
A 20
A 27
D4
D 10
W A IT_B 0
YO B I_B U SB U SY
C A R 2_P O R TO 5
C A R 2_P O R TI2
C A R 2_C SI_C LK
G R O B A L_S R ES ET
O D D EV EN I0
C H 0_ID 2
C H 0_ID 10
O D D EV EN I1
C H 1_ID 1
C H 1_ID 7
SC LK2I2
C H 2_ID 10
SC LK2O 0
C H 0_O D 7
C H 1_O D 6
P IO _V IO 14
A1
A5
A8
A 13
A 19
A 26
D5
D 11
W R _B
C S_B 2
C A R 2_P O R TO 4
C A R 2_P O R TI1
C A R 2_IN TP 2
C A R 2_C SI_C S
V SYN C I_B 0
C H 0_ID 5
C H 0_ID 13
P IO _V IO 1
C H 1_ID 0
C H 1_ID 6
SC LKI2
R ES ER V ED _C 0
SC LKO 0
C H 0_O D 6
C H 2_O D 1
P IO _V IO 15
G1
G2
G3
G4
G5
G6
G7
G8
G9
G 10
G 11
G 12
G 13
G 14
G 15
G 16
G 17
G 18
G 19
G 20
G 21
G 22
G 23
G 24
G 25
G 26
H1
H2
H3
H4
H5
H6
H7
H8
H9
H 10
H 11
H 12
H 13
H 14
H 15
H 16
H 17
H 18
H 19
H 20
H 21
H 22
H 23
H 24
H 25
H 26
Preliminary User’s Manual U19880EE1V0UM00
V ID EO 2_B 1
A4
3.3V
A 12
A 18
A 25
D2
D8
R D _B
W A IT_B 2
C A R 2_P O R TO 3
C A R 2_P O R TI0
C A R 2_IN TP 1
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
C A R 2_ER R O R O U T J14
H SYN C I_B 0
J15
C H 0_ID 4
J16
C H 0_ID 12
J17
P IO _V IO 3
J18
C H 1_ID 3
J19
C H 1_ID 9
J20
C H 2_ID 1
J21
C H 2_ID 13
J22
C H 0_O D 1
J23
3.3V
J24
C H 2_O D 0
J25
P IO _V IO 16
J26
V ID EO 2_A 1
K1
V ID EO 2_B 2
K2
V ID EO 2_A 2
K3
V ID EO 2_B 3
K4
V ID EO 2_A 3
K5
V ID EO 2_B 4
K6
V ID EO 2_A 4
K7
1.2V
K8
3.3V
K9
3.3V
K10
C A R 2_P O R TO 2 K11
C A R 2_P O R TO 9 K12
C A R 2_IN TP 0
K13
SC LKI0
K14
SC LK2I0
K15
C H 0_ID 7
K16
3.3V
K17
3.3V
K18
1.2V
K19
C H 1_ID 8
K20
C H 2_ID 0
K21
C H 2_ID 12
K22
C H 0_O D 0
K23
C H 1_O D 1
K24
C H 2_O D 3
K25
P IO _V IO 17
K26
2.5V
V ID EO 2_B 5
V ID EO 2_A 5
V ID EO 2_B 6
V ID EO 2_A 6
V ID EO 2_B 7
V ID EO 2_A 7
3.3V
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
1.2V
1.2V
3.3V
C H 1_ID 11
C H 2_ID 3
C H 2_ID 15
C H 0_O D 3
C H 1_O D 0
C H 2_O D 2
2.5V
V ID EO 2_B 8
V ID EO 2_A 8
V ID EO 2_B 9
V ID EO 2_A 9
V ID EO 2_B 10
V ID EO 2_A 10
V ID EO 2_B 11
3.3V
1.2V
1.2V
G ND
G ND
3.3V
3.3V
G ND
G ND
1.2V
1.2V
3.3V
C H 1_ID 10
C H 2_ID 2
C H 2_ID 14
C H 0_O D 2
C H 1_O D 3
C H 2_O D 5
P IO _V IO 18
36
IMAPCAR2 Video I/F Board
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
M2
M3
M4
M5
M6
M7
M8
M9
M 10
M 11
M 12
M 13
M 14
M 15
M 16
M 17
M 18
M 19
M 20
M 21
M 22
M 23
M 24
M 25
M 26
V ID EO 2_A 11
V ID EO 2_B 12
3.3V
V ID EO 2_A 12
V ID EO 2_B 13
V ID EO 2_A 13
V ID EO 2_B 14
V ID EO 2_A 14
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
C H 1_ID 12
C H 1_ID 13
C H 2_ID 5
P IO _V IO 7
C H 0_O D 5
3.3V
C H 2_O D 4
P IO _V IO 19
V ID EO 2_B 15
V ID EO 2_A 15
V ID EO 2_B 16
G ND
V ID EO 2_A 16
V ID EO 2_B 17
V ID EO 2_A 17
V ID EO 2_B 18
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
C H 1_ID 14
C H 1_ID 15
C H 2_ID 4
P IO _V IO 11
G ND
C H 1_O D 2
C H 2_O D 7
P IO _V IO 20
N1
N2
N3
N4
N5
N6
N7
N8
N9
N 10
N 11
N 12
N 13
N 14
N 15
N 16
N 17
N 18
N 19
N 20
N 21
N 22
N 23
N 24
N 25
N 26
P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15
P 16
P 17
P 18
P 19
P 20
P 21
P 22
P 23
P 24
P 25
P 26
V ID EO 2_A 18
V ID EO 2_B 19
V ID EO 2_A 19
V ID EO 2_B 20
V ID EO 2_A 20
V ID EO 2_B 21
V ID EO 2_A 21
V ID EO 2_B 22
3.3V
3.3V
GND
GND
GND
GND
GND
GND
3.3V
3.3V
P IO _V IO 10
P IO _V IO 6
C H 2_ID 7
P IO _V IO 9
C H 0_O D 4
C H 1_O D 5
C H 2_O D 6
P IO _V IO 21
V ID EO 2_A 22
V ID EO 2_B 23
V ID EO 2_A 23
V ID EO 2_B 24
V ID EO 2_A 24
V ID EO 2_B 25
V ID EO 2_A 25
V ID EO 2_B 26
3.3V
3.3V
GND
GND
GND
GND
GND
GND
3.3V
3.3V
TES T_SW 1
TES T_SW 2
TES T_SW 3
TES T_SW 4
TES T_SW 5
TES T_SW 6
TES T_SW 7
TES T_SW 8
R1
R2
R3
R4
R5
R6
R7
R8
R9
R 10
R 11
R 12
R 13
R 14
R 15
R 16
R 17
R 18
R 19
R 20
R 21
R 22
R 23
R 24
R 25
R 26
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
V ID EO 2_A 26
V ID EO 2_B 27
V ID EO 2_A 27
G ND
V ID EO 2_B 28
V ID EO 2_A 28
V ID EO 2_B 29
V ID EO 2_A 29
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
TEST_LED 1
TEST_LED 2
TEST_LED 3
TEST_LED 4
G ND
TEST_LED 5
TEST_LED 6
TEST_LED 7
V ID EO 2_B 30
V ID EO 2_A 30
3.3V
V ID EO 2_B 31
V ID EO 2_A 31
V ID EO 2_B 32
V ID EO 2_A 32
V ID EO 2_B 33
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
3.3V
TEST_SW 9
TEST_SW 10
TEST_SW 11
TEST_SW 12
TEST_SW 13
3.3V
TEST_SW 14
TEST_SW 15
Preliminary User’s Manual U19880EE1V0UM00
U1
U2
U3
U4
U5
U6
U7
U8
U9
U 10
U 11
U 12
U 13
U 14
U 15
U 16
U 17
U 18
U 19
U 20
U 21
U 22
U 23
U 24
U 25
U 26
V1
V2
V3
V4
V5
V6
V7
V8
V9
V 10
V 11
V 12
V 13
V 14
V 15
V 16
V 17
V 18
V 19
V 20
V 21
V 22
V 23
V 24
V 25
V 26
V ID EO 2_A 33
V ID EO 2_B 34
V ID EO 2_A 34
V ID EO 2_B 35
V ID EO 2_A 35
V ID EO 2_B 36
V ID EO 2_A 36
3.3V
1.2V
1.2V
GND
GND
3.3V
3.3V
GND
GND
1.2V
1.2V
3.3V
TEST_LED 8
SV _B U SB U S Y
SV _B U SR EQ
SV _B U SSTA T
SV _B U SR ESET
D X_D O N E
SV _B U R S T
2.5V
V ID EO 2_B 37
V ID EO 2_A 37
V ID EO 2_B 38
V ID EO 2_A 38
V ID EO 2_B 39
V ID EO 2_A 39
3.3V
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
1.2V
1.2V
3.3V
TEST_SW 16
TP 48
TP 50
TP 49
TP 52
R ES ER V ED _D 10
2.5V
37
IMAPCAR2 Video I/F Board
W1
W2
W3
W4
W5
W6
W7
W8
W9
W 10
W 11
W 12
W 13
W 14
W 15
W 16
W 17
W 18
W 19
W 20
W 21
W 22
W 23
W 24
W 25
W 26
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
V ID EO 2_B 40
V ID EO 2_A 40
V ID EO 2_B 41
V ID EO 2_A 41
V ID EO 2_B 42
V ID EO 2_A 42
V ID EO 2_B 43
1.2V
3.3V
3.3V
SR 0_IO 14
SR 0_A 13
SR 1_A 6
SR 1_IO 3
SR 1_A 2
SR A M 1_O EB
3.3V
3.3V
1.2V
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
A A 10
A A 11
A A 12
A A 13
A A 14
A A 15
A A 16
A A 17
A A 18
A A 19
R ES ER V ED _D 7 A A 20
R ES ER V ED _D 6 A A 21
C A R 2_H D R S TB A A 22
C A R 2_D C O N I9
A A 23
C A R 2_D C O N I0
A A 24
C A R 2_FA ILD C
A A 25
C A R 2_R EG O N 25 A A 26
V ID EO 2_A 43
AB1
V ID EO 2_B 44
AB2
3.3V
AB3
V ID EO 2_A 44
AB4
V ID EO 2_B 45
AB5
V ID EO 2_A 45
AB6
V ID EO 2_B 46
AB7
V ID EO 2_A 46
AB8
V ID EO 2_B 47
AB9
V ID EO 2_A 47
A B 10
SR 0_IO 13
A B 11
SR 0_A 12
A B 12
SR 1_A 5
A B 13
SR 2_IO 2
A B 14
O P _D O
A B 15
SR A M 1_U B B
A B 16
SR 1_IO 12
A B 17
SR 1_A 11
A B 18
SR 2_A 5
A B 19
SR 2_IO 3
A B 20
SR 2_A 2
A B 21
SR A M 2_U B B
A B 22
SR 2_IO 11
A B 23
3.3V
A B 24
R ES ER V ED _D 9 A B 25
R ES ER V ED _D 8 A B 26
V ID EO 2_B 48
V ID EO 2_A 48
V ID EO 2_B 49
V ID EO 2_A 49
R ES ER V ED _G 0
V ID EO 2_B 50
V ID EO 2_A 50
V ID EO 2_B 51
V ID EO 2_A 51
SR 0_A 15
SR 0_IO 12
SR 0_A 11
SR A M 1_W EB
SR 1_IO 1
SR 1_A 1
SR A M 1_LB B
SR 1_IO 11
SR 1_A 10
SR A M 2_W EB
SR 1_IO 2
SR 2_A 1
SR A M 2_LB B
SR 2_IO 10
SR 2_A 11
R ES ER V ED _D 5
R ES ER V ED _D 4
V ID EO 2_B 52
V ID EO 2_A 52
V ID EO 2_B 53
V ID EO 2_A 53
V ID EO 2_B 54
V ID EO 2_A 54
V ID EO 2_B 55
V ID EO 2_A 55
V ID EO 2_B 56
SR A M 0_O EB
SR 0_IO 11
SR 0_A 10
SR 1_IO 8
SR A M 1_C SB
SR 1_A 0
SR 1_IO 16
SR 1_IO 10
SR 2_A 9
SR 2_IO 8
SR 2_IO 1
SR 2_A 0
SR 2_IO 16
SR 2_IO 9
SR 2_A 10
R ES ER V ED _D 3
R ES ER V ED _D 2
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
A C 10
A C 11
A C 12
A C 13
A C 14
A C 15
A C 16
A C 17
A C 18
A C 19
A C 20
A C 21
A C 22
A C 23
A C 24
A C 25
A C 26
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
A D 10
A D 11
A D 12
A D 13
A D 14
A D 15
A D 16
A D 17
A D 18
A D 19
A D 20
A D 21
A D 22
A D 23
A D 24
A D 25
A D 26
V ID EO 2_A 56
V ID EO 2_B 57
M1
G ND
V ID EO 2_A 57
SR 0_IO 6
SR 0_IO 2
SR 0_A 4
SR 0_A 0
SR A M 0_U B B
SR 0_IO 10
G ND
SR 1_IO 7
X_IN T
G ND
SR 1_IO 15
SR 1_IO 9
SR 2_A 8
SR 2_IO 7
SR A M 2_C S B
SR 2_A 17
SR 2_IO 15
G ND
DO NE
R ES ER V ED _D 1
R ES ER V ED _D 0
SR 0_A 9
SR 0_A 8
G ND
SR 0_A 7
SR A M 0_W EB
SR 0_IO 5
3.3V
SR 0_A 3
SR 0_A 17
SR A M 0_LB B
3.3V
SR 1_A 9
SR 1_IO 6
R ES ER V ED _E3
SR 1_A 17
3.3V
SR 1_A 14
SR 2_A 7
SR 2_IO 6
3.3V
SR 2_A 16
SR 2_IO 14
SR 2_A 14
G ND
R ES ER V ED _E0
C C LK
Preliminary User’s Manual U19880EE1V0UM00
A E1
A E2
A E3
A E4
A E5
A E6
A E7
A E8
A E9
A E10
A E11
A E12
A E13
A E14
A E15
A E16
A E17
A E18
A E19
A E20
A E21
A E22
A E23
A E24
A E25
A E26
A F1
A F2
A F3
A F4
A F5
A F6
A F7
A F8
A F9
A F10
A F11
A F12
A F13
A F14
A F15
A F16
A F17
A F18
A F19
A F20
A F21
A F22
A F23
A F24
A F25
A F26
2.5V
GND
M0
SR 0_A 6
SR 0_IO 8
SR 0_IO 4
SR 0_IO 1
SR 0_A 2
SR 0_A 16
SR 0_IO 16
SR 0_IO 9
SR 1_A 8
SR 1_IO 5
SR 1_A 4
SR 1_A 16
SR 1_IO 14
SR 1_A 13
SR 2_A 6
SR 2_IO 5
SR 2_A 4
SR 2_A 15
SR 2_IO 13
SR 2_A 13
R ES ER V ED _E1
GND
2.5V
GND
2.5V
M2
SR 0_A 5
SR 0_IO 7
SR 0_IO 3
SR A M 0_C SB
SR 0_A 1
2.5V
SR 0_IO 15
SR 0_A 14
SR 1_A 7
SR 1_IO 4
SR 1_A 3
SR 1_A 15
SR 1_IO 13
SR 1_A 12
2.5V
SR 2_IO 4
SR 2_A 3
SR A M 2_O EB
SR 2_IO 12
SR 2_A 12
R ES ER V ED _E2
2.5V
GND
38
IMAPCAR2 Video I/F Board
5.2 FPGA ROM configuration
Supplier : Xilinx
Model
: XCF08PVOG48C 48pinTSOP
For more information, please refer to the Platform Flash In-System
Programmable Configuration PROMS data sheet.
5.3 High speed status random access memory
Supplier : NEC
Model
: ML86V7655 µPD444016LG5-A8-7JF-A 44pinTSOP
Features
•
262,144 words by 16 bits organization
•
Fast access time : 8, 10, 12 ns (MAX.)
•
Byte data control : /LB (I/O1 – I/O8), /UB (I/O9 – I/O16)
•
Output Enable input for easy application
•
3.3 V single power supply
For more information, please refer to the uPD444016L data sheet.
5.4 LVDS
Supplier : Thine
Model
: THCV213 48pinTQFP / THCV214 48pinTQFP
Features
•
Transmit 18bit data and 4bit control data through a
•
single differential cable
•
Wide frequency range: 5MHz to 40MHz
•
Support INIT pattern and LOCK indicator
•
Pre Emphasis Mode
•
Clock Edge Selectable
•
Dual Display Mode
•
Power Down Mode
•
Low power single 3.3V CMOS design
•
48pin TQFP/QFN
For more information, please refer to the THCV213/THC214 data sheet.
Preliminary User’s Manual U19880EE1V0UM00
39
IMAPCAR2 Video I/F Board
5.5 NTSC decoder/encoder
Supplier : OKI
Model
: ML86V7655 / ML86V7656 100pinTQFP
Features
•
Supported video type: NTSC/PAL
•
Scanning method: Interlace/Progressive/Single-field signals
•
Input data format
•
•
•
o
ITU-R BT.656-4 type (Y/CbCr 4:2:2 10-bit multiplexing,
synchronization signal information added)
o
ITU-R BT.601 (Y/CbCr 4:2:2 20-bit non-multiplexing (Y/CbCr 4:1:1
20-bit non-multiplexing)
o
Y/CbCr 4:2:2 10-bit multiplexing, without synchronization signal
o
YCbCr 4:2:2 20-bit non-multiplexing (progressive)
o
YCbCr 4:4:4 30-bit/24-bit non-multiplexing (interlaced/progressive)
o
RGB 4:4:4 30-bit/24-bit non-multiplexing (interlaced/progressive)
Input pixel frequency (Input double-speed clock frequency)
o
12.272727 MHz (24.545454 MHz): NTSC Square Pixel
o
13.5 MHz (27 MHz): NTSC/PAL ITU-R BT.601
o
14.318182 MHz (28.636364 MHz): NTSC 4fsc
o
14.75 MHz (29.5 MHz): PAL Square Pixel
o
18 MHz (36 MHz): NTSC/PAL ITU-R BT.601 wide
Output format
o
Composite (CVBS)
o
S-Video (Y/C separate signals)
o
RGB (Interlace/Progressive)
o
YCbCr component (Interlace/Progressive)
Scan type conversion function / Color space conversion function
o
Interlace to Progressive / Progressive to Interlace
o
YCbCr to RGB / RGB to YCbCr
•
Built-in 6ch 11-bit DAC: Capable of simultaneous output of composite, Svideo, YCbCr or RGB
•
Output load resistance: 300 Ohm (A video amp is required when a TV
monitor is connected.)
•
Master/Slave operation (Slave only for ITU-R BT.656 mode)
•
Color bar output
•
3-bit title graphic input interface
•
Luminance adjustment
•
RGB gain adjustment
•
Expanded luminance range mode
Preliminary User’s Manual U19880EE1V0UM00
40
IMAPCAR2 Video I/F Board
•
Synchronization signal level adjustment
•
CGMS/WSS information adding function
•
Supports Macrovision copyguard function (only available in the
ML86V7656)
o
Conforms to version 7.1.L1 for interlace
o
Conforms to version 1.2 for progressive
•
I2C-bus type serial interface
•
Supply voltage: 3.3 V (I/O supply)/2.5 V (core supply) (SCL and SDA pins
only, 5 V tolerant)
•
Package: 100-pin plastic TQFP (TQFP100-P-1414-0.5-K)
(ML86V7655TB/ML86V7656TB)
For more information, please refer to the ML86V7666/ ML86V7665 data sheet.
5.6 RS485 transceivers
Supplier : Linear Technology
Model
: LTC2850CS8 8-LEAD PLASTIC MSOP
Features
•
3.3V Supply Voltage
•
20Mbps Maximum Data Rate
•
No Damage or Latchup Up to ±15kV HBM
•
High Input Impedance Supports 256 Nodes (C, I-Grade)
•
Operation Up to 125°C (H-Grade)
•
Current Limited Drivers and Thermal Shutdown
•
Delayed Micropower Shutdown: 5µA Maximum (C, I-Grade)
•
Power Up/Down Glitch-Free Driver Outputs
•
Low Operating Current: 370µA Typical in Receive Mode
•
Compatible with TIA/EIA-485-A Specifications
For more information, please refer to the LTC2850 data sheet.
5.7 Equipment connection cable
NEC recommends using a category 7 Ethernet cable 7(600MHz/10GBASE-T)
Preliminary User’s Manual U19880EE1V0UM00
41
IMAPCAR2 Video I/F Board
6
Revision history
Version
Date
Document Number
Description
1.0
July 2009
U19880EE1V0UM00
First version
The following revision list shows all functional changes compared to the
previous version.
Chapter
Page
Description
Preliminary User’s Manual U19880EE1V0UM00
42