Download Texas Instruments TMS320C6455 User's Manual

Peripheral Architecture
www.ti.com
2.4.4
Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or
following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and
mode set register commands (MRS and EMRS). During a DCAB command, DEA10 is driven high to
ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command.
Figure 6. DCAB Command
DCAB
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:11, 9:0]
DEA[10]
DBA[2:0]
DSDDQM[3:0]
SPRU970G – December 2005 – Revised June 2011
Submit Documentation Feedback
C6455/C6454 DDR2 Memory Controller
Copyright © 2005–2011, Texas Instruments Incorporated
17