Download Philips Q549.2E User's Manual

Colour Television
Chassis
Q549.2E
LA
18310_000_090317.eps
090317
Contents
Page
Revision List
2
Technical Specifications and, Connections
2
Precautions, Notes, and Abbreviation List
6
Mechanical Instructions
10
Service Modes, Error Codes, and Fault Finding 15
Alignments
36
Circuit Descriptions
42
IC Data Sheets
53
Block Diagrams
Wiring Diagram 32" (Elite Core)
59
Wiring Diagram 37" (Elite Core)
60
Block Diagram Video
62
Block Diagram Audio
63
Block Diagram Control & Clock Signals
64
Block Diagram I2C
65
Supply Lines Overview
66
10. Circuit Diagrams and PWB Layouts
Drawing
Interface Ambilight: Interface + Single DC-DC(AB1)67
Interface Ambilight: Dual DC-DC
(AB2) 68
Interface Ambilight: Microcontrollerblock (AB3) 69
6 LED Low-Pow: Microcontroller Block Liteon(AL1)71
6 LED Low-Pow: Microcontroller Block Liteon(AL2)72
6 LED Low-Pow: LED Liteon
(AL3) 73
8 LED Low-Pow: Microcontroller Block Liteon(AL1)75
8 LED Low-Pow: Microcontroller Block Liteon(AL2)76
8 LED Low-Pow: LED Liteon
(AL3) 77
8 LED Low-Pow: LED Drive Liteon
(AL4) 78
10 LED Low-Pow: Microcontroller Block Liteon(AL1)80
10 LED Low-Pow: Microcontroller Block Liteon(AL2)81
10 LED Low-Pow: LED Liteon
(AL3) 82
10 LED Low-Pow: LED Drive Liteon
(AL4) 83
SSB
(B01A-B10) 85-133
SSB: SRP List Explanation
134
SSB: SRP List Part 1
135
Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
Page
SSB: SRP List Part 2
Light guide
Wi-Fi Antenna
136
139
141
140
141
PWB
70
70
70
74
74
74
79
79
79
79
84
84
84
84
137-138
©
Copyright 2009 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Published by ER/EL 0965 BU TV Consumer Care, the Netherlands
Subject to modification
EN 3122 785 18311
2009-May-08
EN 2
1.
Q549.2E LA
Revision List
1. Revision List
Manual xxxx xxx xxxx.0
• First release.
Manual xxxx xxx xxxx.1
• All Chapters: the following sets to the manual: see Table
2-1 Described Model numbers.
• Chapter 5: paragraph 5.8.10 PCI bus added.
• Chapter 6: paragraph 6.6 Service SSB delivered without
main software loaded added.
2. Technical Specifications and, Connections
Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections
2.4 Chassis Overview
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).
2.1
Technical Specifications
For on-line product support please use the links in Table 2-1.
Here is product information available, as well as getting started,
user manuals, frequently asked questions and software &
drivers.
Table 2-1 Described Model numbers
CTN
2.2
Styling
Published in:
32PFL9604H/12 Elite Core
3122 785 18310
32PFL9604H/60
3122 785 18310
37PFL9604H/12
3122 785 18310
37PFL9604H/60
3122 785 18311
56PFL9954H/12
3122 785 18311
Directions for Use
You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
2009-May-08
Technical Specifications and, Connections
2.3
Q549.2E LA
2.
EN 3
Connections
SERVICE UART
VGA
AUDIO IN VGA
NETWORK
4
3
2
1
18310_001_090317.eps
090317
Figure 2-1 Connection overview
2009-May-08
EN 4
2.
Q549.2E LA
Technical Specifications and, Connections
Note: The following connector colour abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow.
2.3.1
Side Connections
Head phone (Output)
Bk - Head phone
32 - 600 ohm / 10 mW
Cinch: Video CVBS - In, Audio - In
Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm
Ye - Video CVBS
1 VPP / 75 ohm
S-Video (Hosiden): Video Y/C - In
1 - Ground Y
Gnd
2 - Ground C
Gnd
3 - Video Y
1 VPP / 75 ohm
4 - Video C
0.3 VPP / 75 ohm
ot
jq
jq
jq
Cinch: S/PDIF - Out
Bk - Coaxial
0.4 - 0.6VPP / 75 ohm
kq
Cinch: Audio - Out
Rd - Audio - R
Wh - Audio - L
0.5 VRMS / 10 kohm
0.5 VRMS / 10 kohm
kq
kq
EXT3: Cinch: Video YPbPr - In, Audio - In
Gn - Video Y
1 VPP / 75 ohm
Bu - Video Pb
0.7 VPP / 75 ohm
Rd - Video Pr
0.7 VPP / 75 ohm
Rd - Audio - R
0.5 VRMS / 10 kohm
Wh - Audio - L
0.5 VRMS / 10 kohm
jq
jq
jq
jq
jq
EXT1 & 2: Video RGB - In, CVBS - In/Out, Audio - In/Out
H
H
j
j
20
21
2
1
10000_001_090121.eps
090121
USB2.0
Figure 2-4 SCART connector
1
2
3
4
10000_022_090121.eps
090121
Figure 2-2 USB (type A)
1
2
3
4
- +5V
- Data (-)
- Data (+)
- Ground
k
jk
jk
H
Gnd
HDMI: Digital Video, Digital Audio - In
(see HDMI 1, 2, 3 & 4 - Rear Connections)
Common Interface
68p - See diagram B07A SSB: CI: PCMCIA
Connector
2.3.2
jk
Rear Connections
Service Connector (UART)
1 - Ground
Gnd
2 - UART_TX
Transmit
3 - UART_RX
Receive
H
k
j
1
2
3
4
5
6
7
8
- Audio R
- Audio R
- Audio L
- Ground Audio
- Ground Blue
- Audio L
- Video Blue
- Function Select
9
10
11
12
13
14
15
16
- Ground Green
- n.c.
- Video Green
- n.c.
- Ground Red
- Ground P50
- Video Red
- Status/FBL
17
18
19
20
21
- Ground Video
- Ground FBL
- Video CVBS/Y
- Video CVBS
- Shield
Aerial - In
- - IEC-type (EU)
VGA: Video RGB - In
1
0.5 VRMS / 1 kohm
0.5 VRMS / 10 kohm
0.5 VRMS / 1 kohm
Gnd
Gnd
0.5 VRMS / 10 kohm
0.7 VPP / 75 ohm
0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3
Gnd
k
j
k
H
H
j
jk
j
H
0.7 VPP / 75 ohm
j
Gnd
Gnd
0.7 VPP / 75 ohm
0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm
Gnd
Gnd
1 VPP / 75 ohm
1 VPP / 75 ohm
Gnd
H
H
j
j
H
H
k
j
H
Coax, 75 ohm
D
5
10
6
RJ45: Ethernet (if present)
15
11
10000_002_090121.eps
090127
12345678
Figure 2-3 VGA Connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2009-May-08
- Video Red
- Video Green
- Video Blue
- n.c.
- Ground
- Ground Red
- Ground Green
- Ground Blue
- +5VDC
- Ground Sync
- n.c.
- DDC_SDA
- H-sync
- V-sync
- DDC_SCL
0.7 VPP / 75 ohm
0.7 VPP / 75 ohm
0.7 VPP / 75 ohm
j
j
j
Gnd
Gnd
Gnd
Gnd
+5 V
Gnd
H
H
H
H
j
H
DDC data
0-5V
0-5V
DDC clock
j
j
j
j
E_06532_025.eps
210905
Figure 2-5 Ethernet connector
1
2
3
4
5
6
7
8
- TD+
- TD- RD+
- CT
- CT
- RD- GND
- GND
Transmit signal
Transmit signal
Receive signal
Centre Tap: DC level fixation
Centre Tap: DC level fixation
Receive signal
Gnd
Gnd
k
k
j
j
H
H
Technical Specifications and, Connections
Cinch: Audio - In (VGA/DVI)
Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm
jq
jq
HDMI 1, 2, 3 & 4: Digital Video, Digital Audio - In
19
18
1
2
E_06532_017.eps
250505
Figure 2-6 HDMI (type A) connector
1
2
3
4
2.4
- D2+
- Shield
- D2- D1+
Data channel
Gnd
Data channel
Data channel
j
H
j
j
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Q549.2E LA
- Shield
- D1- D0+
- Shield
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- n.c.
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground
2.
EN 5
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Control channel
H
j
j
H
j
j
H
j
jk
DDC clock
DDC data
Gnd
j
jk
H
j
j
H
Hot Plug Detect
Gnd
Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.
2009-May-08
EN 6
3.
Q549.2E LA
Precautions, Notes, and Abbreviation List
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1
Safety Instructions
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
• Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard. Of de set
ontploft!
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
• Route the wire trees correctly and fix them with the
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage.
• Check the strain relief of the Mains/AC Power cord for
proper function.
• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2
•
Warnings
•
•
•
•
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched “on”.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
3.3
Notes
3.3.1
General
•
2009-May-08
Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
3.3.2
Schematic Notes
•
•
•
•
•
•
3.3.3
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 kΩ).
Resistor values with no multiplier may be indicated with
either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
All capacitor values are given in micro-farads (μ = × 10-6),
nano-farads (n = × 10-9), or pico-farads (p = × 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An “asterisk” (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.
Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4
BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
“Magazine”, then go to “Repair downloads”. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5
Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
– To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
Precautions, Notes, and Abbreviation List
3.3.6
3.4
Alternative BOM identification
It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number “1”
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a “2” (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g.
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers
to the Service version change code, digits 5 and 6 refer to the
production year, and digits 7 and 8 refer to production week (in
example below it is 2006 week 17). The 6 last digits contain the
serial number.
MODEL
: 32PF9968/10
PROD.NO: AG 1A0617 000001
MADE IN BELGIUM
220-240V ~ 50/60Hz
128W
VHF+S+H+UHF
S
BJ3.0E LA
10000_024_090121.eps
090121
0/6/12
AARA
ACI
ADC
AFC
AGC
AM
AP
AR
ASF
ATSC
ATV
Auto TV
AV
AVC
AVIP
B/G
BLR
BTSC
Board Level Repair (BLR) or Component Level Repair
(CLR)
If a board is defective, consult your repair procedure to decide
if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
3.3.8
Practical Service Precautions
•
•
It makes sense to avoid exposure to electrical shock.
While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.
3.
EN 7
Abbreviation List
Figure 3-1 Serial number (example)
3.3.7
Q549.2E LA
B-TXT
C
CEC
CL
CLR
ComPair
CP
CSM
CTI
CVBS
DAC
DBE
DDC
D/K
DFI
DFU
DMR
DMSD
DNM
SCART switch control signal on A/V
board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
format
Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
Analogue to Digital Converter
Automatic Frequency Control: control
signal used to tune to the correct
frequency
Automatic Gain Control: algorithm that
controls the video input of the feature
box
Amplitude Modulation
Asia Pacific
Aspect Ratio: 4 by 3 or 16 by 9
Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information
Advanced Television Systems
Committee, the digital TV standard in
the USA
See Auto TV
A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
External Audio Video
Audio Video Controller
Audio Video Input Processor
Monochrome TV system. Sound
carrier distance is 5.5 MHz
Board-Level Repair
Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
Blue TeleteXT
Centre channel (audio)
Consumer Electronics Control bus:
remote control bus on HDMI
connections
Constant Level: audio output to
connect with an external amplifier
Component Level Repair
Computer aided rePair
Connected Planet / Copy Protection
Customer Service Mode
Color Transient Improvement:
manipulates steepness of chroma
transients
Composite Video Blanking and
Synchronization
Digital to Analogue Converter
Dynamic Bass Enhancement: extra
low frequency amplification
See “E-DDC”
Monochrome TV system. Sound
carrier distance is 6.5 MHz
Dynamic Frame Insertion
Directions For Use: owner's manual
Digital Media Reader: card reader
Digital Multi Standard Decoding
Digital Natural Motion
2009-May-08
EN 8
3.
DNR
DRAM
DRM
DSP
DST
DTCP
DVB-C
DVB-T
DVD
DVI(-d)
E-DDC
EDID
EEPROM
EMI
EPLD
EU
EXT
FDS
FDW
FLASH
FM
FPGA
FTV
Gb/s
G-TXT
H
HD
HDD
HDCP
HDMI
HP
I
I2 C
I2 D
I2 S
IF
IR
IRQ
ITU-656
2009-May-08
Q549.2E LA
Precautions, Notes, and Abbreviation List
Digital Noise Reduction: noise
reduction feature of the set
Dynamic RAM
Digital Rights Management
Digital Signal Processing
Dealer Service Tool: special remote
control designed for service
technicians
Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394
Digital Video Broadcast - Cable
Digital Video Broadcast - Terrestrial
Digital Versatile Disc
Digital Visual Interface (d= digital only)
Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
Extended Display Identification Data
(VESA standard)
Electrically Erasable and
Programmable Read Only Memory
Electro Magnetic Interference
Erasable Programmable Logic Device
Europe
EXTernal (source), entering the set by
SCART or by cinches (jacks)
Full Dual Screen (same as FDW)
Full Dual Window (same as FDS)
FLASH memory
Field Memory or Frequency
Modulation
Field-Programmable Gate Array
Flat TeleVision
Giga bits per second
Green TeleteXT
H_sync to the module
High Definition
Hard Disk Drive
High-bandwidth Digital Content
Protection: A “key” encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a “snow vision” mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP “software key”
decoding.
High Definition Multimedia Interface
HeadPhone
Monochrome TV system. Sound
carrier distance is 6.0 MHz
Inter IC bus
Inter IC Data bus
Inter IC Sound bus
Intermediate Frequency
Infra Red
Interrupt Request
The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
SDI), is a digitized video format used
for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
ITV
LS
LATAM
LCD
LED
L/L'
LPL
LS
LVDS
Mbps
M/N
MIPS
MOP
MOSFET
MPEG
MPIF
MUTE
NC
NICAM
NTC
NTSC
NVM
O/C
OSD
OTC
P50
PAL
PCB
PCM
PDP
PFC
PIP
PLL
POD
POR
PTC
PWB
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
Institutional TeleVision; TV sets for
hotels, hospitals etc.
Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
Latin America
Liquid Crystal Display
Light Emitting Diode
Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I
LG.Philips LCD (supplier)
Loudspeaker
Low Voltage Differential Signalling
Mega bits per second
Monochrome TV system. Sound
carrier distance is 4.5 MHz
Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor
Matrix Output Processor
Metal Oxide Silicon Field Effect
Transistor, switching device
Motion Pictures Experts Group
Multi Platform InterFace
MUTE Line
Not Connected
Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe.
Negative Temperature Coefficient,
non-linear resistor
National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
Non-Volatile Memory: IC containing
TV related data such as alignments
Open Circuit
On Screen Display
On screen display Teletext and
Control; also called Artistic (SAA5800)
Project 50: communication protocol
between TV and peripherals
Phase Alternating Line. Color system
mainly used in West Europe (color
carrier= 4.433619 MHz) and South
America (color carrier PAL M=
3.575612 MHz and PAL N= 3.582056
MHz)
Printed Circuit Board (same as “PWB”)
Pulse Code Modulation
Plasma Display Panel
Power Factor Corrector (or Preconditioner)
Picture In Picture
Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency
Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set)
Power On Reset, signal to reset the uP
Positive Temperature Coefficient,
non-linear resistor
Printed Wiring Board (same as “PCB”)
Precautions, Notes, and Abbreviation List
PWM
QRC
QTNR
QVCP
RAM
RGB
RC
RC5 / RC6
RESET
ROM
RSDS
R-TXT
SAM
S/C
SCART
SCL
SCL-F
SD
SDA
SDA-F
SDI
SDRAM
SECAM
SIF
SMPS
SoC
SOG
SOPS
SPI
S/PDIF
SRAM
SRP
SSB
STBY
SVGA
SVHS
SW
SWAN
SXGA
TFT
THD
TMDS
TXT
TXT-DW
UI
uP
UXGA
V
VESA
VGA
VL
VSB
WYSIWYR
WXGA
XTAL
XGA
Pulse Width Modulation
Quasi Resonant Converter
Quality Temporal Noise Reduction
Quality Video Composition Processor
Random Access Memory
Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
Remote Control
Signal protocol from the remote
control receiver
RESET signal
Read Only Memory
Reduced Swing Differential Signalling
data interface
Red TeleteXT
Service Alignment Mode
Short Circuit
Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
Serial Clock I2C
CLock Signal on Fast I2C bus
Standard Definition
Serial Data I2C
DAta Signal on Fast I2C bus
Serial Digital Interface, see “ITU-656”
Synchronous DRAM
SEequence Couleur Avec Mémoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
Sound Intermediate Frequency
Switched Mode Power Supply
System on Chip
Sync On Green
Self Oscillating Power Supply
Serial Peripheral Interface bus; a 4wire synchronous serial data link
standard
Sony Philips Digital InterFace
Static RAM
Service Reference Protocol
Small Signal Board
STand-BY
800 × 600 (4:3)
Super Video Home System
Software
Spatial temporal Weighted Averaging
Noise reduction
1280 × 1024
Thin Film Transistor
Total Harmonic Distortion
Transmission Minimized Differential
Signalling
TeleteXT
Dual Window with TeleteXT
User Interface
Microprocessor
1600 × 1200 (4:3)
V-sync to the module
Video Electronics Standards
Association
640 × 480 (4:3)
Variable Level out: processed audio
output toward external amplifier
Vestigial Side Band; modulation
method
What You See Is What You Record:
record selection that follows main
picture and sound
1280 × 768 (15:9)
Quartz crystal
1024 × 768 (4:3)
Y
Y/C
YPbPr
YUV
Q549.2E LA
3.
EN 9
Luminance signal
Luminance (Y) and Chrominance (C)
signal
Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
Component video
2009-May-08
EN 10
4.
Q549.2E LA
Mechanical Instructions
4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing and Taping
4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
4.1
Notes:
• Figures below can deviate slightly from the actual situation,
due to the different set executions.
Cable Dressing and Taping
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Figure 4-1 Cable dressing 32”
2009-May-08
Mechanical Instructions
Q549.2E LA
4.
EN 11
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Figure 4-2 Cable dressing 37"
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Figure 4-3 Cable dressing 56" (21:9)
2009-May-08
EN 12
4.2
4.
Q549.2E LA
Mechanical Instructions
Service Positions
4.3.3
Each Ambi Light unit is mounted on a subframe. Refer to
Figure 4-5 for details.
For easy servicing of this set, there are a few possibilities
created:
• The buffers from the packaging.
• Foam bars (created for Service).
4.2.1
Ambi Light
Foam Bars
1
1
1
Required for sets
42"
E_06532_018.eps
171106
18310_212_090318.eps
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Figure 4-4 Foam bars
The foam bars (order code 3122 785 90580 for two pieces) can
be used for all types and sizes of Flat TVs.
See Figure 4-4 for details. Sets with a display of 42" and larger,
require four foam bars [1]. Ensure that the foam bars are
always supporting the cabinet and never only the display.
Caution: Failure to follow these guidelines can seriously
damage the display!
By laying the TV face down on the (ESD protective) foam bars,
a stable situation is created to perform measurements and
alignments. By placing a mirror under the TV, you can monitor
the screen.
4.3
Assy/Panel Removal
4.3.1
Rear Cover
Figure 4-5 Ambi Light unit
1. Remove the Ambi Light cover [1].
2. Unplug the connector(s).
3. The PWB can now be taken from the subframe.
When defective, replace the whole unit.
Note: the screws that secure the AmbiLight units are longer
than the other screws.
4.3.4
1. Unplug all connectors.
2. Remove the fixation screws.
3. Take the board out.
When defective, replace the whole unit.
4.3.5
Warning: Disconnect the mains power cord before you remove
the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.
Main Supply Panel
IR & LED Board
Refer to Figure 4-6 for details.
Removing the Piezo Touch Control Panel PWB requires
special attention. Refer to Piezo Touch Control Panel for
details.
1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
4.3.2
Speakers
2
2
2
1
Each speaker unit is mounted with two screws. A sticker on the
the unit indicates if it is the right (“R”) or left (“L”) box, seen from
the front side of the set.
When defective, replace the whole unit.
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Figure 4-6 IR & LED Board
2009-May-08
Mechanical Instructions
Q549.2E LA
4.
EN 13
1. Remove the Main Supply Panel as earlier described.
2. Remove the stand [1] and its subframe [2].
3. Now you gain access the IR & LED board.
When defective, replace the whole unit.
4.3.6
Piezo Touch Control Panel
4
The flexfoil between Piezo Flexfoil Assy (mounted on the
plastic rim of the set), and the PWB as described below, is
extremely vulnerable. Do not pull hard at the PWB or
flexfoil.
Once the flexfoil has been damaged, the entire plastic rim
of the set (with the touch-control pads) has to be swapped!
3
The Piezo Touch Control Panel PWB contains ESD sensitive
components, implying that necessary industrial ESD
precautions must be taken during removing or remounting.
Refer to Figure 4-7, Figure 4-8 and Figure 4-9 for details.
18310_215_090318.eps
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Figure 4-9 Piezo Touch Control Panel -31. To unplug the flexfoil connector, first the outer part of the
connector has to be moved upwards [3], before this part
can be turned sidewards [4] as shown in the picture. Now
the flexfoil can be removed from the connector and the
PWB can be taken out of the set.
When defective, replace the whole unit.
4.3.7
Small Signal Board (SSB)
Caution: It is mandatory to remount screws at their original
position during re-assembly. Failure to do so may result in
damaging the SSB.
1. Remove the Wi-Fi module that is mounted on the SSB.
2. Unplug all connectors.
3. Remove the screws that secure the board.
4. The SSB can now be taken out of the set.
1
4.3.8
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Figure 4-7 Piezo Touch Control Panel -11. Gently pull the bottom side of the PWB out of the cabinet
until you can unplug the connector [1].
2
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Figure 4-8 Piezo Touch Control Panel -2-
LCD Panel
Refer to Figure 4-10 and Figure 4-11 for details.
1. Remove the Piezo Touch Control Panel PWB as earlier
described.
2. Remove the AL covers as earlier described.
3. Remove both Main Supply Panel and SSB as earlier
described.
4. Remove the subframes of Main Power Supply and SSB [1].
5. Remove both AL subframes (with the AL unit still mounted
on it) by unplugging the connector [2] and removing the
screws [3].
6. Remove all remaining adhesive tapes and remove all
cables from their clamps.
7. Carefully remove the conducting tape [4], it must be reused during re-assembly!
8. Remove the remaining screws (indicated with an arrow)
that hold the plastic rim and remove the rim.
9. Now the LCD Panel can be lifted from the front cabinet.
The panel has to be slided downwards once it has been
lifted, because the brackets on the top cannot be removed
from the cabinet. You will see a conducting foam between
metal front and panel, near the location of the Piezo Touch
Control Panel.
When mounting a new LCD Panel:
1. Check if this conducting foam between panel and metal
front is in place !
2. Re-attach the conducting tape between LCD Panel and
metal rim [4] !
1. Now gently pull the top side of the PWB out of the cabinet
without damaging the flexfoil until you can unplug the
connector [2].
2009-May-08
EN 14
4.
Q549.2E LA
4
1
Mechanical Instructions
1
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Figure 4-10 LCD Panel -1-
2
3
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Figure 4-11 LCD Panel -24.3.9
Wi-Fi antenna
Follow the instructions for LCD Panel until “remove plastic rim”.
After removal of this rim, you gain access to the Wi-Fi
antennas.
4.4
Set Re-assembly
To re-assemble the whole set, execute all processes in reverse
order.
Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
2009-May-08
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 15
5. Service Modes, Error Codes, and Fault Finding
•
Index of this chapter:
5.1 Test Points
5.2 Service Modes
5.3 Stepwise Start-up
5.4 Service Tools
5.5 Error Codes
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading
5.1
How to Activate SDM
For this chassis there are two kinds of SDM: an analog SDM
and a digital SDM. Tuning will happen according Table 5-1.
• Analog SDM: use the standard RC-transmitter and key in
the code “062596”, directly followed by the “MENU” (or
HOME) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it “off”, push the “MENU”(or
HOME) button again.
• Digital SDM: use the standard RC-transmitter and key in
the code “062593”, directly followed by the “MENU” (or
HOME) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it “off”, push the “MENU” (or
HOME) button again.
• Analog SDM can also be activated by grounding for a
moment the solder pad on the SSB, with the indication
“SDM” (see Service mode pad).
Test Points
As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
Perform measurements under the following conditions:
• Service Default Mode.
• Video: Colour bar signal.
• Audio: 3 kHz left, 1 kHz right.
5.2
All service-unfriendly modes (if present) are disabled, like:
– (Sleep) timer.
– Child/parental lock.
– Picture mute (blue mute or black mute).
– Automatic volume levelling (AVL).
– Skip/blank of non-favourite pre-sets.
Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section “5.4.1 ComPair”).
SDM
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
5.2.1
Service Default Mode (SDM)
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Purpose
• To create a pre-defined setting, to get the same
measurement results as given in this manual.
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
section “5.3 Stepwise Start-up”.
• To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section “5.5 Error Codes”).
Figure 5-1 Service mode pad
After activating this mode, “SDM” will appear in the upper right
corner of the screen (when a picture is available).
How to Navigate
When the “MENU” (or HOME) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
normal user menu.
Specifications
Table 5-1 SDM default settings
Freq. (MHz)
Default
system
Europe, AP(PAL/Multi)
475.25
PAL B/G
Europe, AP DVB-T
DVB-T
546.00 PID
Video: 0B 06 PID
PCR: 0B 06 PID
Audio: 0B 07
Region
•
•
All picture settings at 50% (brightness, colour, contrast).
All sound settings at 50%, except volume at 25%.
How to Exit SDM
Use one of the following methods:
• Switch the set to STAND-BY via the RC-transmitter.
• Via a standard customer RC-transmitter: key in “00”sequence.
5.2.2
Service Alignment Mode (SAM)
Purpose
• To perform (software) alignments.
• To change option settings.
• To easily identify the used software version.
2009-May-08
EN 16
•
•
5.
Q549.2E LA
Service Modes, Error Codes, and Fault Finding
To view operation hours.
To display (or clear) the error code buffer.
TV will go to the Stand-by mode. If the NVM was corrupted or
empty before this action, it will be initialized first (loaded with
default values). This initializing can take up to 20 seconds.
How to Activate SAM
Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” button. After activating SAM
with this method a service warning will appear on the screen,
continue by pressing the “OK” button on the RC.
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, it’s advised to use ComPair (the correct
HEX values for the options can be found in Chapter 6.
Alignments) or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code “062598” directly followed by the “MENU” (or HOME)
button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned in Table 6-3). Make sure to key in all three
digits, also the leading zero’s. If the above action is successful,
the front LED will go out as an indication that the RC sequence
was correct. After the display option is changed in the NVM, the
2009-May-08
39mm
PHILIPS
27mm
Contents of SAM (see also Table 6-4)
• Hardware Info.
– A. SW Version. Displays the software version of the
main software (example: Q5492-1.2.3.4 =
AAAAB_X.Y.W.Z).
• AAAA= the chassis name.
• B= the SW branch version. This is a sequential
number (this is no longer the region indication, as
the software is now multi-region).
• X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
– B. STBY PROC Version. Displays the software
version of the stand-by processor.
– C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
• Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched “on/off”, 0.5 hours is added to this number.
• Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section “5.5 Error Codes”).
• Reset Error Buffer. When “cursor right” (or the “OK
button) is pressed and then the “OK” button is pressed, the
error buffer is reset.
• Alignments. This will activate the “ALIGNMENTS” submenu. See Chapter 6. Alignments.
• Dealer Options. Extra features for the dealers.
• Options. Extra features for Service. For more info
regarding option codes, 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the “OK” button before
the options are stored. Otherwise changes will be lost.
• Initialize NVM. The moment the processor recognizes a
corrupted NVM, the “initialize NVM” line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
– Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
– Initialize the NVM.
Display Option
Code
040
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
(CTN Sticker)
E_06532_038.eps
240108
Figure 5-2 Location of Display Option Code sticker
•
•
•
•
•
•
•
Store - go right. All options and alignments are stored
when pressing “cursor right” (or the “OK” button) and then
the “OK”-button.
SW Maintenance.
– SW Events. Not useful for Service purposes. In case
of specific software problems, the development
department can ask for this info.
– HW Events. Not useful for Service purposes. In case
of specific software problems, the development
department can ask for this info.
Operation hours display. Displays the accumulated total
of display operation hours. So, this one keeps up the
lifetime of the display itself, mainly to compensate the
degeneration behaviour.
Test settings. For development purposes only.
Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
“Channel list”, “Personal settings”, “Option codes”,
“Display-related alignments” and “History list”. First a
directory “repair\” has to be created in the root of the
USB stick. To upload the settings select each item
separately, press “cursor right” (or the “OK” button),
confirm with “OK” and wait until “Done” appears. In case
the download to the USB stick was not successful “Failure”
will appear. In this case, check if the USB stick is
connected properly and if the directory “repair” is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download onto another
TV or other SSB. Uploading is of course only possible if the
software is running and if a picture is available. This
method is created to be able to save the customer’s TV
settings and to store them into another SSB.
Download to USB. To download several settings from the
USB stick to the TV, same way of working needs to be
followed as with uploading. To make sure that the
download of the channel list from USB to the TV is
executed properly, it is necessary to restart the TV and
tune to a valid preset if necessary.
Note: The “History list item” can not be downloaded from
USB to the TV. This is a “read-only” item. In case of
specific problems, the development department can ask
for this info.
How to Navigate
• In SAM, the menu items can be selected with the
“CURSOR UP/DOWN” key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the “CURSOR UP/DOWN” key to
display the next/previous menu items.
• With the “CURSOR LEFT/RIGHT” keys, it is possible to:
– (De) activate the selected menu item.
– (De) activate the selected sub menu.
Service Modes, Error Codes, and Fault Finding
•
With the “OK” key, it is possible to activate the selected
action.
How to Exit SAM
Use one of the following methods:
• Switch the TV set to STAND-BY via the RC-transmitter.
• Via a standard RC-transmitter, key in “00” sequence, or
select the “BACK” key.
5.2.3
Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
When in this chassis CSM is activated, a testpattern will be
displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second
Green). This test pattern is generated by the PNX5100. So if
this test pattern is shown, it could be determined that the back
end video chain (PNX5100, LVDS, and display) of the SSB is
working.
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. This info can be handy if no information is displayed.
Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED. Only the latest error is displayed. (see also
section 5.5 Error Codes).
How to Activate CSM
Key in the code “123654” via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
How to Navigate
By means of the “CURSOR-DOWN/UP” knob on the RCtransmitter, can be navigated through the menus.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
•
•
•
•
Q549.2E LA
5.
EN 17
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
12NC display. Shows the 12NC of the display.
12NC supply. Shows the 12NC of the supply.
12NC “fan board”. Shows the 12NC of the “fan board”module (for sets with LED backlight)
12NC “LED Dimming Panel”. Shows the 12NC of the
LED dimming Panel (for sets with LED backlight).
Software versions
• Current main SW. Displays the built-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q5492_1.2.3.4
• Standby SW. Displays the built-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
Upgrading).
Example: STDBY_88.68.1.2.
• MOP ambient light SW. Displays the MOP ambient light
EPLD SW.
• LED Dimming SW. Displays the LED Dimming EPLD SWversion (for sets with LED backlight).
• Local contrast SW. Displays the MOP local contrast SWversion.
Quality items
• Signal quality. Poor / average /good
• Child lock. Not active / active. This is a combined item for
locks. If any lock (Preset lock, child lock, lock after or
parental lock) is active, the item shall show “active”.
• HDMI HDCP key. Indicates if the HDMI keys (or HDCP
keys) are valid or not. In case these keys are not valid and
the customer wants to make use of the HDMI functionality,
the SSB has to be replaced.
• Ethernet MAC address. Displays the MAC address
present in the SSB.
• Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
• BDS key. Indicates if the “BDS level 1” key is valid or not.
• CI slot present. If the common interface module is
detected the result will be “YES” or “NO”.
• HDMI input format. The detected input format of the
HDMI.
• HDMI audio input stream. The HDMI audio input stream
is displayed: present / not present.
• HDMI video input stream. The HDMI video input stream
is displayed: present / not present.
How to Exit CSM
Press “MENU” (or HOME) / “Back” key on the RC-transmitter.
General
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this.
• Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee a in possibility to
do this.
• Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
• Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
• Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
• 12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
2009-May-08
EN 18
5.3
5.
Q549.2E LA
Service Modes, Error Codes, and Fault Finding
Stepwise Start-up
mode with a faulty FET 7U08 is done, you can destroy all IC’s
supplied by the +3V3, due to overvoltage (12V on 3V3-line). It
is recommended to measure first the FET 7U08 or others
FET’s on shortcircuit before activating SDM via the service
pads.
When the TV is in a protection state due to an error detected by
stand-by software (error blinking is displayed) and SDM is
activated via shortcutting the pins on the SSB, the TV starts up
until it reaches the situation just before protection. So, this is a
kind of automatic stepwise start-up. In combination with the
start-up diagrams below, you can see which supplies are
present at a certain moment. Important to know is, that if e.g.
the 3V3 detection fails and thus error layer 2 = 18 is blinking
while the TV is restarted via SDM, the Stand-by Processor will
enable the 3V3, but the TV set will not go to protection now.
The TV will stay in this situation until it is reset (Mains/AC
Power supply interrupted). Caution: in case the start-up in this
Mains
off
The abbreviations “SP” and “MP” in the figures stand for:
• SP: protection or error detected by the Stand-by
Processor.
• MP: protection or error detected by the MIPS Main
Processor.
Mains
on
WakeUp
requested
- WakeUp requested
- Acquisition needed
St by
- Tact switch Pushed
- last status is hibernate
after mains ON
- No data Acquisition
required
- tact SW pushed
- last status is hibernate
after mains ON
Semi
St by
Active
- St by requested
- tact SW pushed
Tact switch
pushed
WakeUp
requested
(SDM)
GoToProtection
Hibernate
GoToProtection
Protection
I_17660_124.eps
140308
Figure 5-3 Transition diagram
2009-May-08
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 19
Off
Stand by or
Protection
Mains is applied
Standby Supply starts running.
All standby supply voltages become available .
st-by µP resets
Initialise I/O pins of the st-by µP:
- Switch reset-AVC LOW (reset state)
- Switch WP-NandFlash LOW (protected)
- Switch reset-system LOW (reset state)
- Switch reset-5100 LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-ST7100 LOW (reset state)
- keep reset-NVM high, Audio-reset and Audio-Mute-Up HIGH
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.
- Switch Audio-Reset high.
It is low in the standby mode if the standby
mode lasted longer than 10s.
start keyboard scanning, RC detection. Wake up reasons are
off.
Important remark; the appearance of the +12V
will start the +1V2 DCDC converter automatically
Switch ON Platform and display supply by switching
LOW the Standby line.
+12V, +/-12Vs, AL and Bolt-on power
is switched on, followed by the +1V2 DCDC converter
Detect2 should be polled on the standard 40ms
interval and startup should be continued when
detect2 becomes high.
Detect2 high received
within 1 second?
Enter protection
Yes
Supply-fault I/O
High?
Power-OK error:
Layer1: 3
Layer2: 16
No
The supply-fault line is a
combination of the DCDC
converters and the audio
protection line.
1V2 DCDC or class D error:
Layer1: 2
Layer2: 19
No
Enter protection
Yes
This enables the +3V3 and
+5V converter. As a result,
also +5V-tuner, +2V5, +1V8PNX8541 and +1V8-PNX5100
become available.
Enable the DCDC converter for +3V3 and
+5V. (ENABLE-3V3)
Delay of 50ms needed because of the latency of the detect-1 circuit.
This delay is also needed for the PNX5100. The reset of the
PNX5100 should only be released 10ms after powering the IC.
Wait 50ms
Supply-fault I/O
High?
Enter protection
yes
Detect-1 I/O line
High?
3V3 / 5V DCDC or class D error:
Layer1: 2
Layer2: 11
No
Detect-2 I/O line
High?
No
Yes
Yes
Voltage output error:
Layer1: 2
Layer2: 18
Enable the supply fault detection
algorithm
Set I²C slave address
of Standby µP to (A0h)
No
Disable 3V3, switch standby
line high and wait 4 seconds
Added to make the system more robust to
power dips during startup. At this point the
regular supply fault detection algorithm which
normally detects power dips is not up and
running yet.
Enter protection
This will allow access to NVM and
NAND FLASH and can not be done
earlier because the FLASH needs to
be in Write Protect as long as the
supplies are not available.
Switch LOW the RESET-NVM line to allow access to NVM. (Add a
2ms delay before trying to address the NVM to allow correct NVM
initialization , this is not issue in this setup , the delay is automatically
covered by the architectural setup)
Switch HIGH the WP-NandFlash to
allow access to NAND Flash
No
Release Reset-PNX5100.
PNX5100 will start booting.
Before PNX8541 boots, the PNX5100 should have
set its PCI arbiter (bootscript command). To allow
this, approx. 1ms is needed. This 1ms is extended
to 10ms to also give some relaxation to the supplies .
Wait 10ms (minimum) to allow the bootscript
of the PNX5100 to configure the PCI arbiter
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
EJTAG probe
connected ?
An EJTAG probe (e.g. WindPower ICE probe) can
be connected for Linux Kernel debugging
purposes.
Yes
No
No
Cold boot?
Yes
Release AVC system reset
Feed warm boot script
To I_17660_125b.eps
Release AVC system reset
Feed cold boot script
Release AVC system reset
Feed initializing boot script
disable alive mechanism
To I_17660_125b.eps
I_17660_125a.eps
140308
Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)
2009-May-08
EN 20
5.
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
From I_17660_125a.eps
From I_17660_125a.eps
Reset-system is switched HIGH by the
AVC at the end of the bootscript
Reset-system is switched HIGH by the
AVC at the end of the bootscript
Release reset MPEG4 module:
BOLT-ON-IO: High
AVC releases Reset-Ethernet when the
end of the AVC boot-script is detected
AVC releases Reset-Ethernet when the
end of the AVC boot-script is detected
MPEG4 module will start booting
autonomously.
Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the
startup process
Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the
startup process
Wait 3000 ms
Reset-system is connected to USB -reset,
4to1HDMI Mux and channel decoder.
This cannot be done through the bootscript,
the I/O is on the standby µP
Timing need to be updated if
more mature info is available.
POR polling positive ?
Bootscript ready
in 1250 ms?
No
No
Log SW event:
STi7100PorFailure
No
Yes
Wait 200 ms
yes
Set I²C slave address
of Standby µP to (60h)
Alive
polling
RPC start (comm. protocol)
Flash to Ram
image transfer succeeded
within 30s?
No
Code =
Layer1: 2
Layer2: 15
Start alive IIC polling
mechanism
yes
POR polling positive ?
NOK
Timing needs to
be updated if more
mature info is
available.
Log SW event
STi7100AliveFailedError
and generate fast cold reboot
eventually followed by a cold
reboot.
No
bootSTi7100PorFailure:
Log HW error
Layer1: 2
Layer2: 38
and generate cold boot
Yes
Switch AVC PNX8541
in reset (active low)
Code =
Layer1: 2
Layer2: 53
No
Wait 10ms
SW initialization
succeeded
within 20s?
Timing needs to be
updated if more
mature info is
available .
Yes
Enable Alive check mechanism
Switch the NVM reset
line HIGH.
MIPS reads the wake up reason
from standby µP.
Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.
Wait until AVC starts to
communicate
Initialize audio
Wait 5ms
Switch on the display in case of a LED backlight
display by sending the TurnOnDisplay(1) (I²C)
command to the PNX5100
switch off the remaining DC/DC
converters
3-th try?
In case of a LED backlight display , a LED DIM panel is
present which is fed by the Vdisplay. To power the LED DIM
Panel, the Vdisplay switch driven by the PNX 5100 must be
closed. The display startup sequence is taken care of by the
LED DIM panel.
Switch Standby
I/O line high.
Yes
Download firmware into the channel
decoder
No
Blink Code as
error code
Enter protection
Third try?
No
Downloaded
successfully ?
Yes
Yes
Log channel decoder error:
Layer1: 2
Layer2: 37
initialize tuner , Master IF and channel
decoder
Initialize source selection
Initialize video processing IC 's
initialize AutoTV
Initialize Ambilight with Lights off .
Semi-Standby
Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)
2009-May-08
I_17660_125b.eps
140308
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 21
Constraints taken into account:
- Display may only be started when valid LVDS output clock can be delivered by the AVC .
- Between 5 and 50 ms after power is supplied, display should receive valid lvds clock .
- minimum wait time to switch on the lamp after power up is 200ms.
action holder: AVC
action holder: St-by
autonomous action
Semi Standby
The assumption here is that a fast toggle (<2s)
can only happen during ON -> SEMI -> ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON-> SEMI>STBY -> SEMI -> ON can be made in less than 2s,
the semi -> stby transition has to be delayed
until the requirement is met.
CPipe already generates a valid output
clock in the semi -standby state: display
startup can start immediately when leaving
the semi-standby state.
The timings to be used in
combination with the PanelON
command for this specific display
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
Assert RGB video blanking
and audio mute
Switch on the display by sending the
TurnOnDisplay(1) (I²C) command to the PNX5100
wait 250ms (min. = 200ms)
Initialize audio and video
processing IC's and functions
according needed use case.
Switch on LCD backlight
(Lamp-ON)
Wait until valid and stable audio and video , corresponding to
the requested output is delivered by the AVC.
The higher level requirement is that audio and
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.
Switch Audio-Reset low and wait 5ms
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
unblank the video.
The higher level requirement is that the
ambilight functionality may not be switched on
before the backlight is turned on in case the
set contains a CE IPB inverter supply.
Switch on the Ambilight functionality according the last status
settings.
Active
I_17660_126.eps
140308
Figure 5-6 “Semi Stand-by” to “Active” flowchart
2009-May-08
EN 22
5.
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
Constraints taken into account:
- Display may only be started when valid LVDS output clock can be delivered by the AVC .
- Between 5 and 50 ms after power is supplied, display should receive valid lvds clock .
- minimum wait time to switch on the lamp after power up is 200ms.
- To have a reliable operation of the backlight, the backlight should be driven with a PWM duty cycle of 100%
during the first second. Only after this first one or two seconds, the PWM may be set to the required output level
(Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts, the
picture should only be unblanked after these first seconds.
action holder: AVC
action holder: St-by
autonomous action
Semi Standby
The assumption here is that a fast toggle (<2s)
can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON -> SEMI->STBY -> SEMI -> ON can be made in less than 2s,
the semi -> stby transition has to be delayed
until the requirement is met.
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
Assert RGB video blanking
and audio mute
CPipe already generates a valid output
clock in the semi -standby state: display
startup can start immediately when leaving
the semi-standby state.
Switch on the display by sending the
TurnOnDisplay(1) (I²C) command to the PNX5100
wait 250ms (min. = 200ms)
Initialize audio and video
processing IC's and functions
according needed use case.
Switch off the dimming backlight feature, set
the BOOST control to nominal and make sure
PWM output is set to 100%
Switch on LCD backlight
(Lamp-ON)
Wait until valid and stable audio and video , corresponding to the requested
output is delivered by the AVC
AND
[the backlight PWM has been on for 1s (internal inverter LPL displays
OR the backlight PWM has been on for 2s (external inverter LPL displays)] .
The higher level requirement is that audio and
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.
Switch Audio-Reset low and wait 5ms
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
Restore dimming backlight feature, PWM and BOOST output
and unblank the video.
The higher level requirement is that the
ambilight functionality may not be switched on
before the backlight is turned on in case the
set contains a CE IPB inverter supply.
Switch on the Ambilight functionality according the last status
settings.
Active
Figure 5-7 “Semi Stand-by” to “Active” flowchart LCD with preheat
2009-May-08
I_17660_127.eps
140308
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 23
action holder: AVC
Constraints taken into account:
- Display may only be started when valid LVDS output clock can be delivered by the AVC .
- Between 5 and 50 ms after power is supplied, display should receive valid lvds clock .
- minimum wait time to switch on the lamp after power up is 200ms.
action holder : St-by
autonomous action
Semi Standby
The assumption here is that a fast toggle (<2s)
can only happen during ON -> SEMI -> ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON -> SEMI>STBY->SEMI->ON can be made in less than 2s,
the semi -> stby transition has to be delayed
until the requirement is met.
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
Assert RGB video blanking
and audio mute
CPipe already generates a valid output
clock in the semi -standby state: display
startup can start immediately when leaving
the semi-standby state.
Switch on the display by sending the OUTPUTENABLE (I²C) command to the LED DIM panel
wait 250ms (min. = 200ms)
TBC in def. spec
Initialize audio and video
processing IC's and functions
according needed use case.
Switch on LCD backlight
(Lamp-ON)
Wait until valid and stable audio and video , corresponding to
the requested output is delivered by the AVC.
The higher level requirement is that audio and
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.
Switch Audio-Reset low and wait 5ms
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
unblank the video.
The higher level requirement is that the
ambilight functionality may not be switched on
before the backlight is turned on in case the
set contains a CE IPB inverter supply.
Switch on the Ambilight functionality according the last status
settings.
Active
I_17660_128.eps
140308
Figure 5-8 “Semi Stand-by” to “Active” flowchart (LED backlight)
2009-May-08
EN 24
5.
Q549.2E LA
Service Modes, Error Codes, and Fault Finding
Active
action holder: AVC
action holder: St-by
autonomous action
Mute all sound outputs via softmute
Wait 100ms
Set main amplifier mute (I/O: audio-mute)
Force ext audio outputs to ground
(I/O: audio reset)
And wait 5ms
switch off Ambilight
Wait until Ambilight has faded out
(fixed wait time of x s)
The higher level requirement is that the
backlight may not be switched off before the
ambilight functionality is turned off in case the
set contains a CE IPB inverter supply.
switch off LCD backlight
Mute all video outputs
Wait 250ms (min. = 200ms)
Switch off the display by sending the
TurnOnDisplay(0) (I²C) command to the PNX5100
Semi Standby
I_17660_129.eps
140308
Figure 5-9 “Active” to “Semi Stand-by” flowchart (LCD non DFI)
2009-May-08
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
Semi Stand by
5.
EN 25
action holder: MIPS
action holder: St-by
autonomous action
If ambientlight functionality was used in semi -standby
(lampadaire mode), switch off ambient light
Delay transition until ramping down of ambient light is
finished. *)
*) If this is not performed and the set is
switched to standby when the switch off of
the ambilights is still ongoing , the lights will
switch off abruptly when the supply is cut.
transfer Wake up reasons to the Stand by µP.
Switch Memories to self-refresh (this creates a more
stable condition when switching off the power).
Switch AVC system in reset state
Switch reset-PNX5100 LOW
Switch reset-ST7100 LOW
Switch Reset-Ethernet LOW
Wait 10ms
Switch the NVM reset line HIGH
Switch het WP-Nandflash LOW
Disable all supply related protections and switch off
the DC/DC converters (ENABLE-3V3)
Wait 5ms
Switch OFF all supplies by switching HIGH the
Standby I/O line
Important remark:
release reset audio 10 sec after
entering standby to save power
Stand by
I_17660_130.eps
140308
Figure 5-10 “Semi Stand-by” to “Stand-by” flowchart
2009-May-08
EN 26
5.
Q549.2E LA
action holder: MIPS
Service Modes, Error Codes, and Fault Finding
MP
SP
action holder: St-by
autonomous action
Log the appropriate error and
set stand-by flag in NVM
Redefine wake up reasons for protection
state and transfer to stand-by µP.
Switch off LCD lamp supply
If needed to speed up this transition,
this block could be omitted . This is
depending on the outcome of the
safety investigations .
Wait 250ms (min. = 200ms)
Switch off LVDS signal
Switch off 12V LCD supply within a time frame of
min. 0.5ms to max. 50ms after LVDS switch off.
Ask stand-by µP to enter protection state
Switch AVC in reset state
Wait 10ms
Switch the NVM reset line HIGH.
Disable all supply related protections and switch off
the +1V8 and the +3V3 DC/DC converter.
Wait 5ms
Switch OFF all supplies by switching HIGH the
Standby I/O line.
Flash the Protection-LED in order to indicate
protection state*
(*): This can be the standby LED or the ON LED
depending on the availability in the set
Protection
Figure 5-11 “To Protection State” flowchart
2009-May-08
I_17660_131.eps
140308
Service Modes, Error Codes, and Fault Finding
5.4
Service Tools
5.4.1
ComPair
5.4.2
5.
EN 27
Memory and Audio Test
With this tool you can test the memory of the PNX8543, as well
if the PNX5100 is enabled and audio-testing.
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
What is needed?
– An USB-stick
– “TESTSCRIPT Q549”. Downloadable from the Philips
Service website from the section “Software for Service
only”
– A ComPair/service cable (3138 188 75051).
Procedure
Create a directory “JETTFILES” under the root of the USB-stick
– Place “MemTestTV543.bin” and “autojett.bin” (available in
“TESTSCRIPT Q549”) under the directory “JETTFILES”
– Install the computer program “BOARDTESTLOGGER”
(available in “TESTSCRIPT Q549”) on the PC
– Connect a “ComPair/service”-cable from the serviceconnector in the set, into the “multi function” jack at the
front of the ComPair II box :
Required settings in ComPair :
- start up the ComPair application.
- Select the correct database (open file “Q549.2E LA”, this
will set the ComPair interface in the appropriate mode).
- Close ComPair
– Start up the program “BOARDTESTLOGGER” and select
“COMx”
– Put the USB stick into the TV and start up the TV while
pressing the “i+”-button on a Philips DVD RC6 remote
control (it’s also possible to use a TV remote in “DVD”mode)
– On the PC the memory test is shown now. This is also
visible on the TV screen.
– In “BOARDTESTLOGGER” an option “Send extra UART
command” can be found where you can select “AUD1”.
This command generates hear test tones of 200, 400,
1000, 2000, 3000, 5000, 8000 and 12500Hz.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.
How to Connect
This is described in the chassis fault finding database in
ComPair.
TO TV
TO
UART SERVICE
CONNECTOR
ComPair II
RC in
Q549.2E LA
RC out
TO
I2C SERVICE
CONNECTOR
TO
UART SERVICE
CONNECTOR
Multi
function
Optional Power Link/ Mode
Switch
Activity
I2C
5.5
Error Codes
5.5.1
Introduction
RS232 /UART
PC
ComPair II Developed by Philips Brugge
HDMI
I2C only
Optional power
5V DC
E_06532_036.eps
150208
Figure 5-12 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be
blown!
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• Software is available via the Philips Service web portal.
• ComPair UART interface cable for Q54x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: While encounting problems, contact the local support
desk.
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.
New in this chassis is the way errors can be displayed:
•
•
•
There is a simple blinking LED procedure for board level
repair (home repair) so called LAYER 1 errors next to the
existing errors which are LAYER 2 errors (see Table 5-2).
– LAYER 1 errors are one digit errors.
– LAYER 2 errors are 2 digit errors.
In protection mode.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
Important remark:
2009-May-08
EN 28
•
•
•
•
5.
Q549.2E LA
Service Modes, Error Codes, and Fault Finding
For all errors detected by MIPS which are fatal =>
rebooting of the TV set (reboot starts after LAYER 1
error blinking), one should short the solder paths
(SDM) at start-up from the power OFF state by mains
interruption and not via the power button to trigger the
SDM via the hardware pins.
In CSM mode
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
In SDM mode
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
In the ON state
– In “Display error mode”, set with the RC commands
“mute_06250X _OK” LAYER 2 errors are displayed via
blinking LED.
Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
• Errors detected by the Stand-by software which not
lead to protection. In this case the front LED should blink
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer, Extra Info”. Note that it can take up several
minutes before the TV starts blinking the error (e.g. LAYER
1 error = 2, LAYER 2 error = 15 or 53).
• Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.
5.5.2
How to Read the Error Buffer
Use one of the following methods:
• On screen via the SAM (only when a picture is visible).
E.g.:
– 00 00 00 00 00: No errors detected
– 23 00 00 00 00: Error code 23 is the last and only
detected error.
– 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
– Note that no protection errors can be logged in the
error buffer.
• Via the blinking LED procedure. See section 5.5.3 How to
Clear the Error Buffer.
• Via ComPair.
5.5.3
How to Clear the Error Buffer
Use one of the following methods:
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu.
• With a normal RC, key in sequence “MUTE” followed by
“062599” and “OK”.
• If the content of the error buffer has not changed for 50+
hours, it resets automatically.
5.5.4
Error Buffer
In case of non-intermittent faults, clear the error buffer before
starting to repair (before clearing the buffer, write down the
content, as this history can give significant information). This to
ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
• Via error bits in the status registers of ICs.
2009-May-08
•
•
•
Via polling on I/O pins going to the stand-by processor.
Via sensing of analog values on the stand-by processor or
the PNX8543.
Via a “not acknowledge” of an I2C communication.
Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 29
Table 5-2 Error code overview
Description
Monitored Error/ Error Buffer/
Layer 1 Layer 2 by
Prot Blinking LED Device
Defective Board
I2C3
2
SSB
SSB
I2C2
13
MIPS
E
BL / EB
2
14
MIPS
E
BL / EB
SSB/Display
SSB/display
PNX doesn’t boot (HW cause) 2
PNX 5100 doesn’t boot
15
Stby µP
P
BL
PNX8543/PNX51XX
I2C blocked
SSB
12V
3
16
Stby µP
P
BL
/
Supply
Inverter or display supply
3
17
MIPS
E
EB
/
1V2, 3V3, 5V to low
2
18
Stby µP
P
BL
/
SSB
Temp protection
3
12
MIPS
E
EB
/
Display
PNX 5100
2
21
MIPS
E
EB
PNX5100
SSB
HDMI mux
2
23
MIPS
E
EB
TDA9996
SSB
SSB
I2C switch
2
24
MIPS
E
EB
PCA9540
Boot-NVM PNX5100
2
25
MIPS
E
EB
STM24C08
SSB
Multi Standard demodulator
(Micronas IF)
2
27
MIPS
E
EB
DRX3616K
DRX3626K
SSB
ARM (ambilight)
8
28
MIPS
E
EB
NXP LPC2103
AL module or DC/DC
FPGA (Local contrast)
2
29
MIPS
E
EB
Altera
SSB
Tuner
2
34
MIPS
E
EB
UV1783S/HD1816
SSB
Fan I2C expander
7
41
MIPS
E
EB
PCA9533
FAN module
T° sensor
7
42
MIPS
E
EB
LM 75
T° sensor
FAN 1
7
43
MIPS
E
EB
FAN 2
7
44
MIPS
E
EB
Main NVM
2
/
MIPS
E
X
STM24C128
PNX doesn’t boot (SW cause) 2
53
Stby µP
E
BL
PNX8543
SSB
Display (only 56PFL9954H)
64
MIPS
E
BL / EB
Altera
Display
5
Extra Info
• Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section “5.8 Fault Finding and Repair Tips, 5.8.6
Logging). It’s shown that the loggings which are generated
by the main software keep continuing. In this case
diagnose has to be done via ComPair.
• Error 13 (I2C bus 3 blocked). At the time of release of this
manual, this error was not working as expected. Current
situation: when this error occurs, the TV will constantly
reboot due to the blocked bus. The best way for further
diagnosis here, is to use ComPair.
• Error 15 (PNX8543,PNX5100 doesn’t boot). Indicates
that the main processor/PNX5100 was not able to read his
bootscript. This error will point to a hardware problem
around the PNX8543 (supplies not OK, PNX 8543
completely dead, I2C link between PNX and Stand-by
Processor broken, etc...). When error 15 occurs it is also
possible that I2C1 bus is blocked (NVM). I2C1 can be
indicated in the schematics as follows: SCL-UP-MIPS,
SDA-UP-MIPS, SCL-1, SDA-1, SCL-2 or SDA-2.
Other root causes for this error can be due to hardware
problems from the NVM PNX5100, DDR’s and the
bootscript reading from the PNX5100.
• Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
LAYER 2 error = 16.
• Error 17 (Invertor or Display Supply). Here the status of
the “Power OK” is checked by software, no protection will
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
• Error 18 (1V2-3V3-5V too low). All these supplies are
generated by the DC/DC supply on the SSB. If one of these
supplies is too low, protection occurs and blinking LED
LAYER 1 error = 2 will be displayed automatically. In SDM
this gives LAYER 2 error = 18.
FAN
FAN
•
•
•
•
•
•
•
•
SSB
Error 21 (PNX 5100). When there is no I2C communication
towards the PNX5100, the TV set will start rebooting and
display LAYER 1 error = 2. Disconnect the mains cord now
and start up the TV set with the solder path (SDM) short to
ground during start-up to activate the LAYER 2 error
blinking. Error “21” will be logged and displayed via the
blinking LED procedure after a few moments from start-up.
Remark : the rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section “5.8 Fault Finding and Repair Tips, 5.8.6
Logging”). It is shown that the loggings which are
generated by the main software keep continuing. Check in
the logging for keywords like e.g. “Device error 21”.
Error 23 (HDMI). When there is no I2C communication
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on. It should be noted that in
case a new spare EDID MUX device is used for repair, the
initial default address must be changed from “C0” to “CE”,
to be done via ComPair.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark : this only
works for TV sets with an I2C controlled screen included.
Error 25 (Boot-NVM PNX5100). Same behaviour as
described in “Error 21 (PNX5100)”.
Error 27 (Micronas IF). When there is no I2C
communication towards the multi standard demodulator,
LAYER 2 error = 27 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 28 (ARM ambilight). When there is no I2C
communication towards the ARM processor, LAYER 2
error = 28 will be logged and displayed via the blinking LED
procedure if SDM is switched on.
Error 29 (FPGA local contrast). When there is no I2C
communication towards this FPGA, LAYER 2 error = 29
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner after start-up, LAYER 2 error = 34 will be
2009-May-08
EN 30
•
•
•
•
5.
Q549.2E LA
Service Modes, Error Codes, and Fault Finding
•
logged and displayed via the blinking LED procedure when
SDM is switched on.
Error 42 (Temp sensor). Only applicable for TV sets with
an I2C controlled screen.
Main NVM. When there is no I2C communication towards
the main NVM, LAYER 1 error = 2 will be displayed via the
blinking LED procedure. In SDM, LAYER 2 error will be
blinked as “15”. Errors here can not be logged due to
inaccessibility of the NVM device.
Error 53. This error will indicate that the PNX8543 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
Error 64. Only applicable for TV sets with an I2C controlled
screen .
5.6
The Blinking LED Procedure
5.6.1
Introduction
The blinking LED procedure can be split up into two situations:
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
• Blinking LED procedure LAYER 2 error. Via this procedure,
the contents of the error buffer can be made visible via the
front LED. In this case the error contains 2 digits (see table
“5-2 Error code overview”) and will be displayed when SDM
(hardware pins) is activated. This is especially useful for
fault finding and gives more details regarding the failure of
the defective board.
•
•
•
5.7
Protections
5.7.1
Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
• Protections related to supplies: check of the 12V, +5V,
+3V3 and 1V2.
• Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
Important remark:
For all errors detected by MIPS which are fatal => rebooting of
the TV set (reboot starts after LAYER 1 error blinking), one
should short the solder paths at start-up from the power OFF
state by mains interruption and not via the power button to
trigger the SDM via the hardware pins.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
When one of the blinking LED procedures is activated, the front
LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s
6. The sequence starts again.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence
6. The sequence starts again.
5.6.2
How to Activate
Use one of the following methods:
2009-May-08
Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in “normal operation”
mode or automatically when the error/protection is
monitored by the standby processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether “error devices” are
mentioned. (see section “5.8 Fault Finding and Repair
Tips, 5.8.6 Logging”).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
“normal operation” mode or when SDM (via hardware pins)
is activated when the tv set is in protection.
Important remark:
For all errors detected by MIPS which are fatal =>
rebooting of the TV set (reboot starts after LAYER 1 error
blinking), one should short the solder paths at start-up from
the power OFF state by mains interruption and not via the
power button to trigger the SDM via the hardware pins.
Transmit the commands “MUTE” - “062500” - “OK”
with a normal RC. The complete error buffer is shown.
Take notice that it takes some seconds before the blinking
LED starts.
Transmit the commands “MUTE” - “06250x” - “OK”
with a normal RC (where “x” is a number between 1
and 5). When x = 1 the last detected error is shown, x = 2
the second last error, etc.... Take notice that it takes some
seconds before the blinking LED starts.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section “5.3 Stepwise Start-up”).
5.7.2
Hardware Protections
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D (7D10) and puts the
amplifier in a continuous burst mode (cyclus approximately 2
seconds).
Repair Tip
• There will be still picture available but no sound. While the
Class D amplifier tries to start-up again, the cone of the
Service Modes, Error Codes, and Fault Finding
Important remark regarding the blinking LED indication
As for the blinking LED indication, the blinking led of LAYER 1
error displaying can be switched off by pushing the power
button on the keyboard.
This condition is not valid after the set was unpowered (via
mains interruption). The blinking LED starts again and can only
be switched off by unplugging the mains connection.
This can be explained by the fact that the MIPS can not load
the keyboard functionality from software during the start-up and
doesn’t recognizes the keyboard commands at this time.
5.8
Fault Finding and Repair Tips
Tips
• When an output supply voltage is short-circuited to GND
the corresponding DC-DC converter is not making any
audible noise, the converter switches-off immediately and
will attempt a re-start only after +12V drops and rises
again.
• Check the integrity (at least no short-circuit between drain
and source) of power MOS-FETs, especially the high-side
ones: 7U05, 7U08, 7U0D-1 and 7U0H-1 before starting the
platform in SDM mode, otherwise it can be easily
damaged.
• Switching frequency of DC-DC converters should be
around 290KHz for 12V to 1V2 DC-DC converters and
around 370KHz for 12V to 3V3 and 12V to 5V DC-DC
converters.
Ambilight
Due to degeneration process of the AmbiLights, there can be a
difference in the colour and/or light output of the spare
ambilight module in comparison with the originals ones
contained in the TV set. Via ComPair the light output can be
adjusted.
5.8.2
Audio Amplifier
The Class D-IC 7D10 has a powerpad for cooling. When the IC
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.
5.8.3
5.8.5
CSM
DC/DC Converter
Description
The onboard supply consists of 5 DC/DC converters and 4
linear stabilizers. All DC/DC converters have +12V input
voltage and deliver :
•
•
•
•
•
+1V2-PNX85XX supply voltage (1.24V nominal), stabilized
close to PNX8543 chip.
+1V2-PNX5120 supply voltage (1.26V nominal), stabilized
close to PNX5120 chip.
+3V3 (3.34V nominal, overall 3.3 V for onboard IC’s).
+5V (5.15V nominal) for USB and Conditional Access
Interface and +5V5-TUN for +5V-TUN tuner stabilizer.
+33VTUN (34V nominal) for analog-only tuners.
The linear stabilizers are providing:
•
•
•
•
+1V2-STANDBY (out of +3V3-STANDBY), 1.24V nominal.
+1V8-PNX85XX and +1V8PNX5100 (connected via
CFH1), 1.84V nominal.
+2V5 (WOW FPGA diversity only), 2.5V nominal.
+5V-TUN (out of +5V5-TUN), 5V nominal.
+3V3-STANDY and +1V2-STANDBY are permanent voltages.
Supply voltages +1V2-PNX85XX and +1V2-PNX5100 are
Exit “Factory Mode”
When an “F” is displayed in the screen’s right corner, this
means the set is in “Factory” mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode).
Then push the “SOURCE” button for 10 seconds until the “F”
disappears from the screen.
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)
5.8.4
EN 31
Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power-on via the mains cord,
presuming that the standby microprocessor and the external
supply are operational. Take STANDBY signal high-to-low
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes low) then +1V2-PNX85XX and +1V2PNX5100 are started immediately. Then, after ENABLE-3V3
goes low, all the other supply voltages should rise within 2ms.
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info”.
5.8.1
5.
started immediately when +12V incoming voltage is available
(+12V is enabled by STANDBY signal, active low). Supply
voltages +3V3, 2V5, +1V8-PNX5100, +1V8-PNX85XX, +5V
and +5V-TUN are switched-on directly by signal ENABLE-3V3
(active low), provided that +12V (detected via 7U40 &7U41) is
available. +12V is considered OK (=> DETECT -12V signal
becomes high and 12V/3V3 and 12V/5V DC-DC converter can
be started up) if it rises above 10V5 (typical) and doesn’t drop
below 10V (typical).
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again.
5.7.3
Q549.2E LA
5.8.6
Logging
When something is wrong with the TV set (f.i.the set is
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a “ComPair UART”cable (3138 188 75051) from the service connector in the TV to
the “multi function” jack at the front of ComPair II box.
Required settings in ComPair before starting to log :
- Start up the ComPair application.
- Select the correct database (open file “Q549.2E LA”, this will
set the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. “logging”)
in the “Connection Description” box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the “Display Option Code” (useful when there is no picture),
2009-May-08
EN 32
5.
Q549.2E LA
Service Modes, Error Codes, and Fault Finding
look for item “DisplayRawNumber” in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for “error devices” in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.7
Loudspeakers
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!
EDID4
5.8.8
IPB
In case of no picture when CSM-test pattern from PNX5100 is
activated and backlight doesn’t light up, it’s recommended first
to check the inverter on the IPB + wiring (LAYER 2 error = 17
is displayed in SDM).
5.8.9
18310_220_090318.eps
090319
Tuner
Figure 5-13 4th HDMI EDID NVM pin
Attention: In case the tuner is replaced, always check the tuner
options!
5.8.10 PCI bus
The splash screen image is not distributed via the regular YUV
signal path from the PNX8543 to the PNX51XX, but loaded one
time via the PCI bus.Once the splash screen image is loaded
into the PNX51XX, it will be continuously generated by the
PNX51XX until the first incoming video disables the splash
screen.So when teletext and/or general UI is available, but no
splash screen (option “ON”) is visible during start-up, check the
PCI bus as possible root cause.
5.8.11 Display option code
Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.
5.8.12 Upgrade HDMI EDID NVM
The EDID MUX device (including all HDMI NVM except the 4th)
is upgradeable via USB, see ComPair for further instructions. It
should be noted that in case a new spare EDID MUX device is
used for repair, the initial default address must be changed
from “C0” to “CE”, to be done via ComPair.
5.8.13 Upgrade VGA/4th HDMI EDID NVM
The EDID for VGA connector or the 4th HDMI can only be
upgraded via external I2C. To upgrade the EDID for the VGA
connector or 4th HDMI, pin 7 of the EDID NVM has to be short
circuited to ground. Therefore a test point is foreseen (see
Figure 5-13). For the VGA EDID NVM it’s most suitable to
connect pin 7 to ground on the NVM device itself. See ComPair
for further instructions.
2009-May-08
5.8.14 Wi-Fi module
To prevent damage on the coax wires, especially the female
core of the coax wires (can be bend over during dis- and
reconnecting), this should be carried out by use of pliers.
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 33
5.8.15 SSB Replacement
Follow the instructions in the flowchart in case a SSB has to be
exchanged. See figure “SSB replacement flowchart”.
Instruction note: SSB replacement Q528.x, Q522.x, Q529.x, Q54x.x
START
Set is going into protection after
replacing the SSB
(blinking LED, error 2).
Take care that speakers are connected!
In some sets, the speakers are in the rear
cover, and when the set is switched “on”
without speakers, it is possible that the Audio
protection is triggered.
Advise: remount rear cover before switching
“on” (see also SCC_71772).
Set is still
operating?
No
Create “repair” directory on USB stick and
connect USB stick to TV-set
Go to SAM mode (062596 i+) and
save the TV settings via “Upload to USB”.
- Replace SSB board by a Service SSB.
- Make the SSB fit mechanically to the set.
Start-up set.
Set behaviour?
Set is starting up but no display.
Set is starting up & display is OK.
Set is starting up in “Factory” mode.
Update main software in this step, by using
“autorun.upg” file.
Noisy picture with bands/lines is visible and the
red LED is continuous “on”
(sometimes also the letter “F” is visible).
Program “Display Option” code via 062598
MENU/HOME, followed by 3 digits code (this
code can be found on a sticker inside the set).
Press 5 s. the “Volume minus” button on the local
cntrl until the red LED switches “off”, and then
press 5 s. the MENU (*) button of the local cntrl.
(* in some chassis this button is named SOURCE)
The picture noise is replaced by blue mute!
After entering “Display Option” code, set is
going to Standby (= validation of code).
Unplug the mainscord to verify the correct
disabling of the factory-mode.
Program “Display Option” code via 062598 MENU/
HOME, followed by 3 digits code (this code can be
found on a sticker inside the set).
Restart the set.
No
Saved settings
on USB stick?
After entering “Display Option” code, set is going
to Standby (= validation of code).
Connect PC via ComPair interface to Service
connector.
Yes
Start TV in Jett mode (DVD i+/OSD)
Open ComPair browser Q52x.
Go to SAM mode, and reload settings
via “Download from USB”.
Restart the set.
In case of settings reloaded from USB, the set type,
serial number, Display 12NC, are automatically stored
when entering display options.
Program “set type number”, “serial number”,
and “display 12NC”.
If not already done;
Check latest software on Service website.
Update Main and Standby software via USB.
Check and perform alignments in SAM
according to the Service Manual.
E.g. option codes, colour temperature...
- Check if correct “Display Option” code is
programmed.
- Verify “Option Codes” according sticker inside the set.
- Default settings for White drive ...see Service Manual
Final check of all menus in CSM.
Special attention for HDMI Keys.
END
Q52xE SSB Board swap – v5.1
VDS/JA Updated 18-03-2009
(changes are indicated in red)
H_16771_007.eps
090318
Figure 5-14 SSB replacement flowchart
2009-May-08
EN 34
5.
Q549.2E LA
5.9
Software Upgrading
5.9.1
Introduction
Service Modes, Error Codes, and Fault Finding
5. The renamed “upg” file will be visible and selectable in the
upgrade application.
Back-up Software Upgrade Application
If the default software upgrade application does not start (could
be due to a corrupted boot 2 sector) via the above described
method, try activating the “back-up software upgrade
application”.
How to start the “back-up software upgrade application”
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the “INFO”-button on a Philips remote control or
“CURSOR DOWN” button on a Philips DVD RC-6 remote
control (it is also possible to use a TV remote in “DVD”
mode). Keep the “INFO”-button (or “cursor down” button)
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.
The set software and security keys are stored in a NANDFlash, which is connected to the PNX8543 via the PCI bus.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the DFU.
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
(copy protection keys, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if the HDMI key, MAC address.. are valid.
For the correct order number of a new SSB, always refer to the
Spare Parts list!
5.9.2
5.9.3
In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory “UPGRADES” on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbySW_CFT72_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section “
Manual Software Upgrade”.
5. Select the appropriate file and press the “OK” button to
upgrade.
Main Software Upgrade
•
•
The “UpgradeAll.upg” file is only used in the factory.
The “FlashUtils.upg” file is only used by service centra
which are allowed to do component level repair on the
SSB.
5.9.4
Automatic Software Upgrade
In “normal” conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the “AUTORUN.UPG”
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q5492_ 1.26.15.0_commercial.zip). This can also be done by
the consumers themselves, but they will have to get their
software from the commercial Philips website or via the
Software Update Assistant in the user menu (see eUM). The
“autorun.upg” file must be placed in the root of the USB stick.
How to upgrade:
1. Copy “AUTORUN.UPG” to the root of the USB stick.
2. Insert USB stick in the set while the set is in ON MODE.
The set will restart and the upgrading will start
automatically. As soon as the programming is finished, a
message is shown to remove the USB stick and restart the
set.
Manual Software Upgrade
In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the “OK” button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use
a TV remote in “DVD” mode). Keep the “OK” button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.
Stand-by Software Upgrade via USB
Content and Usage of the One-Zip Software File
Below the content of the One-Zip file is explained, and
instructions on how and when to use it.
•
•
•
•
•
•
•
•
•
•
Attention!
In case the download application has been started manually,
the “autorun.upg” will maybe not be recognized.
What to do in this case:
1. Create a directory “UPGRADES” on the USB stick.
2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.
2009-May-08
•
•
•
BootProm_PNX5120_Q5492_x.x.x.x.zip. A programmed
device can be ordered via the regional Service
organization.
Ceisp2padll_P2PAD_x.x.x.x.zip. Not to be used by
Service technicians. For ComPair development only.
DDC_Q5492_x.x.x.x.zip. Contains the content of the VGA
NVM. See ComPair for further instruction.
EDID_Q5492_x.x.x.x.zip. Contains the EDID content of
the different EDID NVM’s. See ComPair for further
instructions.
EJTAGDownload_Q5492_x.x.x.x.zip. Only used by
service centra which are allowed to do component level
repair.
FUS_Q5492_x.x.x.x_commercial.zip. Contains the
“autorun.upg” which is needed to upgrade the TV main
software and the software download application.
Factory_Q5492_x.x.x.x_commercial.zip. Only for
production purposes, not to be used by Service
technicians.
FlashUtils_Q5492_x.x.x.x_commercial.zip. Not to be
used by Service technicians.
MOP_RAC3_x.x.x.x.zip. Contains the MOP local contrast
software and is upgradeable via USB (UPG). This SW is
not part of the FUS autorun.upg!
OAD_Q5492_x.x.x.x.zip. Not to be used by Service
Technicians.
OpenSourceFile_Q5492_x.x.x.x.zip. Not to be used by
Service technicians.
PQPrivate_Q5492_x.x.x.x.zip. Not to be used by Service
technicians.
StandbySW_CFTxx_x.x.x.x_commercial.zip. Contains
the Stand-by software in “upg” and “hex” format.
– The “StandbySW_xxxxx_prod.upg” file can be used to
upgrade the Stand-by software via USB.
– The “StandbySW_xxxxx.hex” file can be used to
upgrade the Stand-by software via ComPair.
Service Modes, Error Codes, and Fault Finding
Q549.2E LA
5.
EN 35
–
•
•
•
•
•
•
•
5.9.5
Content of the MOP Ambilight ARM SW File
•
5.9.6
The files “StandbySW_xxxxx_exhex.hex” and
“StandbySW_xxxxx_dev.upg” may not be used by
Service technicians (only for development purposes).
UpgradeAll_Q5492_x.x.x.x_commercial.zip. Only for
production purposes, not to be used by Service
technicians.
Caution: Never try to use this file, because it will
overwrite the HDCP keys ! ! !
UpgradeExe_Q5492X_x.x.x.x.zip. Not to be used by
Service Technicians.
Ambilight_Q5492_x.x.x.x.zip. Not to be used by Service
technicians.
Cabinet_Q5492_x.x.x.x.zip. Not to be used by Service
technicians.
Display_Q5492_x.x.x.x.zip. Not to be used by Service
technicians.
LightGuide_TV522_x.x.x.x_.zip. Not to be used by
Service Technicians.
ProcessNVM_Q5492_x.x.x.x.zip. Default NVM content.
Must be programmed via ComPair or can be loaded via
USB, be aware that all alignments stored in NVM are
overwritten here.
MOP_AMBILIGHT_V1-2_UPG_jettsigned.zip. Contains
the MOP ambientlight software (ARM processor on the
DC-DC AL interface board) and is upgradeable via USB
(UPG). This SW is not part of the FUS autorun.upg! and is
not available in the One-Zip software file but provided
separately via the commercial Philips website (software for
servicers only). Instructions for upgrading are included in
the zip file.
UART logging 2K9 (see section “5.8 Fault Finding and
Repair Tips, 5.8.6 Logging)
2009-May-08
EN 36
6.
Q549.2E LA
Alignments
6. Alignments
•
Index of this chapter:
6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 Option Settings
6.5 Reset of Repaired SSB
6.7 Total Overview SAM modes
6.1
General Alignment Conditions
Perform all electrical adjustments under the following
conditions:
• Power supply voltage (depends on region):
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%).
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%).
– EU: 230 VAC / 50 Hz (± 10%).
– LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%).
– US: 120 VAC / 60 Hz (± 10%).
• Connect the set to the mains via an isolation transformer
with low internal resistance.
• Allow the set to warm up for approximately 15 minutes.
• Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heat sinks as ground.
• Test probe: Ri > 10 MΩ, Ci < 20 pF.
• Use an isolated trimmer/screwdriver to perform
alignments.
6.1.1
Alignment Sequence
•
•
•
6.2
First, set the correct options:
– In SAM, select “Options”, and then “Option numbers”.
– Fill in the option settings for “Group 1” and “Group 2”
according to the set sticker (see also paragraph 6.4
Option Settings).
– Press OK on the remote control before the cursor is
moved to the left.
– In submenu “Option numbers” select “Store” and press
OK on the RC.
OR:
– In main menu, select “Store” again and press OK on
the RC.
– Switch the set to Stand-by.
Warming up (>15 minutes).
Hardware Alignments
Not applicable.
6.3
Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error
Codes, and Fault Finding). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
The following items can be aligned:
• Tuner AGC.
• White point.
To store the data:
• Press OK on the RC before the cursor is moved to the
left.
• In main menu select “Store” and press OK on the RC.
• Press MENU on the RC to switch back to the main menu.
• Switch the set to stand-by mode.
For the next alignments, supply the following test signals via a
video generator to the RF input:
2009-May-08
•
•
6.3.1
EU/AP-PAL models: a PAL B/G TV-signal with a signal
strength of at least 1 mV and a frequency of 475.25 MHz
US/AP-NTSC models: an NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25
MHz (channel 3).
LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).
Tuner AGC (RF AGC Take Over Point Adjustment)
Purpose: To keep the tuner output signal constant as the input
signal amplitude varies.
No alignment is necessary, for the AGC alignment you can use
the default value : “80”.
Store settings and exit SAM.
6.3.2
White Point
•
•
Set “Active control” to “Off”.
Choose “TV menu”, “TV Settings” and then “Picture” and
set picture settings as follows:
Picture Setting
Dynamic backlight
Off
Dynamic Contrast
Off
Colour Enhancement
Off
Picture Format
Unscaled
Light Sensor
Off
Brightness
50
Colour
0
Contrast
100
•
Go to the SAM and select “Alignments”-> “White point”.
White point alignment LCD screens:
• Use a 100% white screen as input signal and set the
following values:
– “Colour temperature”: “Normal”.
– All “White point” values to: “127”.
– “Red BL offset” values to “8”.
– “Green BL offset” values to “8”.
In case you have a colour analyser:
• Measure with a calibrated contactless colour analyser in
the centre of the screen. Consequently, the measurement
needs to be done in a dark environment.
• Adjust the correct x,y coordinates (while holding one of the
White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
correct x,y coordinates (see Table 6-1 White D alignment
values). Tolerance: dx: ± 0.004, dy: ± 0.004.
• Repeat this step for the other colour temperatures that
need to be aligned.
• When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
NVM.
• Restore the initial picture settings after the alignments.
Table 6-1 White D alignment values
Value
Cool (11000K )
Normal (9000K)
Warm (6500K)
x
0.270
0.279
0.309
y
0.279
0.287
0.328
If you do not have a colour analyser, you can use the default
values. This is the next best solution. The default values are
average values coming from production.
• Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
Alignments
•
•
•
Table 6-2 White tone default setting
Colour Temp
32"
R
G
37"
Black level
offset
B
R
G
B
R
G
8
Normal
127
95
97
127
121
106
8
Cool
127
100
112
124
127
119
8
8
Warm
127
89
52
127
111
64
8
8
White Tone
Colour Temp
56"
R
G
B
R
G
127
117
111
8
8
Cool
124
124
125
8
8
Warm
127
95
65
8
8
EN 37
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code. For
the power supply there is no difference. Refer to Chapter 2.
Technical Specifications and, Connections.
Black level
offset
Normal
6.
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
See Table 6-3 Option and display code overview for the
options.
Set the RED, GREEN and BLUE default values according
to the values in Table 6-2.
When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
Restore the initial picture settings after the alignments.
White Tone
Q549.2E LA
6.4.5
Option Code Overview
Table 6-3 Option and display code overview
6.4
Option Settings
6.4.1
Introduction
CTN
Options Group 1
Options Group 2
Disp.
code
32PFL9604H/12 08211 35971 18431 45288 30645 47282 00184 00000 181
32PFL9604H/60 08211 35971 18431 45288 30645 47282 00184 00000 181
37PFL9604H/12 08227 35972 18431 45288 30625 47282 00176 00000 161
The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these
PNX5100 ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes.
Notes:
• After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left,
select STORE in the SAM root menu and press OK on the
RC.
• The new option setting is only active after the TV is
switched “off” / “stand-by” and “on” again with the mains
switch (the NVM is then read again).
6.4.2
Dealer Options
For dealer options, in SAM select “Dealer options”.
See Table 6-4 SAM mode overview.
6.4.3
(Service) Options
Select the sub menu's to set the initialisation codes (options) of
the model number via text menus.
See Table 6-4 SAM mode overview.
6.4.4
37PFL9604H/60 08227 35972 18431 45288 30625 47282 00176 00000 161
56PFL9954H/12 08275 33925 18431 45288 30644 47282 00161 00000 180
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!
6.5
Reset of Repaired SSB
A very important issue towards a repaired SSB from a service
repair shop implies the reset of the NVM on the SSB.
A repaired SSB in service should get the service Set type
“00PF0000000000” and Production code “00000000000000”.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool.
In case of a display replacement, reset the “Operation hours
display” to “0”, or to the operation hours of the replacement
display.
New here in this chassis is the “Net TV” functionality. Therefore
the CTN (“set type” item in CSM1) must be filled into the spare
SSB to ensure access to the Net TV portals.
The loading of the CTN can be done via ComPair (Model
number programming).
The reset item (Clear NET TV memory) can be selected via
MENU (or HOME) => Setup => Installation => Clear NET TV
memory (customer preferences stored at provider side will be
reset now).
Opt. No. (Option numbers)
Select this sub menu to set all options at once (expressed in
two long strings of numbers).
An option number (or “option byte”) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set and in Table 6-3
Option and display code overview.
Example: The options sticker gives the following option
numbers:
• 08192 00133 01387 45160
• 12232 04256 00164 00000
2009-May-08
EN 38
6.5.1
6.
Q549.2E LA
Alignments
SSB identification
3. Create a folder "upgrades" in the root of a USB stick (size
> 50 MB) and save the "autorun.upg" file in this "upgrades"
folder. Note: it is possible to rename this file, e.g.
"Q549_SW_version.upg", this in case there are more than
one "autorun.upg" files on your USB stick
4. Plug the prepared USB stick into the TV set, and select the
"autorun" file in the displayed browser on the screen
5. Now the main TV software will be loaded automatically,
supported by a progress bar
6. Set the correct "display code" via "062598-HOME-xxx",
where "xxx" is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of a “Service” SSB is the same as the ordering
number of an initial “factory” SSB.
6.6.2
Due to a possible wrong display option code in the received
Service SSB (NVM), no picture can be available at start-up and
thus no download application will be visible. Here you can
proceed and finalize step by step to load the main TV software
via the UART logging on the PC (for visual feedback).
1. Start-up the TV set, equipped with the Service SSB, and
enable the UART logging on the PC (see for settings 5.8
Fault Finding and Repair Tips 5.8.6 Logging)
2. The TV set will start-up automatically in the download
application if main TV software is not loaded
3. Plug the prepared USB stick into the TV set, press cursor
"Right" to enter the list, and navigate to the "autorun" file in
the UART logging printout via the cursor keys on the
remote control. When the correct file is selected, press
"OK"
4. Press cursor "Down" and "OK" to start the flashing of the
main TV software. Printouts like: "L: 1-100% , V: 1-100%
and P: 1-100%" should be visible now in the UART logging
5. Wait until the message "Operation successful!” is
displayed and remove all inserted media. Restart the TV
set
6. Set the correct "display code" via "062598-HOME-xxx",
where "xxx" is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).
18310_221_090318.eps
090319
Figure 6-1 SSB identification
6.6
Service SSB delivered without main software
loaded
Due to a changed manufacturing process, new Service SSB’s
can be delivered to the warehouse without main TV
software loaded. Below you find the steps to follow when such
an SSB is received.
6.6.1
When a picture is available
6.6.3
1. Mount the Service SSB into the TV set. After start-up,
normally the download application will appear on the
screen.
2. Download the latest main software (FUS) from the
www.p4c.philips.com website.
6.7
When no picture is available
Use of repaired SSBs instead of new
Repaired SSBs on stock will obviously already contain main TV
software. This implies that only a main software upgrade is
required if you use a “repaired” SSB for board swap instead of
a “new” SSB.
Total Overview SAM modes
Table 6-4 SAM mode overview
Main Menu
Sub-menu 1
Sub-menu 2
Hardware Info
A. SW VERSION
e.g. “Q5492_1.26.15.0”
Sub-menu 3
B. Standby processor version e.g. “STDBY_88.68.0.0”
C. Production code
Description
Display TV & Standby SW version and CTN serial
number.
e.g. “See type plate”
Operation hours
Displays the accumulated total of operation hours.TV
switched “on/off” & every 0.5 hours is increase one
Error
Displayed the most recent errors.
Reset error buffer
Alignment
Clears all content in the error buffer.
Tuner AGC
Whitepoint
RF-AGC Take over point adjustment (AGC default
value is 80)
Colour temperature
Normal
Warn
3 different modes of colour temperature can be selected
Cool
White point red
White point green
White point blue
Red black level offset
Green black level offset
2009-May-08
LCD White Point Alignment. For values,
see Table 6-1 White D alignment values.
Alignments
Q549.2E LA
EN 39
Main Menu
Sub-menu 1
Sub-menu 2
Dealer options
Picture mute
Off/On
Select Picture mute On/Off. Picture is muted / not
muted in case no input signal is detected at input
connectors.
Virgin mode
Off/On
Select Virgin mode On/Off. TV starts up / does not
start up (once) with a language selection menu after
the mains switch is turned “on” for the first time (virgin
mode)
Select E-sticker On/Off (USP’s on-screen)
E-sticker
Off/On
Auto store mode
None
Sub-menu 3
6.
Description
PDC/VPS
TXT page
PDC/VPS/TXT
Options
Digital broadcast
Digital features
Display
Video reproduction
DVB
Off/On
Select DVB On/Off
DVB - T installation
Off/On or Country dependent
Select DVB T installation On/Off or by country
DVB - T light
Off/On
Select DVB T light On/Off
DVB - C
Off/On
Select DVB C On/Off
DVB - C installation
Off/On or Country dependent
Select DVB C installation On/Off or by country
Over the air download
Off/On or Country dependent
Select Over the air download On/Off or by country
8 days EPG
Off/On
Select 8 day EPG On/Off
USB
Off/On
Select USB On/Off
Ethernet
Off/On
Select Ethernet On/Off
Wi-Fi
Off/On
Select Wi-Fi On/Off
DLNA
Off/On
Select DLNA On/Off
Online service
Off
Online service is Off
PTP (Picture Transfer Protocol)
Off/On
Select PTP On/Off
Update assistant
Off/On
Select Update assistant On/Off
Internet software update is Off
Internet software update
Off
Screen
180 / LCD Sharp Z3LA13 56"
Displayed the panel code & type model.
LightGuide
Off/On
Select LightGuide On/Off
Display fans
Not present/Present
Select Display fans Present/Not present.
Temperature sensor
Sensor present in display (only for N.A.
21:9)
Temperature LUT
0
N.A
E-box & monitor
Off/On
Select E-box & monitor On/Off
Picture processing
None/PNX5100
Select Picture processing None/PNX5100 (Q549.xE
chassis).
MOP local contrast
Off/On
Select MOP local contrast On/Off
Light sensor
Off/On
Select Light sensor On/Off
Light sensor type
0/1/2/3
Select Light sensor type form 0 to 3 (for difference
styling).
Pixel Plus HD
Select type of picture improvement.
Pixel Plus type
Perfect Pixel HD
Pixel Precise HD
Ambilight
None,
Select type of Ambilight modules use.
2 sided 2/2
For 8400 series only
2 sided 4/4
3 sided 2/3/2
3 sided 4/3/4
3 sided 4/5/4
4 sided 4/3/4/3
Ambilight technology
LED/Future use
Ambilight technology LED is in use.
MOP ambilight
Off/On
Select MOP ambilight On/Off
2009-May-08
EN 40
6.
Main Menu
Q549.2E LA
Alignments
Sub-menu 1
Sub-menu 2
Audio reproduction
Acoustic system
Source selection
EXT1/AV1 type
Sub-menu 3
Description
Cabinet design used for setting dynamic audio parameters.
SCART CVBS RGB LR
Select input source when connected with external
equipment.
CVBS Y/C YPbPr LR
CVBS Y/C YPbPr HV LR
(CVBS) YPbPr LR
EXT2/AV2 type
SCART CVBS RGB LR
Select input source when connected with external
equipment.
CVBS Y/C LR
(CVBS) YPbPr LR
CVBS Y/C LR
EXT3/AV3 type
None
Select input source when connected with external
equipment.
CVBS
CVBS LR
YPbPr
YPbPr LR
YPbPr HV LR
Miscellaneous
Option number
VGA
Off/On
Select VGA On/Off
SIDE I/O
Off/On
Select SIDE I/O On/Off
HDMI 1
Off/On
Select HDMI 1 On/Off
HDMI 2
Off/On
Select HDMI 2 On/Off
HDMI 3
Off/On
Select HDMI 3 On/Off
HDMI 4
Off/On
Select HDMI 4 On/Off
HDMI side
Off/On
Select HDMI side On/Off
HDMI CEC
Off/On
Select HDMI CEC On/Off
HDMI CEC RC passthrough
Off/On
Select HDMI CEC RC passthrough On/Off
HDMI CEC Pixel Plus link
Off/On
Select Pixel Plus link On/Off
Region
Europe/AP-PAL-MULTI/Australia
Select Region/country.
Tuner type
HD1816-MK1/TD1716-MK4/
TD1716-MK3/HD1816-MK2
Select type of Tuner used.
System RC support
Off/On
Select System RC support On/Off.
Embedded user manual
Off/On
Select Embedded user manual On/Off.
Start-up screen
Off/On
Select Start-up screen On/Off.
Wallpaper
Off/On
Select Wallpaper On/Off.
Hotel mode
Off
Hotel mode is Off.
Group 1
e.g. “08192.02181.01387.45160”
The first line (group 1) indicates hardware options 1
to 4.
Group 2
e.g. “10185.12448.00164.00000”
The second line (group 2) indicates software options
5 to 8.
Store
Store after changing.
Initialise NVM
N.A
Store
Select Store in the SAM root menu after making any
changes.
Display information is for development purposes.
Software maintenance
Software events
Display
Clear
Test reboot
Hardware events
Display
Display information is for development purposes.
Clear
Operation hours display
Test setting
Digital info
0003
In case the display must be swapped for repair, you
can reset the ""Display operation hours"" to ""0"". So,
this one does keeps up the lifetime of the display itself (mainly to compensate the degeneration behaviour).
QAM modulation: 64-QAM
Display information is for development purposes.
Symbol rate: 23:29
Original network ID: 12817
Network ID:12817
Transportstream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: -1
Install start frequency
000
Install start frequency from "0" MHz
Install end frequency
999
Install end frequency as 999 MHz
Digital only
Select Digital only or Digital + Analogue before installation.
Default install frequency
Installation
Digital + Analogue
2009-May-08
Alignments
Main Menu
Sub-menu 1
Development file ver- Development 1 file version
sions
Sub-menu 2
Display parameters DISPT 3.26.8.7
Sub-menu 3
Q549.2E LA
6.
EN 41
Description
Display information is for development purposes.
Acoustics parameters ACSTS 3.6.6.5
PQ - PRFPP 1.26.10.4
Ambilight parameters PRFAM 2.6.1.3
Development 2 file version
12NC one zip software
Display information is for development purposes.
Initial main software
NVM version Q5492_0.4.0.0
Flash units SW Q5492_0.26.15.0
Upload to USB
Channel list
Personal settings
To upload several settings from the TV to an USB
stick
Option codes
Display-related alignment
History list
Download from USB
Channel list
Personal settings
To download several settings from the USB stick to
the TV.
Option codes
Display-related alignment
2009-May-08
EN 42
7.
Circuit Descriptions
Q549.2E LA
7. Circuit Descriptions
Main difference with the previous platform is the introduction of
“Net TV” and “CI+”.
Index of this chapter:
7.1 Introduction
7.2 Power Architecture
7.3 Front-End
7.4 HDMI
7.5 Video and Audio Processing - PNX8543
7.6 Common Interface CI+
7.7 Net TV
7.8 Ambi Light
7.1.1
Key components of this chassis are:
• PNX8543 Digital Colour Decoder
• EP3C25F324C7N FPGA (“Local Contrast”)
• HD1816AF Hybrid Tuner
• DRX3926K Demodulator
• TDA9996 HDMI Switch
• TPA3123D2PWP Class D Power Amplifier
• DP83816AVNG PCI ethernet media access controller and
physical layer (MacPhyter-II).
Notes:
• Only new circuits (circuits that are not published recently)
are described.
• Figures can deviate slightly from the actual situation, due
to different set executions.
• For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.
7.1
Implementation
7.1.2
TV543 Architecture Overview
•
For details about the chassis block diagrams refer to
chapter 9. Block Diagrams. An overview of the TV543
architecture can be found in Figure 7-1.
Introduction
The Q549.2E LA chassis (platform name TV543/92) is the
successor of the Q529.1E LA chassis (platform TV522/92).
DDR
16
DDR-II
CY3
DDR-II
32
32
NXP
PNX8543
Hybrid Tuner
Saw
MICRONAS
DRX39xyK
Local
Contrast
H264
USB 2
2.0
0
FLASH
Ethernet
hdmi
hdmi
FHD@120p
FHD@100p
Pixelated Ambi
Spartan
XC3S250E
Led Dimming
SPI
LVDS
hdmi
Mini
PCI (Wifi)
hdmi
Matrix
PCI
8
hdmi
Halo Reduced
HD-NM
FHD 120Hz
Ambient Light
Led Dimming
CA
TDA9996
MUX
PNX5120
2 channel
Audio Amp.
18310_200_090317.eps
090317
Figure 7-1 Architecture of TV543/92 Elite Core platform
2009-May-08
Circuit Descriptions
7.
EN 43
SSB Cell Layout
1CJ0
1M01
1R12
serv
DDR2
DDR2
lvds-rx
CY3
C40
ambi
5100
40x40
1.27
SPO
Lo
Pr
Ro
L
Head
PCI/
XIO
I
²
C
1M36
lvds-tx
1HP0
Pb
1R07
Y
1E50
Scart / YPbPr
1E51
1HE0
vdi
VGA
L/R
1R08
Xilinx
DDR2
GPI
O
uart
pci/xio
R
Left
TDA
10048
STBY
Audio In
USB
Audio
Out
LVDS 2
DDR2
LVDS 1
Right
E
J
T
A
G
1G51
1M59
Scart / YPbPr
1G50
1F02
1
H
0
1
1M71
DDR
CVBS
Tuner
PNX8542/3
TDA
10023
DV in
Y/C
Video
Out
TS in
HDMI B
HDMI A
DDR2
PCI
Wifi
TDA
98XX
DDR
Video
In
GPIO
CA
R
HDMI
MUX
RJ45
L
USB
2.0
HD
MI
1.3
1M20
H
D
M
I
H
D
M
I
CA
H
D
M
I
Class-D
1
7
3
5
1M99
1P00
FLASH
H
D
M
I
DC/DC
1M95
Ethernet
H
D
M
I
7.1.3
Q549.2E LA
18310_201_090317.eps
090317
Figure 7-2 SSB layout cells (top view)
2009-May-08
EN 44
7.2
7.
Circuit Descriptions
Q549.2E LA
Power Architecture
Refer to figure Figure 7-3 for the power architecture of this
platform.
F use
PSU
P la tfo rm
P ow er
12VD isp
V display
LC D
Power-on
SSB
Standby
3V3stby
PNX5100
+3V3 stby
+1V2
BL D IM
*
+1V2-ST AN D BY
Lam p On *
BL D IM
Lam p On
F use
Fuse
+12V
12V
U ndervoltage
detect
Enable-3V3
+1V2
+1V2-PNX85XX
+3V3
+3V3
D ual
D C/D C
Sw itches off
+3V3 and
+5V
Inverter**
Display
+3V3F
+2V5
+2V5
+2V5 (loc.Contr.FPGA)
+1V8
+1V8
+1V8-PNX85XX
2.5V 1%
voltage ref
D etect 2
(12V sense)
Boost control (Opt)
+1V8
Boost conv
.
(opt)
+1V8-PNX5100
+33V
+33V-TUN(analog)
+1V2
+1V2-PN X5100
AN D
24V** Inverter*
Power-OK
+5V
D ual
D C/D C
24 Vs
+5V
+5V
tuner
+5V-T un
+5V-T U N
(+/-12 Vs opt)
Stby P
D etect1
Audio proc
+ C lass D
24V
Am bilight
+3V3 (SSB)
Bolt- on
*: present in inverterless displays
**: present in displays w ith internal inverter
V inverter 4kV*
V backlight 24 V**
18310_202_090317.eps
090317
Figure 7-3 Power Architecture TV543/92 platform
7.2.1
Power Supply Unit
All power supplies are a black box for Service. When defective,
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct
specifications! This part is available in the regular market.
Consult the Service website for the order codes of the boards.
In the TV543 Elite Core platform, for sets up to and including
47", the Integrated Power Board (IPB) - incl. inverter is used.
For sets of 52 " and 56", a conventional PSU (with additional
inverters) is used.
In this manual, no detailed information is available because of
design protection issues.
The output voltages to the chassis are:
• +3V3-STANDBY (standby-mode only)
• +12V (on-mode)
• +Vsnd (+24V) (audio power) (on-mode)
• +24V (bolt-on power) (on-mode)
• IPB: High voltage to the LCD panel (for sets up to and
including 47").
2009-May-08
7.2.2
Diversity
Below find an overview of the different PSUs that are used:
Table 7-1 Supply diversity
Supplier
PSU
Model
LGIT
PLHL-T826A
32"
Input Voltage Range
High Mains (198- 265 Vac)
Delta
DPS-298CP A
37"
High Mains (198- 265 Vac)
Delta
DPS-411AP-3 A
56"
High Mains (198- 265 Vac)
Circuit Descriptions
7.3
Q549.2E LA
7.
EN 45
Front-End
P la tfo rm w ith e m b e d d e d E D ID
The Front-End consist of the following key components:
•
•
•
•
Tuner HD1816AF
SAW filter 36M125
IF demodulator DRX3926K
AGC amplifier UPC3221GV.
E D ID: 2 5 3B
IIC
3B
3B
3B
3B
Below find a block diagram of the front-end application.
I2C-SSB
NXP Hybrid
Tuner
SAW
Filter
4 × HDMI
inputs
CVBS
IF Amplifier
DRX3926K
2nd SIF
PNX8543
TS
18440_211_090227.eps
090227
Figure 7-6 EDID control (embedded EDID)
The delta’s with respect to the use of the TDA9996 as HDMI
multiplexer compared with earlier chassis/platforms are:
• +5V detection mechanism
• Stable clock detection mechanism
• Integrated EDID
• RT control
• HPD control
• TMDS output control
• CEC control
• New hotplug control for PNX8543 for 5th HDMI input
• New EDID structure: EDID stored in TDA9996, therefore
there are no EDID pins on the SSB. Only in the event of a
5th HDMI input, an additional EEPROM is foreseen, as
was implemented in previous platforms.
Figure 7-4 Front-End block diagram
The DRX3926K is a multi-standard demodulator supporting
DVB-C, DVB-T and analogue standards. The demodulated
digital stream is fed into the parallel transport stream data ports
of the PNX8543. The demodulated analogue signal in the form
of CVBS is connected to the analogue video CVBS/Y input
channel, while the SIF is connected via the SSIF2 positive input
port.
HDMI
In this platform, the TDA9996 HDMI multiplexer is
implemented. Only for one HDMI input, a separate EEPROM is
implemented to store the EDID values. For the other HDMI
inputs, the EDID contents are no longer stored in a separate
EEPROM, but directly in the multiplexer. Each input has its own
physical subaddress: the first 253 bytes are common, where
the last 3 bytes define the specific input. The EDID contents
are, at +5V power-up, downloaded to RAM. The following
figures show the HDMI input configuration and EDID control.
DRX
1P 05
H D M IB-R X
D
A
CRX
B
1P02
1P03
BR X
1P04
Some more delta’s compared to the previous PNX85xx are:
• 2 HDMI inputs (A & B)
• HDMI deep colour RGB/YCbCr 4:4:1 10/12 bit detection.
The PNX8543 handles the digital and analogue audio- and
video decoding and processing. The processor is a MIPS32
general purpose CPU and a 8051-based TV controller for
power management and user event handling.
AR X
1P06
Video and Audio Processing - PNX8543
H D M I Side
(optional)
C
Out
TDA9996
HDMI 4
(optional)
7.5
B
H D M IA-R X
E d id
After replacement of the TDA9996 HDMI mux, the default I2C
address should be reprogrammed from C0 to CE, and the
HDMI EDIDs should be reprogrammed as well. Both actions
should be executed via ComPair.
The PNX8543 is the main audio and video processor (or
System-on-Chip) for this platform. It is a member of the
PNX85xx SoC family (described in earlier chassis) with the
addition of the MPEG4 functionality; the separate STi710x
MPEG4 decoder is no longer implemented in this platform.
PNX8543
A
•
1M 96
2 5 3 co m m o nB yte s
+ 1B su ba d d re s o f
S o u rceP h ysica l A d d re ss
+3B fo r inp u t A
+3B fo r inp u t B
+3B fo r inp u t C
+3B fo r inp u t D
18440_214_090227.eps
090227
IF-AGC
I2C-TUNER
7.4
CPU
TDA9996
HDMI 3
(optional)
HDMI 2
For a functional diagram of the PNX8543, refer
to Figure 7-7.
HDMI 1
18440_213_090227.eps
090227
Figure 7-5 HDMI input configuration
2009-May-08
EN 46
7.
Q549.2E LA
Circuit Descriptions
PNX8543x
MEMORY
CONTROLLER
TS in from
channel decoder
MPEG
SYSTEM
PROCESSOR
CI/CA
TS out/in for
PCMCIA
DV-ITU-656
PRIMARY
VIDEO
OUTPUT
LVDS for
flat panel display
(single or dual
channel)
LVDS
DV INPUT
AV-PIP
SUB-PICTURE
VIDEO
DECODER
CVBS, Y/C,
RGB
3D COMB
SECONDARY
VIDEO
OUTPUT
Low-IF
SSIF, LR
DIGITAL IF
MPEG/H.264
VIDEO
DECODER
VIDEO
ENCODER
analog CVBS
AUDIO DACS
analog audio
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DEMOD
AND DECODE
AUDIO DSP
Dual SPDIF
AUDIO OUT
AUDIO IN
I2S
300 MHz
AV-DSP
HDMI
RECEIVER
Dual HDMI
PWM GPIO
x 22
SPDIF
DRAWING
ENGINE
300 MHz
MIPS32 4KEc
CPU
SYSTEM
CONTROLLER
(8051)
I 2C
I2S
IR
ADC
SPI
DMA BLOCK
UART
I2C
GPIO Flash USB 2.0 CA
x 10
PCI 2.2
18440_202_090226.eps
090226
Figure 7-7 PNX8543 functional diagram
7.5.1
Video Subsystem
Refer to Figure 7-8 for the main video interfaces for the
PNX8543 and the video signal flow between blocks and
memory.
2009-May-08
Circuit Descriptions
Q549.2E LA
7.
EN 47
DDR2-SDRAM
PNX8543x
MCU-DDR
A
VCP/PC
VCP_RX
GFX2
CPIPE_
L2QTV
PIP
PC_
UIP
PC_RX
HDMI
Dual HDMI
GFX1
VCP_
WIFD
AFE
(ADC)
HDMI_
RX
DMA BUS
LOW IF
CVBS
RGB
YPbPr
VGA
2D_DE
VCP_
UIP
LVDS_BUF
LVDS_TX
LCD panel
FPD-LVDS1
LCD panel
FPD-LVDS2
main
MBVP_
L2QTV
HDMI_UIP
MBVP_
L2VO1
DV (including
ITU-656)
MBVP_
L2VO2
VIP
(ITU-656)
CPIPE_
L2VO
CVBS/Y
DENC
C
MUX
A
TS
PCMCIA
TSDO
TSDI
CMD
DAC
monitor
CVBS1/Y
DAC
monitor
CVBS2/C
TSI
CAI
MSVD
VMSP
18440_203_090226.eps
090226
Figure 7-8 PNX8543 video flow diagram
The Video Subsystem consist of the following blocks:
• Analogue Front-End (AFE) block
• Video and PC Capture (VPC/PC) pipe
• HDMI Receiver interface
• Memory-Based Video Processor MBVP)
• Video Composition Pipe (CPIPE)
• Memory Based Video Processor (MBVP) VO-1
• Memory Based Video Processor (MBVP) VO-2
• Video Composition Pipe (CPIPE)
• Dual Flat Panel Display-LVDS (FPD-LVDS)
• Digital Encoder (DENC)
• Digital Video VIP
• 2D graphics block.
7.5.2
Audio Subsystem
Refer to Figure 7-9 for the main audio interfaces for the
PNX8543 and the audio signal flow between blocks and
memory.
2009-May-08
EN 48
7.
Circuit Descriptions
Q549.2E LA
DDR2-SDRAM
PNX8543x
MCU
TS-IN
CAI
TM2270
(MPEG, AC-3, MP3
DECODER)
VMSP
XB4
XB1
SPDIF-IN1
SPDIF-IN2
SPDIF-IN
DMA BUS
fast SPDIF
I2S-IN-SD1
I2S-IN-SD2
I2S-IN-SD3
I2S-IN-SD4
SPDIF-Out
SPDIF-OUT
XB2
AI
AO
I2S-IN-WS
I2S-IN-SCK
I2S-IN-OSC
4 × I2S
HDMI
SPDIF
HDMI_RX
I2S
4 × I2S
XB3
4
4 × I2S
4
IF
SSIF
from
XB4
L, R
ADC
ASDEC
DigIF (DEMODULATION
AND DECODING)
SPDIF
APP - AUDIO DSP
(POST PROCESSING)
ADC
I2S-OUT-SD1
I2S-OUT-SD2
I2S-OUT-SD3
I2S-OUT-SD4
I2S-OUT-WS
I2S-OUT-SCK
I2S-OUT-OSC
2
DAC
2
DAC
2
DAC
HP L, R
2
DAC
SCART1 L, R
Main L, R
SCART2 L, R
18440_204_090226.eps
090226
Figure 7-9 PNX8543 audio flow diagram
The Audio Subsystem consist of the following blocks:
• Analogue Audio Front End (AAFE) used to capture
Baseband Audio Inputs and to sample Secondary Sound
IF (SSIF) directly or via Low-IF input
• HDMI Receiver interface block
• SPDIF input block
• Audio Input (AI) block
• Audio Output (AO) block
• Demodulation & Decoding (ASDEC) DSP for decoding all
analogue terrestrial TV sound standards
• Audio Post-Processing (APP) block
• Digital Audio decoder.
7.5.3
Connectivity and Compute Subsystem
Refer to Figure 7-10 for the connectivity and compute
subsystem.
2009-May-08
Circuit Descriptions
Q549.2E LA
7.
EN 49
DDR2-SDRAM
PNX8543x
MCU_DDR
IIC4_DMA
I2C-2
IIC2_DMA
UART-1
IIC3_DMA
UART1
DMA BUS
I2C-3
MIPS
4KEc
DCS-NETWORK
I2C-1
EJTAG
AVDSP
PCI_XIO
PCI/XIO
UART-2
UART2
CAI
USB
CI/CA
USB2.0
I2C-MC
EJTAG
JTAG_MMIO
SYSTEM
CONTROLLER
80C51
UART-3
PWMs
GPIOs
18440_205_090226.eps
090226
Figure 7-10 PNX8543 connectivity and compute subsystem
The Connectivity Subsystem consists of:
• PCI/XIO interface
• USB2.0 interface
• Three 2-wire UARTs
• Four Master/Slave I2C interfaces
• Common Interface/Conditional Access Interface.
keys in the components, unauthorised exchange of these
components will always result in a defective board.
The Computing Subsystem consists of:
• 32-bit MIPS RISC core
• Enhanced JTAG (EJTAG) block inside the MIPS
• JTAG_MMIO blocks
• TV controller
• Audio/Video DSP (AV_DSP)
• Memory Control Unit (MCU).
7.5.4
Service Notice - FLASH RAM / PNX8543 exchange
The FLASH RAM (item 7P10) and/or PNX8543 (item 7H00)
can only be exchanged by an authorised central workshop with
dedicated programming tools. Due to the presence of (CI+)
2009-May-08
EN 50
7.6
7.
Circuit Descriptions
Q549.2E LA
Common Interface CI+
Access Module (CAM) and the Integrated Digital Television
(IDTV). The security mechanisms in CI+ are derived/copied
from POD (with the exception of Out Of Band (OOB) used in
US CA systems). For more information about conventional CA
systems using a CI module, refer to the BJ3.0E L/PA or BL2.xU
Service Manual.
Together with this platform, an extention to the Common
Interface (CI) Conditional Access system is added, called CI+.
CI+ or Common Interface Plus is a specification that extends
the Common Interface (DVB-CI) as described in the digital
broadcasting standard DVB.
The CI+ standard is downwards compatible with the existing CI
standard.
The weakness of the conventional CI module as Conditional
Access system was the absence of a Copy Protection
mechanism, as decrypted content could be sent over the
PCMCIA interface unscrambled. With the CI+ extension, a
form of copy protection is established between the Conditional
tuner
channel
decoder
The following figure shows the implementation of the CI+
Conditional Access system in the TV543 platform.
TS -IN P U T
d em u x
D E S /AE S
d escram b ler
M
Matrix
atrix
d eco d er
M H E G C I+
C A-C TR L
C om m and
interface
MHEG MMI
ap p licatio n
P C I/X IO
C A-M D O
D E S /AE S
scram b ler
C A clien t
T ransport stream
interface
C A-M D I
P N X 8543
Tran sp o rt S tream s
C A-C o n tro l
CAM
(S C )
P ro p rietary C A
scram b ling
C I + S tan d ard ised C C S
scram b ling
18440_221_090227.eps
090227
Figure 7-11 CI+ Conditional Access implementation
7.7
Net TV
In this chassis, a feature that enables access to dedicated
internet pages from a limited group of information suppliers,
7.8
called “Net TV”, is introduced. A separate Wi-Fi module
enables wireless communication with a local network.
Ambi Light
The Ambi Light architecture in this platform has been entirely
renewed. The characteristics are:
• Additional DC/DC board generating 12/16/24 V (optional)
• ARM processor (on DC/DC panel or AL board)
• Low-power LEDs
• SPI interface from ARM to LED drivers
• I2C upgradeable via USB
• Each AL module has a temperature sensor.
2009-May-08
The use of the DC/DC board is optional. In case no DC/DC
board is implemented, the ARM processor is located on one of
the AL boards.
Refer to Figure 7-12 for the Ambi Light architecture.
Circuit Descriptions
Q549.2E LA
7.
EN 51
18310_203_090317.eps
090317
Figure 7-12 Interface between Ambi Light and SSB
The SPI bus is a synchronous serial data link standard that
operates in full duplex mode.
ARM controller
Refer to Figure 7-13 below for signal interfacing to and from the
ARM controller. The ARM controller is located on the DC/DC
board (item no. 7302) or AL panel (item no. 7102).
SD A
SC L
S E L1
S E L2
S da1
Sck
S c l1
P 0. 7
t bd
P 0. 8
M OSI
M A T0.0
AR M
M ISO
M A T1.0
t bd
Tx D
RxD
For debugging purposes, the working principle is given below:
• At startup the controller will read-out matrix data from the
EEPROM devices (via SPI DATA RETURN)
• Before operation, the driver current is set via SPI, with
driver in DC mode
• During normal operation the controller receives RGB-,
configuration-, operation mode- and topology data via I2C
• The controller converts the I2C RGB data via the matrixes
to SPI LED data
• Via data return the controller receives error data (if
applicable).
Also PWM clock and BLANK signals are generated by the
controller. The controller can be reprogrammed via I2C (via
USB). The controller can receive matrix values via I2C, which
will be stored in the EEPROM of each AL module via the SPI
bus. The temperature sensor in each AL module controls the
TEMP line; in case of a too high temperature the controller will
reduce the overall brightness.
SPI C LO C K
SPI LATC H
SPI LATC H 2
(only on dc/dc for aurea)
t bd
Tx d0
t bd
R x d0
P 0. 10
SPI D ATA O U T
PW M C LO C K
SPI D ATA R ETU R N
BLAN K
PR O G
C S EEPR O M
TEM P
7.8.2
LED driver communication (via SPI bus)
18310_204_090318.eps
090318
Refer to Figure 7-14 below for signal interfacing between the
ARM controller and the LED drivers on the AL boards, and the
LED drivers and the EEPROMs on the AL boards.
Figure 7-13 ARM controller interface
Data transfer between ARM processor and LED drivers is
executed by a Serial Peripheral Interface (SPI) bus interface.
ARM
S o ut
S in
LED
D R IV E R
2
S o ut
A m b ilig h t m o d u le N
S in
o ut16
LED
D R IV E R
1
A m b ilig h t m o d u le 2
o ut16
o ut16
Am b ilig h t m o d u le 1
S P I d ata in
7.8.1
LED
D R IV E R
N
S o ut
SPI d ata return
SPI c lo c k (SC LK)
SPI latc h (XLAT )
PR O G (VPR G )
BLAN K
PW M C LO C K ( G SC LK)
18310_205_090318.eps
090318
2009-May-08
EN 52
7.
Q549.2E LA
Circuit Descriptions
Figure 7-14 SPI communication between ARM controller and LED drivers
The ARM controller communicates with the LED drivers (on
each AL module) via an SPI bus. For debugging purposes, the
working principle is given below:
• Data from the ARM controller is linked through the drivers,
which are connected in cascade
• SPI CLK, SPI LATCH, PROG, BLANK and PWM CLOCK
are going directly from the controller to each driver
• SPI DATA RETURN is linked from the last driver to the
controller: controller decides which driver returns data.
7.8.3
Temperature Control
Refer to Figure 7-15 for signal interfacing between the ARM
controller and the temperature sensor on the AL boards.
Am bilight m odule 1
Vcc
Am bilight m odule 2
Vcc
Pull-up
TEMP
SENSOR
Am bilight m odule N
Vcc
Pull-up
TEMP
SENSOR
Pull-up
TEMP
SENSOR
ARM
18310_206_090318.eps
090318
Figure 7-15 Communication between ARM controller and
temperature sensor
Each AL board is equipped with a temperature sensor. If one of
the sensors detects a temperature over the threshold, the
TEMP line is pulled LOW which results in brightness reduction.
2009-May-08
IC Data Sheets
Q549.2E LA
8.
EN 53
8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as “black boxes” in the
8.1
electrical diagrams (with the exception of “memory” and “logic”
ICs).
Diagram SSB: DC/DC B01A, TPS53124PW (IC 7U03)
Block Diagram
Pin Configuration
VBST1
1
28
NC
2
27
LL1
EN1
3
26
DRVL1
PGND1
DRVH1
4
25
5
24
TRIP1
NC
6
23
VIN
22
VREG5
GND
7
TEST1
8
NC
9
TPS53124
VO1
VFB1
21
V5FILT
20
TEST2
TRIP2
VFB2
10
19
VO2
11
18
PGND2
EN2
12
17
DRVL2
NC
13
16
LL2
VBST2
14
15
DRVH2
18250_300_090319.eps
090319
Figure 8-1 Internal block diagram and pin configuration
2009-May-08
EN 54
8.2
8.
IC Data Sheets
Q549.2E LA
Diagram SSB: Front End B02B, DRX3926K (IC 7T50)
Block Diagram
RF AGC
DVB-T/QAM
FEC
IF AGC
SAW
Main
Tuner
IF AMP
ADC
DVB-T/QAM/ATV
Demodulator
DAC
Stereo Decoder
Integrated Tuner
DAC
MPEG-2
TS
CVBS
SIF
I2S Audio
Presaw
Sense
I2C
I2 C
System Controller
GPIO
Pin Configuration
VSSAH_CVBS
INP
VDDAH_CVBS
INN
CVBS
VSSAH_AFE1
SIF
VDDAH_AFE1
VSSAL_AFE2
VDDAL_AFE1
VDDAL_AFE2
VSSAL_AFE1
PDP
IF_AGC
PDN
RF_AGC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XI
49
32
RSTN
XO
50
31
SAW_SW
VSSAH_OSC
51
30
GPIO2
VDDAH_OSC
52
29
VSYNC
VDDH
53
28
VSSL
VSSH
54
27
VDDL
VSSL
55
26
VDDH
VDDL
56
25
VSSH
TDO
57
TMS
DRXK
24
I2C_SDA1
58
23
I2C_SCL1
TCK
59
22
MD7
TDI
60
21
MD6
I2C_SDA2
61
20
MD5
I2C_SCL2
62
19
MD4
I2S_CL
63
18
VDDH
I2S_DA
64
17
VSSH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
I2S_WS
VDDL
VDDL
VSSL
VSSL
MD3
GPIO1
MD2
MSTRT
MD1
MERR
MD0
VSSH
VDDH
MVAL
MCLK
Figure 8-2 Pin configuration
2009-May-08
18440_300_090303.eps
090303
IC Data Sheets
8.3
Q549.2E LA
8.
EN 55
Diagram SSB: PNX8543 - Stand-by Controller B04A, PNX8543 (IC7H00)
Block Diagram
PNX8543x
MEMORY
CONTROLLER
TS in from
channel decoder
MPEG
SYSTEM
PROCESSOR
CI/CA
TS out/in for
PCMCIA
DV-ITU-656
PRIMARY
VIDEO
OUTPUT
LVDS for
flat panel display
(single or dual
channel)
LVDS
DV INPUT
AV-PIP
SUB-PICTURE
VIDEO
DECODER
CVBS, Y/C,
RGB
3D COMB
SECONDARY
VIDEO
OUTPUT
Low-IF
SSIF, LR
DIGITAL IF
MPEG/H.264
VIDEO
DECODER
VIDEO
ENCODER
analog CVBS
AUDIO DACS
analog audio
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DEMOD
AND DECODE
AUDIO DSP
Dual SPDIF
I2S
AUDIO OUT
AUDIO IN
I2S
SPDIF
300 MHz
AV-DSP
HDMI
RECEIVER
Dual HDMI
DRAWING
ENGINE
300 MHz
MIPS32 4KEc
CPU
SYSTEM
CONTROLLER
(8051)
I2C
PWM GPIO
x 22
IR
ADC
SPI
DMA BLOCK
UART
I2C
GPIO Flash USB 2.0 CA
x 10
PCI 2.2
Pin Configuration
ball A1
index area
2
1
B
D
F
H
K
M
P
T
V
Y
AB
AD
AF
AH
AK
AM
AP
4
3
6
5
7
8 10 12 14 16 18 20 22 24 26 28 30 32 34
9 11 13 15 17 19 21 23 25 27 29 31 33
A
C
E
G
J
L
PNX8543xEH
N
R
U
W
AA
AC
AE
AG
AJ
AL
AN
Transparent top view
18440_301_090303.eps
090303
Figure 8-3 Internal block diagram and pin configuration
2009-May-08
EN 56
8.4
8.
Q549.2E LA
IC Data Sheets
Diagram SSB: Ethernet B05A, PNX5120 (IC7C00)
Block Diagram
PNX51xx
MEMORY
CONTROLLER
TM327x 1
LVDS RX 1
GIC 1
UIP L3K7
Video
TM327x 2
GIC 2
LVDS RX 2
TM327x 3
GIC 3
PCI/XIO
LVDS TX 1
Video
I2C
LVDS TX 2
I2C-DMA
I2C
CPIPE L3K7
GFX
LVDS TX 3
LVDS TX 4
UART
UART
16 X GPIO
EJTAG
CLOCK
CAB
AUDIO IN
AUDIO OUT
Pin Configuration
ball A1
index area
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
PNX51xx
Transparent top view
18560_300_090403.eps
090403
Figure 8-4 Internal block diagram and pin configuration
2009-May-08
IC Data Sheets
8.
EN 57
Diagram SSB: Ethernet B07G, DP83816 (IC7N04)
Pin Configuration
NC
VSS
NC
AUXVDD
VSS
TXCLK
TXEN
C RS
COL/MA16
AUXVDD
VSS
TXD3/MA15
TXD2/MA14
TXD1/MA13
TXD0/MA12
AUXVDD
VSS
C1
X2
X1
VSS
RXDV/MA11
RXER/MA10
RXOE
RXD3/MA9
RXD2/MA8
RXD1/MA7
AUXVDD
VSS
RXD0/MA6
RXCLK
M DC
MDIO
M A5
MA4/EECLK
MA3/EEDI
Block Diagram
TPTDP/M
RAM
BIST
Logic
SRAM
RXFilter
.5 KB
Test data in
MII TX
SRAM
RX-2 KB
Test data out
25 MHz Clk
MII RX
MII Mgt
3V DSP Physical Layer
Interface
Logic
BROM/EE
MII TX
MII Mgt
MII RX
R x A ddr
Rx wr data
Tx Addr
Tx wr data
Rx rd data
Tx rd data
SRAM
TX-2 KB
PCI CLK
MAC/BIU
BIOS ROM Cntl
BIOS ROM Data
EEPROM/LEDs
NC
VSS
IAUXVDD
VREF
RESERVED
NC
NC
VSS
TPRDM
TPRDP
IAUXVDD
REGEN
VSS
RESERVED
VSS
VSS
TPTDM
TPTDP
VSS
AUXVDD
VSS
AUXVDD
PMEN/CLKRUNN
PCICLK
INTAN
RSTN
GNTN
REQN
VSS
AD31
AD30
AD29
PCIVDD
AD28
AD27
AD26
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin1
Identification
DP83816
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MA2/LED100N
MA1/LED10N
MA0/LEDACTN
MD7
MD6
MD5
MD4/EEDO
AUXVDD
VSS
MD3
MD2
MD1/CFGDISN
MD0
MWRN
MRDN
MCSN
EESEL
RESERVED
NC
NC
NC
PWRGOOD
3VAUX
AD0
AD1
AD2
AD3
PCIVDD
AD4
AD5
VSS
AD6
AD7
CBEN0
AD8
AD9
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
PCI CNTL
MII RX
MII TX
MII Mgt
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TPRDP/M
PCI AD
DP83816
AD25
AD24
CBEN3
IDSEL
VSS
AD23
AD22
PCIVDD
AD21
AD20
AD19
NC
NC
AD18
AD17
AD16
CBEN2
VSS
FRAMEN
IRDYN
TRDYN
PCIVDD
DEVSELN
STOPN
PERRN
SERRN
PAR
CBEN1
AD15
AD14
VSS
AD13
AD12
AD11
PCIVDD
AD10
8.5
Q549.2E LA
F_15710_167.eps
230905
Figure 8-5 Internal block diagram and pin configuration
2009-May-08
EN 58
8.6
8.
IC Data Sheets
Q549.2E LA
Diagram SSB: Audio B10A, TPA3123D (IC 7D10)
Block Diagram
1 F
0.22 F
LIN
BSR
RIN
ROUT
1 F
22 H
0.68 F
PGNDR
0.68 F
PGNDL
1 F
470 F
LOUT
BYPASS
AGND
22 H
BSL
470 F
0.22 F
PVCCL
AVCC
PVCCR
VCLAMP
Shutdown
Control
SD
1 F
MUTE
}
GAIN0
GAIN1
Control
Pin Configuration
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
TERMINAL
24-PIN
(PWP)
I/O/P
DESCRIPTION
SD
2
I
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
AVCC
RIN
6
I
Audio input for right channel
LIN
5
I
Audio input for left channel
GAIN0
18
I
Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1
17
I
Gain select most-significant bit. TTL logic levels with compliance to AVCC
MUTE
4
I
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
outputs enabled). TTL logic levels with compliance to AVCC
BSL
21
I/O
PVCCL
1, 3
P
22
O
Class-D 1/2-H-bridge positive output for left channel
23, 24
P
Power ground for left-channel H-bridge
NAME
LOUT
PGNDL
VCLAMP
11
P
BSR
16
I/O
ROUT
Bootstrap I/O for left channel
Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
Internally generated voltage supply for bootstrap capacitors
Bootstrap I/O for right channel
15
O
Class-D 1/2-H-bridge negative output for right channel
PGNDR
13, 14
P
Power ground for right-channel H-bridge.
PVCCR
10, 12
P
Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND
9
P
Analog ground for digital/analog cells in core
AGND
8
P
Analog ground for analog cells in core
BYPASS
AVCC
Thermal pad
O
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.
19, 20
P
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Die pad
P
Connect to ground. Thermal pad should be soldered down on all applications to properly
secure device to printed wiring board.
7
18440_302_090303.eps
090303
Figure 8-6 Internal block diagram and pin configuration
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 59
9. Block Diagrams
Wiring Diagram 32" (Elite Core)
WIRING DIAGRAM 32" (ELITE CORE)
WIFI ANTENNA
WIFI ANTENNA
(1044)
(1043)
LCD DISPLAY (1004)
8684
TO
BACKLIGHT
1G50 (B05C)
41. N.C
40. TXDAT39.TXDAT
...
...
...
3. TX2E+
2. SCL-DISP
1. SDA-DISP
8151
SCL-AMBI-3V3
GND
SDA-AMBI-3V3
GND
GND
+3V3
GND
8159
1M59 (B06A)
8319
8316
1M85 (AL4)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
1.
2.
3.
4.
5.
6.
7.
TO
BACKLIGHT
8150
1M83 (AL1)
1. SCL
2. SPI-DATA-IN
3. SDA
4. CONTROL-1
5. CONTROL-2
6. +3V3
7. BLANK
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
1G51 (B05C)
51. N.C.
50. SDA-DISP
49. SCL-DISP
...
...
...
3. +VDISP1
2. +VDISP1
1. +VDISP1
CN4
AMBI-LIGHT MODULE
5/5 (1076)
+5V
KEYBOARD
LED1
+3V3-STANDBY
LED2
RC
GND
LIGHT-SENSOR
AL
RIGHT-SPEAKER
GND-AUDIO
GND-AUDIO
LEFT-SPEAKER
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
4.
3.
2.
1.
1735 (B10A)
1M99 (B01B)
12. GND
11. SDA-SET
10. SCL-SET
9. POWER-OK
8. BACKLIGHT-PWM...
7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT
5. LAMP-ON-OUT
4. GND
3. GND
2. +12VD
1. +12VD
1. N
2. L
CN1
8399
12. NC
11. NC
10. NC
9. INV_OK
8. A/P_DIM
7. BOOST
6. DIM
5. BL_ON_OFF
4. GND1
3. GND1
2. +12V
1. +12V
(1011)
1M95 (B01B)
11. N.C
10. GND
9. +AUDIO-POWER
8. +12V
7. +12V
6. +12V
5. GND
4. GND
3. GND
2. STANDBY
1. +3V3-STANDBY
CN5
AL
8735
8735
8408
- +
- +
INLET
8120
(1127)
AMBI-LIGHT MODULE
5/5 (1074)
(1050)
SSB
1M20 (B01B)
8.
7.
6.
5.
4.
3.
2.
1.
8395
11. NC
10. GND_SND
9. +VSND
8. +12V
7. +12V
6. +12V
5. GND1
4. GND1
3. GND1
2. STANDBY
1. 3V3_ST
MAIN POWER SUPPLY
IPB 32 PLHL-T826A
3P
1M01
KEYBOARD CONTROL
(1042)
B
124P
WIFI
MODULE
ON 1A01
1A01
6. GND
5. +24V
4. GND
3. +24V
2. GND
1. +24V
CN7
1319
1. HV2
2. N.C.
3. HV2
1316
1. HV1
2. N.C.
3. HV1
8159
RIGHT SPEAKER
LEFT SPEAKER
(5213)
(5214)
8101
Board Level Repair
IR LED PANEL
(1112)
1M01
1M20
3P
8P
Component Level Repair
Only For Authorized Workshop
18310_400_090305.eps
090421
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 60
Wiring Diagram 37" (Elite Core)
WIRING DIAGRAM 37" (ELITE CORE)
WIFI ANTENNA
WIFI ANTENNA
(1044)
(1043)
8802
8802
1M83 (AL1)
1M84 (AL1)
1. SCL
2. GND
3. SDA
4. CONTROL-1
5. CONTROL-2
6. +3V3
7. GND
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
8684
LCD DISPLAY (1004)
TO
BACKLIGHT
TO
BACKLIGHT
8319
(1042)
DC-DC
INTERFACE
B
SSB
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
(1150)
124P
WIFI
MODULE
ON 1A01
1A01
1M90 (AB1)
6. GND
5. +24V
4. GND
3. +24V
2. GND
1. +24V
1M59 (AB1)
7. GND
6. +3V3
5. CONTROL2
4. CONTROL1
3. SDA
2. GND
1. SCL
6. GND
5. +24V
4. GND
3. +24V
2. GND
1. +24V
CN7
1319
1. HV2
2. N.C.
3. HV2
1316
1. HV1
2. N.C.
3. HV1
AL
AB
AL
51. N.C.
50. SDA-DISP
49. SCL-DISP
...
...
...
3. +VDISP1
2. +VDISP1
1. +VDISP1
(1028)
1M83 (AL1)
CN5
12. NC
11. NC
10. NC
9. INV_OK
8. A/P_DIM
7. BOOST
6. DIM
5. BL_ON_OFF
4. GND1
3. GND1
2. +12V
1. +12V
1M95 (B01B)
11. N.C
10. GND
9. +AUDIO-POWER
8. +12V
7. +12V
6. +12V
5. GND
4. GND
3. GND
2. STANDBY
1. +3V3-STANDBY
8395
12. GND
11. SDA-SET
10. SCL-SET
9. POWER-OK
8. BACKLIGHT-PWM...
7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT
5. LAMP-ON-OUT
4. GND
3. GND
2. +12VD
1. +12VD
8399
1. N
2. L
CN1
AMBI-LIGHT MODULE
3/3 (1073)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
8585
8735
8408
8735
-+
1M84 (AL1)
1M99 (B01B)
FUSE
-+
+5V
KEYBOARD
LED1
+3V3-STANDBY
LED2
RC
GND
LIGHT-SENSOR
AMBI-LIGHT MODULE
3/3 (1076)
1. SCL
2. GND
3. SDA
4. CONTROL-1
5. CONTROL-2
6. +3V3
7. GND
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
8.
7.
6.
5.
4.
3.
2.
1.
INLET
-+
-+
8120
AL
(1050)
1M20 (B01B)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BUF
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH1CONN
3. SPI-DATA-RETURN
2. SPI-CLOCK-BUF
1. SPI-LATCH2CONN
4. RIGHT-SPEAKER
3. GND-AUDIO
2. GND-AUDIO
1. LEFT-SPEAKER
MAIN POWER SUPPLY
IPB DPS-298CPA B
1M84 (AB1)
8584
11. NC
10. GND_SND
9. +VSND
8. +12V
7. +12V
6. +12V
5. GND1
4. GND1
3. GND1
2. STANDBY
1. 3V3_ST
1735 (B10A)
8584
CN4
AL
KEYBOARD CONTROL
(1114)
SCL-AMBI-3V3
GND
SDA-AMBI-3V3
GND
GND
+3V3
GND
1G51 (B05C)
8151
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. SPI-LATCH
5. PWM-CLOCK-BUF
6. +3V3
7. BLANK-BU
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
3P
AMBI-LIGHT MODULE
3/3 (1075)
8590
1M84 (AL1)
1M01
41. N.C
40. TXDAT39.TXDAT
...
...
...
3. TX2E+
2. SCL-DISP
1. SDA-DISP
1M59 (B06A)
8316
1G50 (B05C)
8150
1.
2.
3.
4.
5.
6.
7.
AMBI-LIGHT MODULE
3/3 (1074)
8159
1M84 (AL1)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. SPI-LATCH
5. PWM-CLOCK-BUF
6. +3V3
7. BLANK-BU
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
RIGHT SPEAKER
(5214)
LEFT SPEAKER
(5213)
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
8101
Board Level Repair
TWEETER
TWEETER
IR LED PANEL
(1112)
Component Level Repair
Only For Authorized Workshop
1M01
1M20
3P
8P
18310_401_090305.eps
090420
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 61
Wiring Diagram 56" (Elite Core)
WIRING DIAGRAM 56" (ELITE CORE)
8583
8586
8587
AMBI-LIGHT MOD.
3/3 (1074)
8588
Component Level Repair
Only For Authorized Workshop
AMBI-LIGHT MOD.
4/4 (1072)
8589
8590
8801
8802
Board Level Repair
AL
CN2
CN1
CN3
41P
51P
5P
SCL-AMBI-3V3
GND
SDA-AMBI-3V3
GND
GND
+3V3
GND
AL
1.
2.
3.
4.
5.
6.
7.
SSB
(1011)
1M20 (B01B)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BUF
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH1CONN
3. SPI-DATA-RETURN
2. SPI-CLOCK-BUF
1. SPI-LATCH2CONN
8.
7.
6.
5.
4.
3.
2.
1.
8683
1M84 (AB1)
+5V
KEYBOARD
LED1
+3V3-STANDBY
LED2
RC
GND
LIGHT-SENSOR
1M84 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
1M95 (B01B)
1M99 (B01B)
12. GND
11. SDA-SET
10. SCL-SET
9. POWER-OK
8. BACKLIGHT-PWM...
7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT
5. LAMP-ON-OUT
4. GND
3. GND
2. +12VD
1. +12VD
8399
1. N
2. L
AMBI-LIGHT MODULE
3/3 (1071)
8395
11. N.C
10. GND
9. +AUDIO-POWER
8. +12V
7. +12V
6. +12V
5. GND
4. GND
3. GND
2. STANDBY
1. +3V3-STANDBY
4. RIGHT-SPEAKER
3. GND-AUDIO
2. GND-AUDIO
1. LEFT-SPEAKER
12. GND1
11. I2C_DATA
10. I2C_CLK
9. INV_OK
8. A/P_DIM
7. BOOST
6. DIM
5. BL_ON_OFF
4. GND1
3. GND1
2. +12V
1. +12V
CN1
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
(1028)
CN5
AMBI-LIGHT MODULE
3/3 (1082)
(1042)
DC-DC
INTERFACE
FUSE
8585
8408
8735
-+
-+
-+
AL
8735
AL
1M84 (AL1)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. SPI-LATCH
5. PWM-CLOCK-BUF
6. +3V3
7. BLANK-BU
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
1M59 (AB1)
6. GND
5. +24V
4. GND
3. +24V
2. GND
1. +24V
1M90 (AB1)
11. NC
10. GND_SND
9. +VSND
8. +12V
7. +12V
6. +12V
5. GND1
4. GND1
3. GND1
2. STANDBY
1. 3V3_ST
7. GND
6. +3V3
5. CONTROL2
4. CONTROL1
3. SDA
2. GND
1. SCL
CN7
6. GND1
5. +24V
4. GND1
3. +24V
2. GND1
1. +24V
AB
CN4
12. N.C.
11. N.C.
10. GND3
9. GND3
8. GND3
7. GND3
6. GND3
5. 24Vinv
4. 24Vinv
3. 24Vinv
2. 24Vinv
1. 24Vinv
B
1735 (B10A)
8584
(1050)
CN3 / 1316
WIFI
MODULE
ON 1A01
8120
(1127)
KEYBOARD CONTROL
5. GND1
4. GND1
3. N.C.
2. +12V
1. +12V
3P
1M01
CN9
MAIN POWER SUPPLY
PSU DPS-411AP3A B
1G51 (B05C)
51. N.C.
50. SDA-DISP
49. SCL-DISP
...
...
...
3. +VDISP1
2. +VDISP1
1. +VDISP1
8151
124P
8316
AL
8690
1M59 (B06A)
1G50 (B05C)
41. N.C
40. TXDAT39.TXDAT
...
...
...
3. TX2E+
2. SCL-DISP
1. SDA-DISP
1A01
AMBI-LIGHT MODULE
4/4(1075)
8159
CN2 / 1319
1. SCL
2. GND
3. SDA
4. CONTROL-1
5. CONTROL-2
6. +3V3
7. GND
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
AMBI-LIGHT MODULE
4/4 (1070)
8303
8150
1M83 (AL1)
-+
INLET
LEFT SPEAKER
RIGHT SPEAKER
1M09
1M20
1M01
4P
3P
8P
(5213)
(5214)
8109
IR LED PANEL (1047)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
TO
BACKLIGHT
8319
1M85 (AL4)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. SPI-LATCH
5. PWM-CLOCK-BUF
6. +3V3
7. BLANK-BU
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
1M85 (AL4)
LCD DISPLAY (1004)
TO
BACKLIGHT
14. PDIM_Select
13. PWM
12. On/Off
11. Vbri
10. GND3
9. GND3
8. GND3
7. GND3
6. GND3
5. 24Vinv
4. 24Vinv
3. 24Vinv
2. 24Vinv
1. 24Vinv
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
AL
1M85 (AL4)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
AMBI-LIGHT MOD.
3/3 (1076)
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
AL
WIFI ANTENNA (1043)
1M84 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
AMBI-LIGHT MOD.
3/3 (1080)
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
AL
1M84 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
AMBI-LIGHT MOD.
4/4 (1073)
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
AL
1M84 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
1. SCL
2. GND
3. SDA
4. CONTROL-1
5. CONTROL-2
6. +3V3
7. GND
8. EEPROM-CS
9. TEMP-SENSOR
10. PROG
11. VLED1
12. GND
13. VLED2
14. GND
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
1M83 (AL1)
1M85 (AL4)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. BLANK-BU
6. +3V3
5. PWM-CLOCK-BUF
4. SPI-LATCH
3. SPI-DATA-RETURN
2. SPI-DATA-OUT
1. SPI-CLOCK-BUF
WIFI ANTENNA (1044)
TWEETER
(5216)
1P09
4P
L
LIGHT STRIP
(1046)
TWEETER
(5215)
1M83 (AL1)
14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
4. CONTROL-1
3. SDA
2. GND
1. SCL
8101
18310_407_090420.eps
090508
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 62
Block Diagram Video
VIDEO
B07A
FRONT-END
CI: PCMCIA CONNECTOR
B04
7P15-7P16
74LVC245APW
20
1P00
B06G
PNX8543:
B04N VIDEO STREAMS
MDO(0-7)
CA-MDO(0-7)
BUFFER
17
DEMODULATOR
7T50
DRX3926K
B-IF-_N-IF-
2T19
10
TUN-P10
9T21
B-IF+_N-IF+
2T20
+5V-TUN
PDP
3T53
47
PDN
3T55
48
SIF
CVBS
5
7
4
3
6
SAW 36M125
40
49
AGC CONTROL
50
IF-AGC
+5V-TUN
3 TUN-P3 9T20
34
33
RF-AGC
B08A
7E02
74HC4053PW
16
MDX
3
DRX2DRX1+
19
18
4
6
7
1E01
DRXC+
12
DRXC-
1
1
2
CRX2+
16
3
CRX2CRX1+
20
19
18
ANALOGUE EXTERNALS B
Y_CVBS-MON-OUT-SC
A3
Y-CVBS-MON-OUT
AV1_STATUS
9EA3
AV1-PR
J2
7
AV1-B
9EA1
AV1-PB
L2
B08D
N2
9
10
BRXC+
12
BRXC-
SCART1
7
J3
11
AV3-Y
N3
20
AV2-Y_CVBS
H1
11
7E14
16
AV2-BLK
8
AV2-STATUS
21
SCART2
ARX2ARX1+
B08B
9
10
ARXC+
12
ARXC-
AI41
VDDA_3V3_ADAC
AI23
VDD_3V3_LVDS
AI33
VDDA_HDMI_3V3_BIAS
AI13
VDD_3V3_SBPER
AI42
VDD_1V2_CORE
VDD_1V2_SBCORE
VDD_3V3_PER
VDD_1V8_DDR
1
R-VGA
2
G-VGA
3
13
14
B-VGA
H-SYNC-VGA
K4
PC3_AI3
P4
PC1_AI3
M4
PC2_AI3
T1
HSYNCIN
T2
VSYNCIN
AJ6
11
DRX2+
CRX2CRX1+
71
69
89
87
DRX2DRX1+
CRX1CRX0+
68
66
86
84
DRX1DRX0+
HDMI
SWITCH
CRX0-
65
83
DRX0-
CRXC+
63
81
DRXC+
CRXCBRX2+
62
42
80
DRXC-
V-SYNC-VGA
BRX2BRX1+
41
39
BRX1BRX0+
39
36
BRX0-
35
BRXC+
33
BRXCARX2+
32
23
ARX2ARX1+
22
20
ARX1ARX0+
19
17
ARX0-
16
ARXC+
14
ARXC-
13
AV4-PB
2
C_+
3
C_99
D0_+
100
D0_96
D1_+
D1_D2_+
D2_-
+1V8-PNX85XX
+3V3
AV4-Y
P1
H2
FRONT-Y_CVBS
FRONT-C
1
2
19
18
HDMI 4
CONNECTOR
4
6
7
PNX5100: SDRAM
PNX5100-DDR2-VREF-CTRL
7C01
EDE5116AJBG-8E-E
(0-12)
D
PNX5100-DDR2-D(0-15)
DDR2
SDRAM
J1
VDDL
J2
VREF
+1V8-PNX5100
PNX5100-DDR2VREF-DDR
USB_RPU
PC3_AI1
PNX5100-DDR2-A(0-12)
DDR2
SDRAM
J1
VDDL
J2
VREF
+1V8-PNX5100
PNX5100-DDR2VREF-DDR
1V8-PMNX85XX
USB CONNECTOR
AL16
USB_VBUS
USB-OC
1P07
1
AN16
USB20-DM
USB20-DP
AP16
AM17
3H37
AN17
3H45
2
3
4
USB 2.0
CONNECTOR SIDE
SW UPLOAD
JPEG
MP3
+3V3-PER
+3V3-PER
PC1_AI1
PNX8543: FLASH
B04F CONTROL
PC2_AI1
7P10
NAND01GW3B2BN6F
PCI-AD24<->NAND-AD
NAND
FLASH
1G
AI43
VCC
12,37
+3V3-NAND
3
SVHS IN 5
2
B07E
B04G
4
B04H DIGITAL VIDEO IN
HDMI SWITCH
HDMIB-RXC+
HDMIB-RXCHDMIB-RX0+
HDMIB-RX0HDMIB-RX1+
HDMIB-RX1-
97
93
HDMIB-RX2+
94
HDMIB-RX23HK0
B04G SDRAM
M_IREF
M_VREF
A14
HDMI_RXC_B_N
A15
HDMI_RXC_B_P
B13
HDMI_RX0_B_N
B14
HDMI_RX0_B_P
A12
HDMI_RX1_B_N
A13
HDMI_RX1_B_P
B11
HDMI_RX2_B_N
B12
HDMI_RX2_B_P
C16
HDMI_RREF
AA31
AB32
PNX8543: SDRAM
3HJ5
+1V8-PNX85XX
DDR2-VREF-CTRL
7HG0
EDE1116AEBG
(0-12)
DQ
DDR2-D(0-15)
DDR2
SDRAM
J1
VDDL
J2
VREF
+1V8-PNX85XX
DDR2-VREF-DDR
7HG1
EDE1116AEBG
1P06
3
P24
+3V3-PER
AG30
HDMI SWITCH
1
+1V2-PNX5100-CLOCK
+3V3-PNX5100-CLOCK
1V2-STANDBY
AJ21
G1 AI54
RREF-PNX85XX
B07E
+3V3-PNX5100-LVDS-PLL
+5V
PCI_AD
1
+1V2-PNX5100-LVDS-PLL
+1V2-PNX85XX
AF5
1E11
1E14
+1V2-PNX-TRI-PLL3
+1V2-PNX5100-DLL
+3V3-PNX5100-DDR-PLL0
+3V3-STANDBY
AJ12
ANALOGUE EXTERNALS C
SIDE
I/O
+1V2-PNX-TRI-PLL2
RREF-PNX85XX
AC6
B07F
Y
+3V3
REF-3V3
M1
9FG8
9FG9
9FGA
9FGB
9FGC
9FGD
VDDA-LVDS
F16
1E04
CVBS
8,45,91,24,
75,95
VDDx_1V8
4
VDDO_3V3
46,55
VDDx_3V3
15,21,34,40,
64,70,85,88
VDDH_3V3
K1
AV4-PR
EXT 3
B08C
+3V3-PNX5100-LVDS-IN
+1V2-PNX-TRI-PLL1
B05A
B05A DDR2
VDDA-ADC
AK20
B07C
USB_DM
USB_DP
PB
90
+1V2-PNX5100-DDR-PLL1
(16-31)
AK12
1E03
72
+3V3
+1V2-PNX5100
+1V8-PNX5100
VDDA-DAC
B04E CONTROL
USB_FAULT
PR
CRX2+
T5
M22
AE25
+2V5-DDR1
VREF-DDR1
A
VGA
CONNECTOR
7P02
TDA9996
1
+VDISP1
AB20
AA5
L16
L5
B04P VDD
B04A
CONTROL
B04A
CONTROL
5
1
ARX0-
3
2
7C02
EDE5116AJBG-8E-E
1E05
ARX1ARX0+
4
*JUMPERS IN CASE OF NO FPGA
ANALOGUE EXTERNALS B
10
ARX2+
3
L3
AV3_PB
7
20
5
AB18
J5
FPGA LOCAL CONTRAST
- LVDS IN/OUT
AI12
VDDA_3V3_AADC
AV3-PR
15
TO DISPLAY
1080p 100/120Hz
11
AI22
7E04
15
16
49
40
TX4
AI32
19
BRX0-
1
B06D
CVBS1Y_P
ANALOGUE EXTERNALS D
G4
EXT 2
50
I2C
P22
1
49
1G51
51
TX3
E15
9FG2
9FG3
9FG4
9FG5
9FG6
9FG7
AV1-Y
BRX1BRX0+
QUAD LVDS
1920x1080
100/120HZ
HD-NM
FHD 100Hz
7FL0
EDD1216AJTA
MM1-A(0-12)
41
N.C.
B05E
FPGA WOW - DDR
DDR
SDRAM
8Mx16
39
40
PNX5120
SUPPLY
B04A
CONTROL
B04A
CONTROL
B04A
AV1-R
1E02
38
VREF
AV1-Y_CVBS
BRX2BRX1+
B06F
9,10,11
9EA7
3
AE17
AF17
AC17
AD17
AC16
AD16
AE16
AF16
AE15
AF15
AC15
AD15
TO DISPLAY
1080p 50/60Hz
37
CVBS-TER-OUT
15
1
RX51002A+
RX51002ARX51002B+
RX51002BRX51002CLK+
RX5100CCLKRX51002C+
RX51002CRX51002D+
RX51002DRX51002E+
RX51002E-
2
3
TX2
AE14
AD14
9EA2
BRX2+
TXF2A+
TXF2ATXF2B+
TXF2BTXF2CLK+
TXF2CLKTXF2C+
TXF2CTXF2D+
TXF2DTXF2E+
TXF2E-
TX1
B05E LVDS
TX
B15
AV1-G
1
U2
V3
U4
V4
U6
V6
U5
V5
U7
V7
U8
V8
B05B LVDS
RX
+5V
AV1_BLK
6
1
2
19
18
1
2
19
18
B08B
16
21
AE20
AF20
AC20
AD20
AC19
AD19
AE19
AF19
AE18
AF18
AC18
AD18
VDDA-LVDS
H264
USB 2.0
AV1-CVBS
CRXC-
AK19
RX51001A+
RX51001ARX51001B+
RX51001BRX51001CLK+
RX51001CLKRX51001C+
RX51001CRX51001D+
RX51001DRX51001E+
RX51001E-
PNX8543
+3V3E
+3V3D
+1V2A
11
1P04
HDMI 3
CONNECTOR
IREF_LVDS
20
CRXC+
4
6
7
+3V3
+1V2
+3V3A
CRX0-
1P03
HDMI 2
CONNECTOR
CVBS-TER-OUT
CRX1CRX0+
12
AI44
RF_AGC
15
1
9
10
AI51
LOCAL
CONTRAST
11
EXT 1
4
6
7
F2
H3
U17
V17
U15
V15
U14
V14
U13
V14
U11
V11
U10
V10
TXF1A+
TXF1ATXF1B+
TXF1BTXF1CLK+
TXF1CLKTXF1C+
TXF1CTXF1D+
TXF1DTXF1E+
TXF1E-
MM1-D(0-15)
7E09
1P02
4
6
7
1
7E05
8
7
9T61
TX852A+
TX852ATX852B+
TX852BTX852C+
TX852CTX852D+
TX852DTX852E+
TX852ETX852CLK+
TX852CLK-
IF_AGC
REGIMBEAU_CVBS-SWITCH
DRX0-
IF-P
CVBS4
7T52
AP22
AN22
AL22
AK22
AP23
AN23
AP24
AN24
AM24
AL24
AM23
AL23
FPGA
WOW
K5
L5
K2
K1
M2
M1
L2
L1
P2
P1
T3
R3
I2C
7E16-7E06
19
DRX1DRX0+
9
10
XO
14
15
1
2
5
DRX2+
XI
ANALOGUE EXTERNALS A
1P05
1
43
8,18,26,53
VDDH
2,16,27,56
VDDL
37
VDDAH_AFE1
42
VDDAH_CVBS
52
VDDAH_OSC
36,46
VDDAL_AFE
1T50
27M
+5V-TUN
+5V-TUN-PIN
3T22
RF-AGC
3T50
3T70
3T70
9T63
OUT
ANTENNA-SUPPLY
9 TUN-P9 9T23
XTAL_OUT
4
39
IF+
44
L14
L15
K17
K18
L17
M17
L13
M14
P17
P18
N17
N18
1
1 TUN-P1 9T18
DC_POWER
IN
IF-
3000
3T98
1
2
HDMI 1
CONNECTOR
B04K ANALOGUE AV
DEMODULATOR
2T15 2
TNR_TSDI
PD_N
VCC
1T25
FE-DATA(0-7)
MD
7T10
UPC3221GV
1 AGC AMPLIFIER
MAIN HYBRID
TUNER
PD_P
LOUT2_A_P
LOUT2_A_N
LOUT2_B_P
LOUT2_B_N
LOUT2_C_P
LOUT2_C_N
LOUT2_D_P
LOUT2_D_N
LOUT2_E_P
LOUT2_E_N
LOUT2_CLK_P
LOUT2_CLK_N
TX851A+
TX851ATX851B+
TX851BTX851C+
TX851CTX851D+
TX851DTX851E+
TX851ETX851CLK+
TX851CLK-
3 2
9T11
PNX5100: LVDS
7C00
PNX5120EH/M2
4
IF-OUT1
TUN-P11
AP18
AN18
AL18
AK18
AP19
AN19
AP20
AN20
AM20
AL20
AM19
AL19
3P59
IF-OUT2
11
5T12
1T11
HD1816AF/BHXP
HDMI SIDE
CONNECTOR
A_P
A_N
B_P
B_N
C_P
C_N
D_P
D_N
E_P
E_N
CLK_P
CLK_N
CA_MDI
PCMCIA-VCC-VPP
18
33
51
52
CONDITIONAL
ACCESS
B02B
B04O LVDS
CA_MD0
CA-MDI(0-7)
B05E
PNX5100: VIDEO-IN
7FN0
EP3C25F324C7N
68P
PCMCIA
B05B
FPGA WOW - IO BANKS
1G50
1
7H00
PNX85439EH/M2
+3V3
+T
B02A
HDMIA-RX2+
HDMIA-RX2HDMIA-RX1+
HDMIA-RX1HDMIA-RX0+
9
10
HDMIA-RXC+
12
HDMIA-RXC-
HDMIA-RX0-
B15
HDMI_RX2_A_N
B16
HDMI_RX2_A_P
A16
HDMI_RX1_A_N
A17
HDMI_RX1_A_P
B17
HDMI_RX0_A_N
B18
HDMI_RX0_A_P
A18
HDMI_RXC_A_N
A19
HDMI_RXC_A_P
A
DDR2-A(0-12)
(16-31)
DDR2
SDRAM
J1
VDDL
J2
VREF
+1V8-PNX85XX
DDR2-VREF-DDR
18310_402_090305.eps
090324
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 63
Block Diagram Audio
AUDIO
B02A FRONT-END
B07A CI: PCMCIA CONNECTOR
B04 PNX8543:
7P15-7P16
74LVC245APW
20
1P00
B04I PNX8543: AUDIO
B04N VIDEO STREAMS
MDO(0-7)
CA-MDO(0-7)
PCMCIA
AADC
VREF_POS
CA_MDI
CA-MDI(0-7)
17
VDDA_3V3_DAC
ADAC1
ADAC2
7T50
DRX3926K
10
TUN-P10
9T21
B-IF-_N-IF-
2T19
B-IF+_N-IF+
2T20
PDP
3T53
PDN
3T55
47
48
PD_P
PD_N
DEMODULATOR
AGC AMPLIFIER
CVBS
5
2T15 2
7
IF-
3052
39
4
2T17 3
6
IF+
3T50
40
1 TUN-P1 9T18
IF-AGC
3 TUN-P3 9T20
34
33
RF-AGC
B07D HDMI
XI
1T50
27M
50
+5V-TUN-PIN
+5V-TUN
44
3T70
43
3T70
IF-P
F2
1
2
1P05
3T56
CVBS4
H3
XO
8,18,26,53
VDDH
2,16,27,56
VDDL
37
VDDAH_AFE1
42
VDDAH_CVBS
52
VDDAH_OSC
36,46
VDDAL_AFE
1
DRX2+
3
DRX2DRX1+
19
18
2
AUDIO IN
VGA
DVI -> HDMI
DRX1DRX0+
9
10
DRXC+
12
DRXC-
+3V3
+1V2
+3V3A
PO_6
+3V3E
+3V3D
+1V2A
1
2
1
CRX2+
3
CRX2CRX1+
A-STBY
2
AUDIO-MUTE
4
11
16
2
20
CRXC-
BRX2BRX1+
4
6
7
BRXC+
12
BRXC-
B08B
5
AP6 AIN_4_L
H264
USB 2.0
ADAC3
ADAC4
ADAC(3)
AM12
AM11
2
ADAC(4)
6
AUDIO-IN4-R
AM5
ARX2ARX1+
4
6
7
11
16
AP-SCART-OUT-L
ARXC+
12
ARXC-
3EA7
AUDIO-CL-L
1
AUDIO-CL-R
7
1
AP-SCART-OUT-R
3EA8
AV1-AUDIO-L
9EA4
AV1-AUDIO-R
7HM1
3
ADAC(7)
AL9 ADAC7
5
ADAC(8)
AL8 ADAC8
B04E CONTROL
USB_FAULT
AUDIO-IN1-L
AN7 AIN_1_L
USB_DM
USB_DP
9EA4
3
AP-SCART-OUT-L
20
USB_VBUS
7E01
A-PLOP
AL16
AN16
USB-OC
USB20-DM
USB20-DP
AP16
AP7 AIN_1_R
AUDIO-IN1-R
USB_RPU
AM17 3H37
1
AP-SCART-OUT-R
VO_2
VDD
8
AUDIO-HDPH-L-AP
2
AUDIO-HDPH-R-AP
3
1
+3V3
Headphone
Out 3.5mm
AN17 3H45
AUDIO-IN2-L
AK6 AIN_2_L
AUDIO-IN2-R
AL6 AIN_2_R
21
AUDIO OUT
L+R
7P10
NAND01GW3B2BN6F
PCI_AD
4
AUDIO-OUT-L
6
AUDIO-OUT-R
8 7HM1
14
7E10
1E03
72
90
DRX2+
71
69
89
87
DRX2DRX1+
CRX1CRX0+
68
66
86
84
DRX1DRX0+
CRX0-
65
83
DRX0-
CRXC+
63
81
DRXC+
CRXCBRX2+
62
42
80
DRXC-
AUDIO IN
L+R
A-PLOP
A-PLOP
10
ADAC(5)
AN11 ADAC5
12
ADAC(6)
AP10 ADAC6
BRX2BRX1+
41
39
BRX1BRX0+
39
36
BRX0-
35
AUDIO-IN3-L
AM6
2
AUDIO-IN3-R
AN6
BRXC+
33
BRXCARX2+
32
23
ARX2ARX1+
22
20
ARX1ARX0+
19
17
ARX0-
16
ARXC+
14
ARXC-
13
7E03
EF
2
M_IREF
M_VREF
SPDIF-OUT
V1
AA31
AB32
3HJ5
+1V8-PNX85XX
DDR2-VREF-CTRL
7HG0
EDE1116AEBG
SPDIF_OUT
DDR2
SDRAM
(0-12)
1E11
5
AUDIO-IN5-L
AN5
8
AUDIO-IN5-R
AP5
B07E HDMI SWITCH
J1
VDDL
J2
VREF
DDR2-D(0-15)
DQ
AIN_5_L
DDR2-A(0-12)
A
DDR2
SDRAM
REF-3V3
HDMIB-RXC+
HDMIB-RXCHDMIB-RX0+
HDMIB-RX0HDMIB-RX1+
HDMIB-RX1HDMIB-RX2+
HDMIB-RX23HK0
RREF-PNX85XX
A14
HDMI_RXC_B_N
A15
HDMI_RXC_B_P
B13
HDMI_RX0_B_N
B14
HDMI_RX0_B_P
A12
HDMI_RX1_B_N
A13
HDMI_RX1_B_P
B11
HDMI_RX2_B_N
B12
HDMI_RX2_B_P
C16
HDMI_RREF
(16-31)
HDMIA-RX2HDMIA-RX1+
HDMIA-RX1HDMIA-RX0+
9
10
HDMIA-RXC+
12
HDMIA-RXC-
HDMIA-RX0-
B15
HDMI_RX2_A_N
B16
HDMI_RX2_A_P
A16
HDMI_RX1_A_N
A17
HDMI_RX1_A_P
B17
HDMI_RX0_A_N
B18
HDMI_RX0_A_P
A18
HDMI_RXC_A_N
A19
HDMI_RXC_A_P
J1
VDDL
J2
VREF
+1V8-PNX85XX
DDR2-VREF-DDR
B04P VDD
VDDA_3V3_AADC
VDDA_3V3_ADAC
VDD_3V3_LVDS
VDDA_HDMI_3V3_BIAS
VDD_3V3_SBPER
1P06
+1V8-PNX85XX
DDR2-VREF-DDR
7HG1
EDE1116AEBG
AIN_5_R
B04H DIGITAL VIDEO IN
HDMIA-RX2+
+3V3-NAND
B04G PNX8543: SDRAM
AIN_3_R
B08C ANALOGUE EXTERNALS C
AUDIO IN
L+R
12,37
AIN_3_L
B04G SDRAM
+1V8-PNX85XX
+3V3
+3V3
VCC
B04M
6
1E07
NAND
FLASH
1G
PCI-AD<->NAND-AD
1E10
DIGITAL
AUDIO
OUT
SIDE
I/O
4
USB 2.0
CONNECTOR SIDE
SW UPLOAD
JPEG
MP3
B07F PNX8543: FLASH
1E04
CRX2CRX1+
2
3
+3V3-PER
B04F CONTROL
CRX2+
1P07
1
15
7P02
TDA9996
2
C_+
3
C_99
D0_+
100
D0_96
D1_+
97
D1_93
D2_+
94
D2_-
IN-2
1E15
7
+3V3-PER
SCART2
EXT 3
8,45,91,24,
75,95
VDDx_1V8
4
VDDO_3V3
46,55
VDDx_3V3
15,21,34,40,
64,70,85,88
VDDH_3V3
IN-1
B04M
6
ARX0-
HDMI
SWITCH
VO_1
B04I PNX8543: AUDIO
6
2
ARX1ARX0+
9
10
1
SHUTDOWN
AIN_4_R
B08B ANALOGUE EXTERNALS B
ARX2+
B08A
A-PLOP
HEADPHONE
AMPLIFIER
21
7
EXT 2
1P04
3
B08C ANALOGUE EXTERNALS C
RESET-AUDIO
AUDIO-IN4-L
A-PLOP
BRX0-
1
MUTE
7HVA-2
RESET-AUDIO
RF_AGC
1E02
BRX1BRX0+
9
10
SPEAKER-R
7HV0
TPA6111A2DGN
15
1
3
4
6
7
AD1
4
7D03
STANDBY &
PROTECTION
PNX8543
SCART1
1P03
BRX2+
RIGHT-SPEAKER
15
SD
+5V
1E01
3
2
CRX0-
1
SPEAKER-L
3
IN-R
1P0B
7
EXT 1
CRXC+
12
2
B07C USB CONNECTOR
CRX1CRX0+
9
10
19
18
6
IF_AGC
B08A ANALOGUE EXTERNALS A
1
4
6
7
1
2
-AUDIO-R
AI44
DRX0-
1P02
1
3
AC5
7HVA-1
1735
1
LEFT-SPEAKER
22
A-STBY
7T52
1P0A
4
6
7
19
18
OUT-L
AI51
B07B AUDIO IN HDMI
1
2
IN-L
+AUDIO-POWER
CLASS D
POWER
AMPLIFIER
1
RF-AGC
49
+5V-TUN
3T22
19
18
5
+AUDIO-L
5D07
10,12 5D08
1,3
B04M PNX8543: AUDIO
OUT
AGC CONTROL
ANTENNA-SUPPLY
9 TUN-P9 9T23
+5V
1
2
ADAC(2)
7HM2-2
EF
3P59
DC_POWER
IN
4
3T98
1T25
PO_7
B04K ANALOGUE AV
SIF
VCC
1
SAW 36M125
19
18
AP13
ADAC(1)
B04A STANDBY
CONTROLLER
FE-DATA(0-7)
MD
7T10
UPC3221GV
1
2
HDMI 4
CONNECTOR
AN14
3 2
9T11
MAIN HYBRID
TUNER
HDMI 3
CONNECTOR
PVCC_L
7HM2-1
EF
4
TUN-P11
+5V-TUN
HDMI 2
CONNECTOR
VDDA-DAC
+T
11
5T12
IF-OUT1
HDMI 1
CONNECTOR
7D10
TPA3123D2PWP
VDDA-AUDIO
OUT-R
IF-OUT2
HDMI SIDE
CONNECTOR
AK9
PVCC_R
B02B DEMODULATOR
1T11
HD1816AF/BHXP
AN8 5HRW
AM9 5HRZ
PCMCIA-VCC-VPP
18
33
51
52
CONDITIONAL
ACCESS
B04L AUDIO
CA_MD0
68P
BUFFER
B10A AUDIO
7H00
PNX85439EH/M2
+3V3
VDD_1V2_CORE
VDD_1V2_SBCORE
VDD_3V3_PER
VDD_1V8_DDR
AJ6
AK12
AK20
F16
AC6
AJ12
AF5
AJ21
AG30
VDDA-DAC
VDDA-ADC
VDDA-LVDS
RREF-PNX85XX
+3V3-STANDBY
+1V2-PNX85XX
1V2-STANDBY
+3V3-PER
1V8-PMNX85XX
18310_403_090305.eps
090313
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 64
Block Diagram Control & Clock Signals
CONTROL + CLOCK SIGNALS
B07G ETHERNET
B07A CI: PCMCIA CONNECTOR
B02A FRONT END
B04 PNX8543:
7H00
PNX85439EH/M2
B04N TUN_CA
B04A
PCI-CLK-ETHERNET
60
RESET-ETHERNET
62
25M
MOCLKA
PCI-AD(0-31)
PCMCIA
IRQ-PCI
CONDITIONAL
ACCESS
CA-MOCLK_VS2
MDO(0-7)
PNX8543
CA_MDO
CA-DATADIR
CA-DATAEN
PCMCIA-D(0-7)
D31
CA_DATA_DIR
A31
CA_DATA_EN
B09A MINI PCI CONNECTOR
CA-ADDEN
PCMCIA-A(0-14)
B31
CA_ADD_EN
AL23
LOUT2_CLK_N
AM23
LOUT2_CLK_P
AL19
CLK_N
CLK_P AM19
TX852CLK-
TX851CLK+
MINI PCI CONNECTOR
MINI PCI CONNECTOR
FOR WIFI PANEL
B06G
7HG0
EDE1116AEBG
7HG1
EDE1116AEBG
DDR2-D(0-31)
DDR2-A(0-12)
J34 CA_RDY
68
M_CLK_N
B07F PNX8543: FLASH
AB34
DDR2-CLK_P
J8
AB33
DDR2-CLK_N
K8
PCI-GNT-B
E29 GNT_B
PCI-AD(0-31)
PCI_AD
PCI-AD(0-31)
B03G PNX8543: CONTROL
PLL_OUT
AP28
PCI-CLK-OUT
19
WP-NANDFLASH
7C00
PNX5120EH/M2/F4
B05G PCI_XIO
L3
PCI-CLK-PNX5100
NAND
FLASH
(1G)
3HF4
3HF2
NAND-AD(0-7) <-- PCI-AD(24-31)
7
XIO-ACK
A20
9
XIO-SEL-NAND
B20
B04A
XIO_ACK
CLK
XIO_SEL_0
B04E CONTROL
GPIO_1
IRQ-CA
L34
IRQ-PCI
U4
PCI-AD(24-31)
1P07
1
PNX5100-DDR2-D(0-31)
1
PNX5120
RESET_SYS
B07C USB CONNECTOR
7C01
EDE5116AJBG
7C02
EDE5116AJBG
USB 2.0
CONNECTOR
SIDE
3 2
B05A PNX5100: SDRAM
2
3
4
B05A DDR2
GPIO_6
4
USB-OC
USB20-DM
USB20-DP
AL16
B05G
PCI-CLK-MINI
B09A
PCI-CLK-PNX8535
7CD0
M24C08-WDW6P
U3
WC-EEPROM-PNX5100
V2
PNX8543-LCD-PWR-ON_SPI-DI
RESET-SYSTEM
AN28
7
B07B
B02B B04A B04B
B08D ANALOGUE EXTERNAL D
L32
3
GPIO_5 L31
2
GPIO_4
DDR2-A(0-12)
PNX5100-DDR2-CLK_P
J8
P25
PNX5100-DDR2-CLK_N
K8
AD2
SDRAM
B04A STANDBY
P0_5
UA_RX_0
B04B PNX8543: DEBUG
2H07
SDM
AG2
P1_7
UA_TX_1
AG1
AH5
RXD-UP
9E05
9E41
TXD-UP
9E03
9E40
B04A PNX8543: STANDBY CONTROLLER
2H06
B05F CONTROL
RESET-PNX5100
CADC_1
B26
LCD-PWR-ON
A26
BACKLIGHT-PWM-ANA-DISP
B01B
DETECT2
B04A
DETECT1
B04E
RESET-SYSTEM
B01B
AV1-BLK
B08A
B01B
B08A
9CG8
F18
BACKLIGHT-CONTROL-FPGA-IN
2
CLK-OUT-PNX5100
B06F FPGA WOW - DDR
3
OUTP 1
AD4
PWM_1
P2_5
RESET-ETHERNET
PWM_0 AJ3
AN3
AH1
AV1-STATUS
AP2
AV2-STATUS
AP1
CADC_0
P3_5
P3_4
CADC_2
RESET-AUDIO
P0_7 AC5
AUDIO-MUTE
P2_2 AE1
LAMP-ON
CADC_3
AE4
ENABLE-3V3
AF1
REGIMBEAU_CVBS-SWITCH
P2_6 AE5
POWER-OK
AB3
RESET-PNX5100
P2_7
P1_1
AF3
RESET_IN
INP
P0_2
GND
P2_3
MM1-CLK+
45
A1
MM1-CLK-
46
1
2
A2
DDDR
SDRAM
8Mx16
B06E FPGA WOW - POWER & COTROL
7P10
NAND01GW3B2BN6F
D1
ASDO
5
H4
DCLK
nCSO
DATA0
6
1
2
NAND
FLASH
(1G)
4x HDMI
CONNECTOR
TO PIN:
1P04-13
1P03-13
1P02-13
1P05-13
CEC-HDMI
AG4
7P02
TDA9996
12
31
ARX-DDC-SCL
1P04-15
BRX-DDC-SCL
1P03-15
CRX-DDC-SCL
1P02-15
DRX-DDC-SCL
1P05-15
HDMI_RX
HDMIB-RX
61
79
B07E
HOTPLUG-A
D19
HOT_PLUG_A
XTAL_O
B04M
TO
IR/LED PANEL
AND
KEYBOARD CONTROL
8
1M99
5
B10A
B01A B01B B01C
B07A
B05H
B08A
BACKLIGHT-OUT
6
BACKLIGHT-BOOST
7
TO
POWER
SUPPLY
9
B05H
B05F
BACKLIGHT-PWM-ANA-DISP
8
1M95
2
7HC3
M24C64-WDW6P
8
TO
POWER
SUPPLY
EEPROM
(8Kx8)
7H02
M25P05-AVMN6P
W2
AJ1
SPI_CLK
AK4
P6_5
AK3
SPI_CSB
AJ4
SPI_SDO
AK1
SPI_SDI
5
7
+5V
W1
B04H HDMI_DV
HDMI
SWITCH
RESET-NVM
P0_1 AC1
XTAL_I
57
PCEC-HDMI
P1_2
+3V3-STANDBY
6
7HC4
7P32
CONTROL
19
18
MM1-A(0-11)
7U11
STANDBY
AD5
3
4
B07G
KEYBOARD
AD1
P0_6
RC
LED1
B07D HDMI
MM1-D(0-15)-->DQ1(0-15)
E2
H3
AB2
P2_4
AH2
RESET-STBY
LED2
AH3 P3_3
7FL0
EDD1216AJTA
FPGA
WOW
P0_3
AJ2
9H25
27M
E18
3HD4
7FN0
EP3C25F324C7N
AD3
AV2-BLK
B08A
+3V3-STANDBY
+3V3-STANDBY 7HD0
NCP303LSN30G
B06G FPGA WOW - IO-BANKS:
B06G I/O BANK
DETECT-12V
B08A
BACKLIGHT-BOOST
RC_UP
1HF0
BOOST-CTRL
9H13
B05H
7CG8
BACKLIGHT-CTRL
1M20
1
LIGHT-SENSOR
AN2
P1_0 AF2
CLK-OUT-PNX5100
AF14
A24
RES
B01B DC / DC
2
B04A PNX8543: STANDBY CONTROLLER
AF13
B23
UP
STANDBY
3
AK2 P6_4
SPI-PROG
B04A
27M
1CD0
AE13
SPI-PROG
1E50
3
RES
SDM
B05H GPIO
UART
SERVICE
CONNECTOR
1
P26
AF24
EEPROM
(2Kx8)
1E06
USB_FAULT
AN16
USB_DM
AP16
USB_DP
B07G
PCI-CLK-PNX5100
A30
GPIO_3
GPIO_2
B05F PNX5100: CONTROL
3HFG PCI-CLK-ETHERNET
3HFH
7P10
NAND01GW3B2BN6F
68
B05 PNX5100:
SDRAM
B04F PCI
PC1-GNT-MINI
PCI-AD(0-31)
B03G
B04G PNX8543: SDRAM
M_DQ
M_CLK_P
IRQ-PCI
RESET-SYSTEM
B06G
B06G
B06G
TX852CLK+
TX851CLK-
M_A
RESET-mPCI
32
PCI-AD(0-14)
IRQ-CA
1A01
1
9
10
5
FE-VALID
FE-SOP
B04O LVDS
B04G MEMORY
PCI-AD(24-31)
7N11
7N12
9H25
50
FE-CLK
B10
C10
TNR_MIVAL
TNR_MISTRT B9
TNR_MICLK
B07H BUFFERING
7N13
DEMODULATOR
CA_MICLK
A34
CA_VSN_0
H31
CA_MOCLK
CA-MDO(0-7)
FE-DATA(0-7)
TNR_TSDI
CA_MDI
7P15-7P16
18
61
H32
CA-MDI(0-7)
COMMON INTERFACE
ETHERNET
CONNECTOR
B04F
1N02
17
MAC
PHYTER II
10/100 Mb/S
CA-MICLK
27M
1P00
1
1304
49
7N04
DP83816AVNGNOPB
1N00
7303
DRX3926K-XK-A3
SPI-CLK
SPI-SDI
6
SPI-WP
3
SPI-CSB
SPI-SDO
1
5
2
512K
FLASH
STANDBY
SW
18310_404_090305.eps
090327
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 65
Block Diagram I2C
I²C
B07D
PNX8543: CONTROL
B02B
HDMI
B02A
DEMODULATOR
B05F
FRONT-END
B06E
PNX5100: CONTROL
B06G
FPGA WOW
POWER & CONTROL
B06A
FPGA WOW - IO BANKS
FPGA BACKLIGHT - LVDS & I2C - MUX
B08D
ANALOGUE EXTERNALS D-
+3V3-PER
7P02
TDA9996
PNX8543: SDRAM
7HG0
EDE1116AEBG
MEMORY
M_DQ
M_A
DDR2-A
ERR
23
SDRAM
16
ARX-DDC-SCL
15
30
31
9T15
RES
DEMODULATOR
MICRONAS
9T71
9T70
62
TUNER BUS
400 kHz
3P67
3P68
61
3T16
TUN-P7
TUN-SCL
3T15
TUN-P6
6
78
DDC_SCL_B
C15
DDC-SCL
5
79
B07E
HDMI_DV
3P65
DDC-SDA
3P66
D15
DDC_SDA_B
BRX-DDC-SDA
16
BRX-DDC-SCL
15
ERR
15
7
ERR
21
1P02
16
CRX-DDC-SCL
15
54
16
DRX-DDC-SCL
15
2M
FLASH
D18
9FNA
C18
9FN9
MM1-D
DDR
SDRAM
8Mx16
1HP0
3
1
SDA
SCL
RESERVED
MM1-A
+3V3
AMBILIGHT BUS
30 kHz
ERR
34
L1
3CDA
SDA-AMBI-3V3
L2
3CD9
SCL-AMBI-3V3
9F22
3FA6
9F21
3FA5
1M59
3
1
3
+3V3
4
5
HDMI
CONNECTOR
SIDE
TO
AMBI-LIGHT
MODULE
7
B08B
HDMI SWITCH
3U67
3U66
SPARTAN-3
FPGA
1P05
DRX-DDC-SDA
7F01
M25P20
53
7F00
XC3S250E
MAIN
TUNER
HDMI
CONNECTOR 1
3F22
3F23
ERR
29
7FL0
EDD1216AJTA
6
3FNG
FPGA
LOCAL
CONTRAST
FPGA WOW - DDR
ERR
25
G18
7FN0
EP3C25F324C7N
BOOT
EEPROM
1T11
HD1816AF
CRX-DDC-SDA
G17
16M
FLASH
B06F
ERR
27
HDMI
CONNECTOR 2
7FH0
M25P16
6
7CD0
M24C08
PNX5120
FHD 120Hz
3FNF
3CDC
5
1P03
+5V-DDC
B04H
K2
7C00
PNX5120EH
TUN-SDA
+5V-DDC
60
3CDD
K1
+3V3
61
3CD7
3CD8
9T16
23
7T50
DRX3926K
HDMI
CONNECTOR 3
+5V-DDC
HDMI
MUX
7HG1
EDE1116AEBG
DDR2-D
12
24
1P04
ARX-DDC-SDA
3FAB
B04G
B04G
11
3FAA
PNX8543
3T59
50
3T61
+5V-DDC
49
3T57
SCL-SSB
ERR
13
3T58
3HPH
3P58
SCL3
3P61
SCL 3
3P63
D33
SDA 3
3P64
SDA-SSB
3P76
3HPJ
3P77
SDA3
3HPM
SSB BUS
400 kHz
G32
3HPK
7H00
PNX85439EH
B05A
ANALOGUE EXTERNALS B
B04N
PNX5100: SDRAM
B07F
PNX8543: VIDEO STREAMS
PNX8543: FLASH
C18
DDCA-SCL
9P20
ERX-DDC-SCL
15
HDMI
CONNECTOR 4
1E05
7P10
NAND01GW3B2BN
B04F
PCI-AD
FLASH
1G
12
PNX5100-DDR2-D(0-31)(0-31)
DATA-SDA
5
EEPROM
CLK-SCL
6
256x8
15
PNX5100-DDR2-A(0-12)
7C02
EDE5116AJBG
3HB2
I2C-SDA
1M97
15
3HB1
I2C-SCL
14
SDRAM
1M96
7P07
M24C02
EEPROM
256x8
PCI
15
5
1
6
6
5
7E18
M24C02
11
PNX5100: SDRAM
7C01
EDE5116AJBG
+5VDCOUT
3P31
B07F
3P30
DDC_SCL_A
16
10
DDC_SDA_A
1P06
ERX-DDC-SDA
3E47
9P19
3E70
DDCA-SDA
3P28
E19
3P29
+5V-DDC
9P29-4
5
9P29-3
6
VGA
CONNECTOR
RES
B01B
B06C
DC/DC
B06A
TEMPERATURE & FAN CONTROL
B06D
FPGA BACKLIGHT - LVDS & I2C - MUX
+3V3-PER
SDA1
3HPE
SDA-UP-MIPS
F33
SCL1
3HPD
SCL-UP-MIPS
SDA 1
SCL 1
3U67
3U66
10
RES
B04A
TO
POWER
SUPPLY
7
6
7F50
LM75ADP
7F51
PCA9533DP
IC TEMP
SENSOR
I2C LED
DIMMER
3F18
2
1
PNX8543: STANDBY CONTROLLER
1M71
3
3F40
1
5F05
4
+3V3
9F16
9F17
9F14
I2C
MULTIPLEXER
TO
TEMP
SENSOR
4
SDA-SET0
9F15
SDA-DISP
5
SCL-SET0
9F13
SCL-DISP
7
SDA-SET1
8
SCL-SET1
3F38
SCL-BOLT-ON
9F18
3F39
9F19
3
7F08
PCA9540BDP
3F41
SDA-BOLT-ON
3E83
3E84
1R08
6
5
TO BOLT-ON
MODULE
+3V3
3F36
3H50
H33
1M99
11
2
9F20
3F37
1
9FA1
+3V3-PER
STANDBY BUS
400 kHz
9FA2
ERR
14
1F53
3F17
2
3F66
SCL-SET
3F67
3HPS
3F62
SCL2
3HPT
SDA-SET
3F61
SCL 2
SDA2
FPGA LOCAL CONTRAST
LVDS IN/OUT
+3V3
3H49
D32
SDA 2
3HPU
3HPV
SET BUS
100 kHz
B33
DISPLAY BUS
100 kHz
1F51
3FH4
1
3FH5
2
TO
DISPLAY
2
+3V3-STANDBY
RESERVED
MC_SCL
3H55
SCL-UP-MIPS
+3V3-PER
STANDBY
PO_1
AC1 RESET-NVM
3HC2-1
5
7HC4
EF 8
RES
7HC3
M24C64
B05E
ANALOGUE EXTERNAL D
6
UART-SWITCH
B04A
EEPROM
(NVM)
7H02
M25P05
ERR
53
B08D
3E08
AL5
MC_SDA
3H53
SDA-UP-MIPS
3H52
3H66
3H53
AK5
3H53
RESERVED
B04A
3HC2-2
UART-SWITCHn
7E19
74HC4066PW
QUAD
BILATERAL 2
6 SWITCHES
9
13
9E40
TXD-UP
1R12
2
FOR
MHP BOLT-ON 3
5
12
7E17
ST3232C
RXD-UP
3
1
8
1E50
3
1
14
3ECK
1R08
2
3
12
UA_TX_1
TXD-UP
11
T1-IN
R2-IN
TXD-UP
1
TO
DISPLAY
UP
1G51
1E51
3
8
1
MIPS
T2-OUT
3H60
RXD-UP
AH5
3H58
AG1
2
3CA2
R1-OUT
7
UA_RX_0
3CA3
T1-OUT
RXD-UP
3ECP
11
+3V3-STANDBY
1G50
RS232
INTERFACE
13
R1-IN
TXD-UP
4
10
PNX5100: LVDS
9E41
RXD-UP
7E20
512K
FLASH
3CA4
50
3CA5
49
TO
DISPLAY
9E05
9E03
GPIO_5
RXD-MIPS
TXD-MIPS
3HPL
L32
L31
GPIO_4
3HPC
+3V3-PER
AL27
RXD-MIPS2
UA2_TX
AK27
TXD-MIPS2
3HPP
+3V3-PER
UA2_RX
9
10
3HPR
B04E
B06B
5FC7
5FC5
1
T2-IN
LEVEL SHIFTER FOR
DEBUG ONLY
LED PANEL CONTROL
1R20
3
R2-OUT
RESERVED
9E35
RXD
3E41
9E36
TXD
3E91
1E06
3
2
1
RES
UART
SERVICE
CONNECTOR
18310_405_090305.eps
090316
2009-May-08
Block Diagrams
Q549.2E LA
9.
EN 66
Supply Lines Overview
SUPPLY LINES OVERVIEW
A
SUPPLY
B01B
DC / DC
B04I
B01C
12V
CN5
1
1M99
1
B05h
GND1
GND1
BL-ON_OFF
DIM
BOOST
A/P_DIM
INV_OK
2
2
3
3
4
4
5
5
7U01
TPS53124PW
LAMP-ON-OUT
6
6
BACKLIGHT-OUT
7
7
BACKLIGHT-BOOST
8
8
BACKLIGHT-PWM-ANA-DISP
9
POWER-OK
MAIN
POWER SUPPLY
7U0D-1
B05H
CONTROL
B05H
CONTROL
3P09
AUDIO-VDD
7HM5
1M95
1
B04L
+5V
12V/1V2
CONVERSION
B01a
B01b,B04a,l
B06a,B07a,c,
d,B08a,b,d,
B09a,d
+3V3
B02A
+3V3-STANDBY
B07B
B05H
7U0M
GND1
GND1
2
3
3
4
4
5
5
USB CONNECTOR
+12VD
+12VD
VDDA-AUDIO
+VDISP
7CG1
IN OUT
COM
1C02
7CG2
LCD-PWR-ON
PNX8543: AUDIO
+VDISP1
B05e
T3A
1C01
FRONT-END
5CG2
5CG0
B05e
RES
B01a
+3V3A
+5V-TUN
5T11
STANDBY
+3V3A
B01a
+5V-TUN
B01b
B07D
+5V-TUN-PIN
+33VTUN
+AUDIO-POWER
+1V8-PNX85XX
+3V3
+3V3
+12V
+12V
6
7
7
B05I
ADIO-VDD
B04i
8
+3V3
3T12
3T11
B04N
+VTUN
+3V3-PER
ANTENNA-SUPPLY
ANTENNA-SUPPLY
B06A
PNX8543: VIDEO STREAMS
5F05
+3V3-PER
+3V3
+12V
+3V3
T3A
+3V3
B02a
7U0P
B04O
7F06
VDDA-LVDS
VDDA-LVDS
9T64
HDMI 1
CONNECTOR
+1V2
T3A
9
10
10
11
2K9 SUPPLIES
5U06
GND1
24Vb
GND1
TO
DC-DC INTERFAC
(OPTIONAL)
B01a
+3V3
+3V3
+5V
+5V
HVR
HVL
HVL
HVL
1M20
+3V3-STANDBY
5
+5V-TUN-CVBS
+1V8-PNX85XX
+1V8-PNX85XX
+3V3-STANDBY
+3V3-STANDBY
TO DISPLAY
+3V3
RES
+12V
5HV8
RREF-PNX85xx
5HVD
VDDA-LVDS
+3V3
+12V
+12V
VDDA-AUDIO
B01a
5HY4
VDDA-DAC
B01b
5HY7
AUDIO-ADC
B06C
B05A
B01b
PNX8543: STANDBY CONTROLLER
+1V2-PNX5100
+1V2-PNX5100
+3V3-STANDBY
+3V3-STANDBY
+12V
+12V
B05h
+5V
5FH4
+VDISP
B04B
PNX8543: DEBUG
B01c
B01b
B01b
1V2-STANDBY
1V2-STANDBY
+3V3-PER
B04p
+3V3-PER
+1V8-PNX85XX
+1V2-PNX5100-CLOCK
5C61
+1V2-PNX5100-TRI-PLL1
5C62
+1V2-PNX5100-TRI-PLL2
B04E
+12VF1
5U33
7U03
TPS53124PW
23
7U08
Dual
Synchronous
Step-Down 15
Controller
7U02
12V/3V3
COVERSION
17
5U03
7U05
+3V3F
B01b,B02b,
B04a,l,m,n,p,
B05b,c,e,h,
f,g,i,
PNX8543: CONTROL
B06a,b,c,e,
B07a,d,f,g,h,
B08a,b,d,
B09a
+3V3-PER
B04p
7U06
26
B04G
+1V2-PNX85XX
B02b,B04a,p
B06a,e
B09b
+1V2-PNX5100-DDR-PLL1
5C65
+1V2-PNX5100-LVDS-PLL
5C66
+1V2-PNX5100-DLL
B01a
+3V3-PER
PNX8543: SDRAM
+1V8-PNX85XX
+3V3-PNX5100-LVDS-IN
5C68
+3V3-PNX5100-CLOCK
5C69
+3V3-PNX5100-DDR-PLL0
5C70
+3V3-PNX5100-LVDS-PLL
3HJ1
DDR2-VREF-CTRL
3HJ3
DDR2-VREF-DDR
B05E
+VDISP2
PNX8543: DIGITAL VIDEO IN
+VDISP1
+VDISP1
B05h
RREF-PNX85XX
B06e
1G50
41
1G51
1
B06e
B06e
B06f
B06e
B06f
2009-May-08
VLED2
+16V
1M84
6
TO
AMBI-LIGHT
MODULE
AB2
DUAL DC-DC
+24VF
+24VF
14
PNX8543: FLASH
NON
SYNCHRONOUS
CONVERTER
+3V3
+3V3-NAND
ETHERNET
AB3
+3V3
B06g
12
5201
(VLED1)
+12V
3
5200
(VLED2)
+16V
5FH4
+2V5-PLL
5FH1
+3V3-FPGA
AB1
AB1
MICROCONTROLLER BLOCK
+3V3
5N06
+3V3-ET-DIG
5N07
+3V3-ET-ANA
+3V3
+3V3
B01b
7301
B01c
B05a,c
+1V8
OPTIONAL
B07H
BUFFERING
+3V3
B01a
+3V3
+5V5-TUN
+5V5-TUN
+5V-TUN
7P11
B02a,b
B06g
7P13
VOLT.
REG.
B06g
B06g
B01b
+12V
+12V
B06g
B08A
FPGA WOW - DDR
+2V5
B01a
B01c
B06G
B06e
+3V3
c002
OPTIONAL
B06g
+2V5-DDR1
3FLK
VREF-DDR1
3FLM
VREF-FPGA1
B06g
FPGA WOW - IO BANKS
+1V2-PLL
B01c
+1V2-FPGA
+2V5-PLL
+2V5out-FPGA
+1V2-PLL
B01b
+2V5-PLL
+5V
B08B
ANALOGUE EXTERNALS B
+3V3
+3V3
+5V
+5V
+12V
+12V
B08D
+2V5out-FPGA
+2V5in-FPFA
+2V5-DDR1
+2V5-DDR1
VREF-FPGA1
+3V3
+5V
+1V2-FPGA
+2V5in-FPFA
3V3-FPGA
ANALOGUE EXTERNALS A
+3V3
B06g
B01a
PNX5100: LVDS
+3V3
+VDISP2
RREF-PNX85XX
+2V5in-FPGA
5FL0
B06e
B05h
B04p
+2V5out-FPGA
5FH3
+2V5
+3V3
5C67
5FH2
+1V8-PNX85XX
B01a
B04H
B06F
+1V8-PNX5100
+3V3
+1V8-PNX5100
+3V3
B06e
12V/1V2
COVERSION
5U00
+1V2-PNX5100-TRI-PLL3
5C64
B09b
B05h,B09b
28
5C63
+1V8-PNX5100
B04F
+3V3
5U01
+3V3-PER
VLED1
B01a
PNX8543: CONTROL
+3V3-PER
B04p
c001
IN OUT
COM
+1V2-PLL
+2V5
+3V3
+12VF
+12VF
B07G
+1V8-PNX85XX
+2V5
+1V2-PNX5100
5C60
AB3
OPTIONAL
+1V2-FPGA
5FH0
B09b
+1V2-PNX5100
+12V
AB2
11
+1V2-PNX85XX
CFH1
DC/DC
+12V
EIN-5V
FPGA WOW - POWER & CONTROL
+3V3
B09b
+3V3
1F51
41
B01a
PNX5100: POWER
T3A
6
+16V
+5V-DDC
5P09
5FG2
CFH0
+3V3
B05C
1P06
18
+3V3
B01a
5FG1
+1V2-PNX85XX
B01a
+24VF
+5V-EDID
+VDISP
B01a
PNX5100: VIDEO-IN
5102
7200
TPS54283PWP
B07F
B06E
TO 1M59
B06A
SSB
AB2
AB1
FPGA WOW - LVDS IN / OUT
3C20 PNX5100-DDR2-VREF-CTRL
B05B
1M59
1M96
3
3C22 PNX5100-DDR2-VREF-DDR
+3V3-PER
+5V
B01c
B06e
CIN-5V
+24V
1101
RES
+3V3
+1V8-PNX5100
+3V3
+3V3-PER
B04p
PNX5100: SDRAM
+1V8-PNX5100
+1V2-PNX85XX
+3V3
B01a
B01A
HDMI SIDE
CONNECTOR
TEMPERATURE & FAN CONTROL
+3V3
B06D
B04A
1P02
18
TO CN7
SUPPLY
HDMI SWITCH
B04a,b,e,f,n
B04h
INTERFACE + SINGLE DC-DC
13
+3V3
B04l
TO
IR/LED
PANEL
DIN-5V
+3V3-PER
VDDA-AUDIO
AB1
6P06
B01b
5HVH
B02a
1P05
18
B07d
U-WAND
+AUDIO-POWER
1
AB2
B07E
+AUDIO-POWER
1M90
+5V-EDID
B06B
B04o
B01a
TO DISPLAY
+5V
B01a
+3V3
B01a
ANTENNA-SUPPLY
+1V2-PNX85XX
1319
1
3
B01b
5T55
+12V
B01c
2
B02a
+3V3E
+2V5
+5V
RES
B09b
5T52
+2V5
+1V2-STANDBY
B01b
1316
1
3
+1V2-STANDBY
B01b
B01c
5
6
2
+1V2-PNX85XX
AUDIO
B01b
BIN-5V
+1V2-PNX85XX
B01c
B04l
8
HVR
HVR
+3V3D
+12V
CN7
1
3
4
5T53
3T69
7T56
2
+3V3A
+1V2-PNX85XX
+5V-TUN
2K8 SUPPLIES
24Vb
5T54
+5V-TUN
B07h
5U17
24Vb
GND1
B04P
B01a
+3V3
AIN-5V
B01a
PNX8543: POWER
B09b
5U20
11
+1V2-PNX85XX
+1V2A
RES
B01a
B04i,m,B10a
+AUDIO-POWER
5U21
N.C.
5T51
IN OUT
COM
+3V3
B01a
HDMI SIDE
CONNECTOR
IN OUT
COM
B04p
7T54
+12VF
IN OUT
COM
+2V5M
B01a
B10A
+1V2M
PNX8543: DIGITAL VIDEO OUT / LVDS
+1V2-PNX85XX
9T62
1U03
+3V3M
7F07
+1V2-PNX85XX
6U0B +33VTUN
5U08
B02B
B01c,B02b,
B06c,B07b,h,
B08b,B09b
+2V5-REF
+5V-EDID
B07e
1P04
HDMI 3
TO 1M59
18
CONNECTOR
AB1
DC-DC
OR
1P03
AMBI-LIGHT
HDMI 2
18
MODULE
CONNECTOR
T1A
+3V3
DEMODULATOR
RESERVED
GND_SND
3P47
1M59
6
1F50
B04p
7A07
VOLT.
REG.
3A26
+5V
FPGA BACKLIGHT-LVDS & I2C-MUX
B01a
9
+V-LM833
+3V3-STANDBY
+5V
B01c
B01a
1U01
+3V3-STANDBY
B01b
VSW
+VSND
+12V
3A07
RES
+3V3
3T10
B02b
8
B01b
1V8-HDMI
IN OUT
COM
PNX5100: DEBUG
B01a
+33VTUN
B01b
B04A
CONTROL
3U42
+12V
REF-3V3
B04g,p,
B06e,B07d
7A00-2
LCD-PWR-ON
7P01
+AUDIO-POWER
AUDIO-VDD
5F04
6
+1V8-PNX85XX
7A02
HDMI
+3V3
+3V3
B06a,e,f
7A00-1
LCD-PWR-ON
+1V8-PNX85XX
B09b
+VDISP2
T3A
+2V5
7A01
+5V
B06d
B04p
VDDA-DAC
+3V3F
B01a
+5V
B01c
B01b
DDR SUPPLY
+3V3F
B01a
+5V
GND1
+12V
RES
B09B
B07C
+3V3
5P11
B07h
RESERVED
2
+5V
B01a,B04p
B02b
STANDBY
+5V-mPCI
+12V
+1V2-STANDBY
7U0N
VOLT.
REG.
5A01
+5V
+3V3F
+3V3
7HP0
B04M
B01b
PNX5100: DISPLAY-INTERFACING
+3V3F
B04a
B05c
B04a,p
B07d,B08d
IN OUT
COM
+3V3-mPCI
AUDIO IN HDMI
+12V
B01a
+3V3
+5V
B01c
+1V2-PNX5100
5U04
PNX8543: AUDIO
26
7U50
+3V3
5A00
B01c
+3V3
B01a
VDDA-DAC
CN4
1
MINI PCI CONNECTOR
PCMCIA-VCC-VPP
PNX5100: PCI
+3V3
B07h
28
7U0D-2
B09A
B01a
+T
B05G
B04p
3.3V_ST
+5V
+5V5-TUN
17
B05H
CONTROL
9
+3V3
+5V
+3V3
B01c
7HM6
CONTROL
12V/5V
CONVERSION
SS36
B05H
CONTROL
+3V3
B04m
23
7U0H-1
Dual
Synchronous
Step-Down 15
5U05
Controller
7U0H-2
B04A
CONTROL
B01a
+3V3
B01a
RES
CI: PCMCIA CONNECTOR
PNX5100: CONTROL
+3V3
+12VF2
3HMF
B05F
+AUDIO-POWER
9HM0
B01b
5U31
12V
+AUDIO-POWER
B01b
+12V
+12V
+12VD
B07A
PNX8543: AUDIO
DC/DC
3V3-FPGA
B01a
B01c
B01b
ANALOGUE EXTERNALS D
+3V3
+3V3-STANDBY
+5V
+3V3
+3V3-STANDBY
+5V
VREF-FPGA1
18310_406_090305.eps
090306
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 67
10. Circuit Diagrams and PWB Layouts
Interface Ambilight: Interface + Single DC-DC
2
1
A
3
1
6
5
4
2
3
8
7
4
5
9
6
7
INTERFACE + SINGLE DC-DC
12
8
13
1100 A6
1101 A7
1M59 C2
1M84 A2
1M85 A2
1M90 D2
2100 A6
2101 B5
2102 C6
2103 D6
2104 D5
2105 D9
2106 D9
2107 E9
2108 D3
2109 E3
3100 B5
3101 C5
3102 D6
3103 D9
3104 D6
3105 D5
3106 D5
3107 D5
3108 E9
3109 D2
3110 D3
3111 E8
3112 B6
5100 A8
5101 A8
5102 A7
5103 B8
5104 B8
5105 B8
5106 B8
5107 A6
5108 A6
6100 C8
7100 B7
9101 C3
9102 C3
9103 C3
9104 C3
F101 B3
F102 B3
F103 B3
F104 B3
F105 B3
F106 B3
F107 A7
F108 B3
F109 B3
F110 B3
F111 B3
F112 B3
F113 B3
F114 B5
F115 C2
F116 D2
F117 D2
F118 D2
F119 D2
F120 D2
F121 E2
F122 E2
9
2n2
I102
SCL
15K
220p
3102
330R
18
1%
30R
30R
30R
30R
5106
I104
D
GND_HS
100n
3K3
2107
3108
100K
+24V
3111
+24V
1%
+24V
1735446-6
E
E
+12V
c001
VLED1
+16V
c002
VLED2
H
1
I
NC
100p
RES
F121
F122
F123
F124
2109
G
VIA
TIM_CAP
I106
1M90
1
2
3
4
5
6
1
VFB
2
GND
I105
33K
3107
1M0
3106
3104
100n
+3V3
2103
2
2104
RES
3105
1735446-7
1
SDA
CONTROL1
CONTROL2
C
20
21
22
23
24
25
26
27
28
29
30
31
12K
RES
3110
100R
100p
RES
3109
100R
BOOT_IN
I108
+16V
2108
D
F116
F117
F118
F119
F120
17
16
VSW
3K3
F115
14
10
11
12
13
SWI_COL
I103
2102
SPI-LATCH2CONN
SPI-LATCH2
SWI_EMIT
3103
47R
DRV_COL
100n
6
7
8
9
LVI_OUT
LPK_SENSE
15
100n
2106
5
I101
Φ
2105
SPI-LATCH1
SPI-LATCH1CONN
B
SS24
502382-1470
1M59
1
2
3
4
5
6
7
30R
5103
5105
VCC
4
3101
*
3
VLED2
7100
NCP3163BMNR2G
16
9103(RES)
9104
*
+16V
100R
F114
9101
9102 (RES)
*
*
0R1
RES
VLED1
E
2.0A T 63V
3100
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
C
A
I109
6100
502382-1470
*
1101
F107
19
16
+3V3
F113
F125
10u
+16V
+12V
10n
D
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH1CONN
PWM-CLOCK-BUF
3112
B
F101
F102
F103
F104
F105
F106
F108
F109
F110
F111
F112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2101
C
1M84
220n
1M85
2100
*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5102
T 3.0A 32V
30R
SPI-LATCH2CONN
5104
I100
1100
+24V
F126
F
5100 RES
+24VF
30R
5101 RES
30R
5108 RES
A
owner.
11
5107 RES
B
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
10
2
3
4
5
6
8
7
A
F123 E2
F124 E2
F125 B3
F126 A2
I100 A6
I101 C6
I102 C6
I103 C6
I104 D9
I105 D5
I106 D7
I108 D6
I109 A8
c001 E2
c002 E2
B
C
D
E
F
G
H
9
I
STUFFING DIVERSITIES FOR DC/DC INTERFACE AMBI 2K9
See the stuffing diversities table in the case of components marked with one star (*)
DC/DC INTERFACE
1101
1M85
5103/5104
5105/5106
VLED1
VLED2
CHN
SETNAME
CLASS_NO
3104 328 58341
3104 328 58351
J
3104 328 58361
3104 328 58371
in
out
out
out
in
out
out
out
in
out
out
out
out
24V
16V
in
in
out
12V
12V
08-06-19
1
16V
16V
08-08-06
2
12V
16V
08-10-23
3
DC-DC INTERFACE
1
2
3
4
5
6
7
MGr
8
08-06-19
2
08-08-06
3
08-09-18
4
08-10-23
5
NAME Peter Van Hove
CT
3104 313 6325
AMBI 2K9
1
CHECK ********
SUPERS.
DATE
9
3
08-06-06
**
C
10
130
1
J
08-12-06
A3
***
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_600_090305.eps
090305
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 68
Interface Ambilight: Dual DC-DC
1
2
3
4
5
6
9
8
7
10
12
11
13
A
A
2
1
3
4
5
6
7
2200 A4
2201 A4
2202 A5
2203 A5
2204 B3
2205 B6
2206 B1
2207 B2
2208 B7
2209 B7
2210 B8
2211 C3
2212 C4
2213 C6
2214 C3
2215 C6
2216 C2
2217 C7
2218 D1
2219 D2
2220 D7
2221 D3
2222 D5
2223 D8
2224 D8
3200 A3
3201 A6
3202 B3
3203 B6
3204 B3
3205 B6
3206 D3
3207 D2
3208 D7
3209 D5
3210 D3
3211 D3
3212 D6
3213 D6
5200 B2
5201 B7
6200 B2
6201 B7
7200 B4
9201 B5
9202 C4
F200 B2
F201 C7
F202 D3
F203 B5
F204 B4
F207 C4
I200 A3
I201 A6
I204 B2
I205 B6
I206 B6
I208 B3
I209 B6
I210 C6
I211 C3
I212 C3
8
DUAL DC-DC
+24VF
B
A
2202
220n
2203
100u 35V
RES
220n
2200
100u 35V
2201
A
I200
3200
I201
RES
3201
VSW
D
**
9202
1n0
2211
**
VIA2
I211
F207
E
2216 RES
*
I209
*
I210
*
GND_HS
C
RES
2217
I212
F201
+12V
3K3
*
2220
*
33K
3213
3K3
1%
3212
D
*
10u
2223
*
F202
10u
VLED1
2224
2222 RES
22n
*
47K
1%
10u
RES
3K3
3209
*
I213
I214
RES 2221
22n
3208
22n
33K
3211
**
I215
3210
**
3K9
1%
**
68K
1%
4u7
4u7
D
2219 RES
2218 RES
22n
3207
RES 3206
+16V
F
B
220u 25V
*
RES
22u
I216
+12V
RES
2210
16
17
18
19
20
21
22
23
24
25
26
10u
22u
I206
*
6201
*
(VLED1)
*
2209
5201
2208
I205
15
4
4u7
GND
2212
2214
C
1n0
**
47n
SS24
ILIM2
SEQ
BP
F203
13
12
6
8
10R
9
10
11
BOOT2
SW2
EN2
FB2
3205
I217
I208
Φ
*
6R8
1n0
10R
**
3204
**
SS24
10u
6200
**
4u7
2206
**
100u 35V
2207
B
BOOT1
SW1
EN1
FB1
3203
2213
2
3
5
7
I204
+16V
PVDD2
*
1n0
F204
47n
6R8
PVDD1
2205
2215
**
14
7200
TPS54283PWP
2204
9201
**5200
F200
6R8
**
1
6R8
3202
(VLED2)
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
7200 : TPS54383 in case of 16V or dual dc-dc converter
G
The components marked with one star (*) belong to the 12V versions (3104 328 58351, 3104 328 58371).
E
E
The components marked with two stars (**) belong to the 16V versions
(3104 328 58331, 3104 328 58341, 3104 328 58361, 3104 328 58371).
H
1
3
2
4
5
6
7
I213 D5
I214 D4
I215 D3
I216 B5
I217 B4
B
C
D
E
F
G
H
8
I
I
CHN
SETNAME
1
CLASS_NO
DC-DC INTERFACE
J
08-06-19
1
08-08-06
2
08-10-23
3
NAME Peter Van Hove
CHECK
1
2
3
4
5
7
6
8
3104 313 6325
AMBI 2K9
SUPERS.
DATE
9
3
08-06-09
130
C
10
08-06-19
2
08-08-06
3
08-09-18
4
08-10-23
5
08-12-06
2
J
A3
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_601_090305.eps
090305
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 69
Interface Ambilight: Microcontrollerblock
1
2
3
4
6
5
8
7
10
9
12
11
16
15
14
13
18
17
20
19
A
A
1
2
4
3
5
6
7
8
9
10
1300 E2
1301 H5
1302 C4
2300 A3
2301 A4
2302 A5
2303 A4
2304 B8
2305 B10
2306 B9
2307 B10
2308 D4
2309 D5
2310 F6
2311 F7
2312 F7
2313 F7
2314 F7
2315 F7
2316 F8
2318 G2
2319 G6
2320 H5
2321 H4
2322 H4
2323 H4
2324 H4
3300-2 D5
3300-3 D7
3300-4 D7
3301-1 D6
3301-2 E5
3301-3 E6
3301-4 D7
3302-1 D7
3302-2 D6
3302-3 E6
3302-4 D6
3303-1 E6
3303-2 D6
3303-3 E6
3304-1 D6
3304-2 D7
3304-3 D7
3304-4 D7
3305-1 E7
3305-2 G8
3305-3 G9
3305-4 G8
3306-1 E8
3306-2 E8
3306-3 E8
3306-4 E8
3307-1 E8
3307-2 F8
3307-4 F8
3308-1 F8
3308-2 F8
3308-4 F8
3309-1 F8
3309-4 F8
3310 A10
3311 A8
3312 A10
3313 B8
3314 B8
3315 B10
3316 B10
3317 B8
3318 C10
3319 C8
3320 C5
3321 C5
3322 D5
3323 D5
3324 D7
3325 D6
3326 D6
3327 D6
3328 E5
3329 E5
3330 E8
3331 E8
3332 E3
3333 F2
3334 G5
3335 G5
3336 G6
3337 G6
3338 E8
3339 F1
7300-1 B9
7300-2 A10
7301 A4
7302 E3
7303 F2
9300 E3
9301 F3
9302 F3
11
B
MICROCONTROLLER
3310
RES
7301
LD2985BM18R
7
6
4
RES
10K
10n
3314
3313
2304
F302
+3V3
F303
2305
3
RST
GND
CD
NC
5
1K5 1%
2307
10n
3316
4
10K
6
10K
7
10K
5
10K
8
10K
8
10K
5
10K
7
10K
5
10K
7
10K
3
3300-3
2
3304-2
4
3304-4
2
3302-2
4
3302-4
2
3303-2
RES
10K
1
3301-1
1
3304-1
4
3301-4
3324
8
10K
5
10K
6
10K
8
10K
1
3302-1
4
3300-4
3
3304-3
1
3305-1
10K
3327
10K
I305
3329
3
3301-3
3
3302-3
1
3303-1
3
3303-3
3326
I310
2
7 3300-2
10K
10K
6
10K
6
10K
8
10K
6
10K 3325
RES
10K
100p
2309
31
I316
I319
I321
6
2
1
4
1
7
8
5
8
4
2
4
2
5
7
5
7
3308-1 1
3309-4 5
3309-1 8
I320
I300
100R
100R
100R
100R
100R
100R
100R
100R
100R
100R
100R
100R
CONTROL1
PWM-CLOCK-BUF
SPI-CLOCK-BUF
SPI-DATA-RETURN
SPI-DATA-OUT
SPI-LATCH1
SPI-LATCH2
PWM-CLOCK-BUF
TEMP-SENSOR
EEPROM-CS
BLANK-BUF
PROG
F320
8
100R
4
1 100R
100R
E
TEMP-SENSOR
CONTROL2
I302
F
SCL
SDA
I307
UD-MD
I322
F309
F310
F311
F312
F313
3334
22R
3335
3
100p
10K
4
owner.
G
5
1
100n
K
3
I308
2318
9305 RES
F317
IN
3333
1K0
3339
2
I315
I318
I317
100p
2316
6
F
7303
NCP303LSN10T1
27
I313
I314
100p
2315
F308
3306-3
RES 3330
3331
3306-2
3306-1
3306-4
3307-1
3338
3307-4
3307-2
3308-4
3308-2
I311
I312
100p
2314 RES
+3V3
F307
I306
100p
2313
+3V3
4
13
14
18
21
22
23
24
28
29
30
35
36
37
41
44
45
46
47
48
1
2
3
32
33
34
38
39
8
9
10
15
16
100n
2312
RES 9302
RES 9303
J
26
10K
RES
9301
VSSA
MICROCTRL
100p
2311
+3V3
C
D
2310
3332
I
Φ
P0.0|TXD0|MAT3.1
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
P0.5|MISO0|MAT0.1
RTXC1
P0.6|MOSI0|CAP0.2
RTXC2
P0.7|SSEL0|MAT2.0
P0.8|TXD1|MAT2.1
RTCK
P0.9|RXD1|MAT2.2
P0.10|RTS1|CAP1.0|AD0.3
VBAT
P0.11|CTS1|CAP1.1|AD0.4
P0.12|DSR1|MAT1.0|AD0.5
P0.13|DTR1|MAT1.1
DBGSEL
P0.14|DCD1|SCK1|EINT1
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
RST
P0.17|CAP1.2|SCL1
P0.18|CAP1.3|SDA1
P0.19|MAT1.2|MISO1
P0.20|MAT1.3|MOSI1
P0.21|SSEL1|MAT3.0
P0.22|AD0.0
P0.23|AD0.1
P0.24|AD0.2
P0.25|AD0.6
P0.26|AD0.7
P0.27|TRST|CAP2.0
P0.28|TMS|CAP2.1
P0.29|TCK|CAP2.2
P0.30|TDI|MAT3.3
P0.31|TDO
VDD_1V8 VDD_3V3
VDDA
X2
100p
2308
20
25
RES 9300
VSS
X1
42
12
17
40
1300
E
16M9
11
7
19
43
7302
LPC2103FBD48
3301-2 2
3328
3322
7
10K
F306
D
H
3318
10K RES
5
B3B-PH-SM4-TBT(LF)
G
I304
1
1K8 1%
RES
3319
10K
F305
4
100R
1
2
3
RES
F304
100R
3323
F
10K
3320
3321
RES
1302
47K
2
+3V3
+3V3
C
B
10n RES
3315
8
1K5 1%
RES
3317
7300-1
LM393PT
F316
+3V3
100n
2306
C300
B
E
4
3305-4
2
5
10K
7
3305-2
10K
3
3305-3
6
10K
G
+3V3
F314
F315
10K
10K
3336
100p
3337
2319
H
100n
2324
100n
100n
2323
H
100n
2322
3
4
+1V8
RES
1301
SKHUBHE010
9307
+3V3
100n
L
2320
100R
1
2
I309
2321
is prohibited without the written consent of the copyright
1K5
3312
1%
1%
3311
5
+3V3
All rights reserved. Reproduction in whole or in parts
A
7300-2
LM393PT
F301
10n
2
D
100K RES
8
COM
-T 10K
4
BP
1K5
I303
4u7
INH
+3V3
+3V3
+1V8
2302
1u0
2300
3
5
OUT
2303
C
IN
2301
1
+3V3
+3V3
F300
100n
A
M
1
2
3
4
5
6
7
8
9
10
9303 F3
9305 G1
9307 H4
C300 B8
F300 A5
F301 A8
F302 A10
F303 B11
F304 C4
F305 C4
F306 D4
F307 F3
F308 F3
F309 G6
F310 G6
F311 G8
F312 G8
F313 G8
F314 G5
F315 H4
F316 C9
F317 F1
F320 E9
I300 E9
I302 F9
I303 A4
I304 C10
I305 E6
I306 E7
I307 G6
I308 G2
I309 G5
I310 D5
I311 E7
I312 E7
I313 E7
I314 F7
I315 F7
I316 F8
I317 F6
I318 F7
I319 F5
I320 F8
I321 F6
I322 G5
B
C
D
E
F
G
H
I
J
K
L
M
11
N
N
O
O
CHN
SETNAME
CLASS_NO
DC-DC INTERFACE
P
08-06-19
1
08-08-06
2
08-10-23
3
AMBI 2K9
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3104 313 6325
15
3
SUPERS.
DATE
16
08-06-09
130
C
17
1
08-06-19
2
08-08-06
3
08-09-18
4
08-10-23
5
08-12-06
P
A2
3
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_602_090305.eps
090410
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 70
1M59
Layout DC/DC Interface Ambilight
Personal Notes:
1302 5201
1M85
2208
2209
3338
2219
2300
5200
3331
2310
2322
9102
3307 9101
2316
3308
2323
2311
3306
3309
2206
2315
7301
2303
2321
2319
3324
3326
2312
2223
6200
2301
2302
1301
9201
9104
9103
2224
1101
2218
9202
5102
1100
1M90
2200
2210
7200
2202
2201
2203
2220
6201
1M84
2207
F115
2108
F108
F102
F103
F106
F109
c001
I302
F113
F101
F119
F116
F105
F111
I300
F110
F126
F112
F304
2212
2306
3317
3319
F207
3209
I104
I216
I212
3103
I102
3206
2204
2221
I214
F204
I204
F123
F107
5107
I200
5108
I211
I208
5100
7100
I108
I215
3204
3200
3202
3211
2214 2211
3310
3318
2305
3315
F104
3210
F314
I304
F316
2102
3104
2104
3108
F303
7300
I103
2106
2105
2216
2100
F301
2304
3314
3311
I309
3105
3106
3107
2107
F302
3316
2307 3312
F125
C300
3313
I316
F200
I105
I109
5101
2109
F114
F315
6100
3207
F317
3112
2101
I100
I101
3301 2324 9307
3208
F308
3303
I319
I201
2205
3212
I106
F320
I307
2313
3325
3329
3327
3328
2320
3335
3205
F203
3213
I308
F120
2217
3333
F309
F300
I320
I322
I318
7303
3111
I315
I314
I321
2222
I217
I303
3337
3336
9301
I209
I213
F201
I206
1300
2318
3102
2103
F311
F305
I313
I310
7302
I205
3201
3203
2308 2309
F313
F310
2314
5104
2215 2213
F202
F312
I317
3302
F118
I210
3322 3323
3334
3305
I306
3304
5105
3320
3321
3330
F306
I311
I312
F117
3110
5103
c002
3300
I305
5106
3339
9305
9302
3332
9300
9303
3109
F122
F307
3101
3100
F124
F121
10000_012_090121.eps
090121
31043136325.5
18310_550_090309.eps
090309
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 71
6 LED Low-Pow: Microcontroller Block Liteon
1
3
2
A
4
5
2
1
4
3
8
7
6
9
10
6
5
8
7
13
12
11
14
9
16
15
10
11
12
19
18
17
13
MICROCONTROLLER LITEON
B
3134
+3V3
7101
LD2985BM18R
F106
RES
10n
3137
10K
2105
3111
10n
3139
1K5 1%
100n
4
8
C
5
10K
10K
6
10K
7
10K
5
10K
8
10K
8
7
10K
5
10K
7
10K
5
CD
NC
4
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
2
4
3102-4
3103-1
1
3
3102-3
3101-3 3
3102-2
5
10K
6
10K
8
10K
4
3101-4
3112
8
10K
1
10K
3115
3
3114
3106-3
3105-1
3102-1 1
RES
10K
3104-1 1
3106-2 2
4
3
1
3105-3
3106-1
3104-3 3
3104-2 2
3116
10K
5
1
2
3
1
8
7
6
8
2
4
2
4
7
5
7
5
3126-1
1
8
3127-1
3127-4
1
4
8
5
I124
100R
100R
100R
100R
100R
100R I125
100R
100R
100R
100R
100R
100R
I126
100R
E
CONTROL-1
PWM-CLOCK-BUF
SPI-CLOCK-BUF
SPI-DATA-RETURN
SPI-DATA-IN
SPI-LATCH
SPI-LATCH-2
TEMP-SENSOR
EEPROM-CS
BLANK-BUF
PROG
TEMP-SENSOR
F
CONTROL-2
SCL
SDA
100R
100R
100p
100p
2131
100p
2126
100p
2124 RES
100p
2123
100p
2122 RES
100p
2117
100p
2116
100p
2115
4
UD-MD
I111
I110
I113
I114
I115
3130
3131
F112
9106
RES
100n
2112
9119
10K
4
7
3103-2
22R
G
5
3103-4
2
100R
VLED1
3105-4
7
10K
100p
2110
100p
3117
7
19
43
5
+3V3
2114 RES
10K
1
100n
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
RST
GND
3104-4 4
10K
9121 RES
3
IN
3120
10K
3119
1u0
2130
7110
NCP303LSN10T1
6
3103-3
3
6
10K
10K
+3V3
VLED2
+3V3
15 16
F103
+1V8
100n
2113
100n
100n
2121
H
2119
H
F104
+3V3
27
100n
2120
L
10K RES
10K
+3V3
VLED1
4
F102
10K
3132
RES 9103
9104
RES
2111
K
3141
1
D
3124-4
3128
3129
3124-1
3124-2
3124-3
3125-1
3142
3125-2
3125-4
3126-2
3126-4
100p
3133
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
1M2A
G
10K
RES
9102
+3V3
13
14
18
21
22
23
24
28
29
30
35
36
37
41
44
45
46
47
48
1
2
3
32
33
34
38
39
8
9
10
15
16
2118 RES
+3V3
26
31
2109
3118
F109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
25
9101
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
2
owner.
M
1
2
3
4
5
6
7
8
9
10
11
12
1101 E4
1105 B5
1M1A C1
1M2A G1
1M83 A1
1M84 E1
2101 A6
2102 A7
2103 A8
2104 B7
2105 B10
2106 B13
2107 B11
2108 B12
2109 D7
2110 D7
2111 G4
2112 H7
2113 H7
2114 F9
2115 F9
2116 F9
2117 F9
2118 H8
2119 H6
2120 H6
2121 H6
2122 F9
2123 F10
2124 F10
2125 B3
2126 F10
2127 B1
2128 B1
2129 B2
2130 F2
2131 F10
3101-2 D7
3101-3 D9
3101-4 E9
3102-1 D9
3102-2 D9
3102-3 E9
3102-4 D9
3103-1 E9
3103-2 G10
3103-3 G11
3103-4 G10
3104-1 D8
3104-2 E8
3104-3 E8
3104-4 D9
3105-1 E9
3105-2 D8
3105-3 E8
3105-4 D8
3106-1 E8
3106-2 D8
3106-3 E8
3107 C7
3108 C7
3109 D7
3110 D7
3111 B10
3112 D9
3113 D8
3114 E8
3115 E8
3116 E8
3117 E7
3118 E5
3119 F4
3120 F5
3123 C11
3124-1 E11
3124-2 E11
3124-3 E11
3124-4 E11
3125-1 F11
3125-2 F11
3125-4 F11
3126-1 F11
3126-2 F11
3126-4 F11
3127-1 F11
3127-4 F11
3128 E11
3129 E11
3130 G8
3131 G7
3132 H8
3133 H8
3134 A13
3135 A11
3136 A12
3137 B11
3138 B13
3139 B12
3140 C11
3141 C13
3142 F11
7101 A7
7102 E6
7110 F4
7116-1 B11
A
7116-2 A12
9101 E5
9102 F5
9103 F5
9104 F5
9106 H8
9107 A5
9108 A5
9109 A5
9110 B5
9111 A3
9112 B2
9113 B3
9114 B2
9119 H6
9121 G4
C140 B10
F101 A8
F102 F5
F103 H7
F104 F5
F105 D7
F106 B12
F107 C7
F108 D7
F109 G3
F112 G8
F116 A10
F117 B13
F118 C11
F120 A1
F121 A1
F122 A1
F123 A1
F124 B1
F125 B1
F126 B1
F127 B1
F128 B1
F129 B1
F130 B1
F131 B1
F132 B1
F133 E1
F134 F1
F135 E1
F136 F1
F137 F1
F138 F1
F139 F1
I110 G8
I111 G8
I113 G10
I114 G10
I115 G10
I124 E11
I125 E11
I126 F11
B
C
D
E
F
G
H
I
J
K
L
M
13
N
N
1X03
REF EMC HOLE
O
O
SETNAME
5
4
3
2
CHN
1
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
F133
F135
F136
F139
F137
VSSA
P0.0|TXD0|MAT3.1
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
P0.5|MISO0|MAT0.1
RTXC1
P0.6|MOSI0|CAP0.2
RTXC2
P0.7|SSEL0|MAT2.0
P0.8|TXD1|MAT2.1
RTCK
P0.9|RXD1|MAT2.2
P0.10|RTS1|CAP1.0|AD0.3
VBAT
P0.11|CTS1|CAP1.1|AD0.4
P0.12|DSR1|MAT1.0|AD0.5
P0.13|DTR1|MAT1.1
DBGSEL
P0.14|DCD1|SCK1|EINT1
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
RST
P0.17|CAP1.2|SCL1
P0.18|CAP1.3|SDA1
P0.19|MAT1.2|MISO1
P0.20|MAT1.3|MOSI1
P0.21|SSEL1|MAT3.0
P0.22|AD0.0
P0.23|AD0.1
P0.24|AD0.2
P0.25|AD0.6
P0.26|AD0.7
P0.27|TRST|CAP2.0
P0.28|TMS|CAP2.1
P0.29|TCK|CAP2.2
P0.30|TDI|MAT3.3
P0.31|TDO
VDD_1V8 VDD_3V3
VDDA
MICROCTRL
42
1M84
Φ
VSS
X1
X2
17
40
16M9
1101
OUT
12
2
7 3101-2
10K
10K
6
10K
6
10K
8
10K
6
10K 3113
RES
10K
100R
15 16
3105-2 2
F108
15 16
3123
10K
F105
VLED2
11
J
3
F107
VLED1
VLED2
RES
8
3140
EEPROM-CS
TEMP-SENSOR
PROG
10K
3107
3108
+3V3
47K
2
+3V3
+3V3
E
F
B
10n RES
3138
1K8 1%
RES
+3V3
SDA
CONTROL-1
CONTROL-2
F138
F134
7116-1
LM393PT
F118
SCL
2108
+3V3
1.5A T
7102
LPC2103FBD48
I
F117
2107
VLED1-F
1K5 1%
RES
VLED1
G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7
6
+3V3
C140
33p
2125
9112
9114
10u 35V
15 16
1105
D
H
3136
5
2106
VLED2
3109
F
1%
1%
F116
VLED1
100R
3110
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7116-2
LM393PT
1K5
+1V8
1M1A
E
A
100K RES
4
BLANK
EEPROM-CS
TEMP-SENSOR
PROG
3135
4
BP
COM
+3V3
+3V3
4u7
INH
100n
3
2102
SPI-LATCH
PWM-CLOCK
5
OUT
10n
9109
9110
IN
2104
CONTROL-1
CONTROL-2
1
+3V3
1u0
SPI-CLOCK
SDA
2101
9107
9108
-T 10K
9113
RES
SCL
SPI-DATA-RETURN
2
+3V3
1u0
2128
B
SCL
SPI-DATA-IN
SDA
CONTROL-1
CONTROL-2
9111
RES
10u 35V
2129
D
F120
F121
F122
F123
F124
F125
F126
F127
F128
F129
F130
F131
F132
2127
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F101
1K5
IN
1M83
2103
A
20
1
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
2
2008-10-27
3
2K9
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8204 000 8857
15
16
2
2008-08-08
3
2008-10-27
P
SUPERS.
DATE
2008-06-10
3
2008-06-02
130
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_610_090305.eps
090410
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 72
6 LED Low-Pow: Microcontroller Block Liteon
1
2
1
A
4
3
2
3
7
6
5
4
8
9
5
11
10
6
7
12
14
13
9
8
15
10
16
11
18
17
12
13
MICROCONTROLLER LITEON
INPUT BUFFER
A
B
+3V3
100p
2217
100R
EN
7
33p
2201
14
100n
10K
1
RES
1K0
9209
7214
F202
1
D
3
D
Q
(64K)
7201-4
74HCT125PW
C
S
3204
7
HOLD
+3V3
12
+3V3
10K
W M95010-WDW6
4
+3V3
13
RES
1K0
3220
11
3209
GND
27R
EN
C
100p
10K
3203
6
2
14
2
Φ
7
5
1
33p
B
8
VCC
33p
3
+3V3
3219
3
3207
7212
PDTC144EU
+3V3
2209
7201-1
74HCT125PW
2
2202
7209
PDTC144EU
B
3210
2214
+3V3
10K
3213
C
A
2218
+3V3
C
9212 RES
E
3223
100p
100R
EN
2219
F207
+3V3
9213
D
D
9214 RES
+3V3
7201-3
74HCT125PW
14
F
G
8
10
F208
3212
100R
7
EN
100p
2220 RES
3121
9
100R
E
E
20
19
H
2201 B8
2202 C8
2203 D8
2209 B2
2210 G6
2211 I6
2214 A6
2215 F7
2216 F7
2217 B12
2218 C12
2219 D12
2220 E9
3121 D9
3203 B5
3204 B7
3205 C5
3207 B9
3209 C9
3210 B3
3211 C9
3212 D11
3213 B3
3214 H6
3215 H6
3216 H6
3217 H6
3218 H6
3219 B11
3220 C11
3221 H11
3222 I8
3223 C11
3224 H11
6216 I8
7201-1 A10
7201-2 C10
7201-3 D10
7201-4 B10
7209 B2
7210 C2
7212 B3
7214 B6
7215 G7
9208 A10
9209 B9
9210 B10
9211 C9
9212 C10
9213 D9
9214 D10
F202 B3
F203 C5
F204 H6
F205 B10
F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
F211 G9
F212 G9
F213 H9
F214 H9
F215 H9
A
B
C
D
E
F
G
H
F
F
I
2216
2215
1u0
100n
3216
4
5
24
H
100R
L
3214
26
+3V3
10K
XLAT
SCLK
SIN
SOUT
XHALF
1
XERR
VIA
I
+3V3
+3V3
F209
H
L
23
6216
33p
2211
GND GND_HS
K
F213
3K3
3
IREF
F212
3221
27
3215
1K2
MODE
3K3
F204
3224
100R
3222
6
3217
F211
470R
K
BLANK
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
J
G
F210
SML-310
2
0
1
2
3
4
5
6
7
OUT 8
9
10
11
12
13
14
15
GSCLK
30
31
32
33
25
M
Φ
VCC
LED DRIVER
PWM CONTROL
G
29
J
28
7215
TLC5946PWP
owner.
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
I
I
M
+3V3
1
N
2
3
4
5
6
7
8
9
10
11
12
13
N
O
O
1
DRIVER 6LED LITEON
P
2008-08-08
2
2008-10-27
3
NAME
2
3
4
5
6
7
8
9
10
11
12
13
14
P
A2
SUPERS.
CHECK
1
8204 000 8857
2K9
15
DATE
16
C
17
18
19
20
18310_611_090305.eps
090410
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 73
6 LED Low-Pow: LED Liteon
4
3
2
1
1
A
5
2
6
3
4
9
8
7
5
10
11
7
6
12
14
13
9
8
16
15
10
11
17
18
19
13
12
LED LITEON
B
A
A
VLED1-F
VLED2
C
B
GREEN
5
RED
6
BLUE
4
GREEN
2
5
RED
1
6
BLUE
3
9305-2
5
RED
2
4
9305-4
5
5
RED
1
6
BLUE
1
1
9305-1
8
6
BLUE
2
8
9313-1
1
9312-4
9312-3
6
5
GREEN
4
7004
LTW-E500T-PH1
4
3
9310-1
1
8
9310-4
3
GREEN
GND_HS
9310-2
7
2
3
2
7003
7
GREEN
7
7
2
4
GND_HS
GND_HS
2
7002
LTW-E500T-PH1
3
B
3
8
9318-1
1
5
RED
2
5
9318-4
4
6
BLUE
1
3 9303-3
6
GREEN
2 9315-2
7
4 9303-4
5
RED
4 9315-4
5
GND_HS
GND_HS
G
R
C
BLUE
GND_HS
G
7
C
4
7
E
7001
LTW-E500T-PH1
7000
LTW-E500T-PH1
7
9301
9309-2
D
4
VLED2
7
VLED1-F
5
B
R
B
B
F
9320-1 8
9320-4 5
9320-2 7
8
3335
9319-1
390R
3345
1
4
2
1
2
390R
3342
3346
560R
E
3339
4
G
390R
1
1K5
9306-1
560R
9306-4
1K5
3344
D
5
3341
3340
G
3336
8
D
R
9304-2
7
3354
560R
3311
390R
3348
1K5
3312
560R
3358
390R
1K5
560R
3357
390R
3349
3353
560R
1K5
E
3360
H
560R
3315
3384
VLED1-F
VLED1-F
3334
F308
F
3303
1K0
Place jumper 9325, 9326, 9327
7315
BC847BW
F348
8
9311-1
F329
1
VLED1-F
H
5
10K
3306
10K
9326
F328
F303
G
1K5
6
if VLED < 17V
10K
3304
Place jumper 9314, 9316, 9317
10K
3325
560R
1K5
3323
F302
3326
3366
1K5
3321
9311-4
1K5
3320
1K5
3322
if VLED < 17V
K
L
3363
560R
1K5
3391
G
560R
3364
1K5
3390
J
1K5
F326
1K5
3389
owner.
H
3308
F330
10K
1K0
9327
7316
BC847BW
3309
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
1K5
3388
10K
3387
560R
7317
BC847BW
10K
F
3301
560R
10K
3331
I
1K5
3317
F325
F307
9311-3
1K5
3370
3362
4
560R
1K5
3316
3
3369
1K5
3385
M
I
I
N
1
2
4
3
5
6
7
8
9
10
11
12
20
3301 F9
3302 F9
3303 F9
3304 G9
3305 G9
3306 H9
3307 H9
3308 H9
3309 I9
3310 D12
3311 D12
3312 E12
3313 E12
3314 E12
3315 E12
3316 E12
3317 F12
3318 F12
3319 F12
3320 F12
3321 G12
3322 G12
3323 G12
3325 G4
3326 H4
3327 H4
3328 G4
3330 I4
3331 F4
3332 F4
3333 H4
3334 F4
3335 D12
3336 D2
3337 D2
3338 D1
3339 D2
3340 D1
3341 D1
3342 E2
3343 D1
3344 D1
3345 D12
3346 E1
3347 D1
3348 E12
3349 E1
3350 E1
3351 E12
3352 E1
3353 E1
3354 D13
3355 E1
3356 E1
3357 D13
3358 E13
3359 E13
3360 E13
3361 E13
3362 E13
3363 F13
3364 F13
3365 F13
3366 F13
3367 G13
3368 G13
3369 F1
3370 F1
3371 F1
3372 F1
3373 F1
3374 G1
3384 E1
3385 F1
3386 F1
3387 F1
3388 F1
3389 F1
3390 G1
3391 G1
7000 C2
7001 C3
7002 C4
7003 C6
7004 C8
7005 C11
7305 G4
7306 H5
7307 F4
7315 G9
7316 H10
7317 F9
9301 C1
9302 C1
9303-1 C10
9303-3 C10
9303-4 C10
9304-1 E10
9304-2 E10
9304-4 E10
9305-1 C6
9305-2 C6
9305-4 C6
9306-1 D5
9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
9309-4 B6
9310-1 B8
9310-2 B8
9310-4 B8
9311-1 H13
9311-3 H13
9311-4 H12
9312-1 B10
9312-3 B10
9312-4 B10
9313-1 B12
9313-2 B12
9313-4 B12
9314 G5
9315-1 C12
9315-2 C12
9315-4 C12
9316 H5
9317 F5
9318-1 C8
9318-3 C8
9318-4 C8
9319-1 D9
9319-3 D9
9319-4 D9
9320-1 D7
9320-2 D7
9320-4 D7
9325 F10
9326 G10
9327 H10
F302 G5
F303 G4
F304 H5
F305 H5
F307 F5
F308 F4
F325 F10
F326 F9
F327 G10
F328 G9
F329 H10
F330 H10
F340 D1
F341 D1
F342 D1
F343 D2
F344 D12
F345 D12
F346 D13
F347 G12
F348 G13
F349 G13
A
B
C
D
E
F
G
H
I
J
K
L
M
N
13
O
O
CHN
SETNAME
1
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
2
2008-10-27
3
2K9
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8204 000 8857
15
16
2
2008-08-08
3
2008-10-27
P
130
3
SUPERS.
DATE
2008-06-10
2008-06-02
C
17
A2
3
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_612_090305.eps
090305
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 74
F108
3335
3345
3348
3351
3317
3316
3315
3313
3312
3311
3310
3314
3320
3319
3318
3323
3322
3321
7005
3309
3308
3307
9311
9304
9303
9319
9327
7316
3303
3302
3301
7317
9325
9326
7315
3306
3305
3304
7004
2127
3111
2105
3137
3140 3135
7116
3123
9312
9320
9310
3113
F130
F107
F215
9318
7212 7210
7209
3134
3141
9315
F120
F132
F105
F123
F127
F349
F214
1M2A
F139
F209
F213
F104
F109
I124
F137
1M1A
F126
F212
F101
I126
F344
F106
F345
F116
F347
7214
2118
2115
3112
3105
F135
F346
F348
2214
3203 3205
3125
C140
2107
3213
3204
7102
9104
9103
3118
9101
2114
3101
2131
2124
2121
3104
2113
2123
3126
3138 3136
2106 3139
2108
2209
3210
3130
2120
7110
7003
I115
3124
3131
2112
3116
9119
1M84
2111
2117
2116
3115
2126
I111
9106
2119
3127
2122
3106
I114
3142
7002
1101
I113
9313
3120
3119
9121
3117
3114
I110
3103
3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108
3110
3107
9102
2102
2103
3132
3133
2104
7101
3331
9309
3332
9317
9308
9307
9305
3330
3333
3327
7306
9306
3326
3328
3325
2210
7305
3211
2219
3217
9314
7001
2216
3214 2215
3215
3223
9213
3207
2217 9209
9316
3222
7307 3334
7215
3221
3224
2101
3218
9108
7201
9208
3219
2203
9212
3128
3129
3102
2125
6216
2211
3216
1105
2130
2129 2128
9114
9110
3121
2220
2201
3385 3389
3384 3390
3356 3391
3350 3386
3347 3387
3344 3388
3341 3353
9301
3338 3374
3340 3369
3343 3373
3346 3372
3349 3371
3352 3370
3355
3337
3336
2218
3220 3212
9211
3209 9210 9214
7000
3342
3339
9302
9107
2202
1M83
9109
9112
9111
9113
Layout 6 LED Low-Pow
F122
F128
F326
F134
F328
F202
F133
F329
F325
F327
F118
F203
F136
I125
F103
F112
F210
F305
F102
F206
F340
F208
F205
F307
F304
F204
F302
F124
F138
F207
F211
F303
F117
F121
F343
F125
F342
F341
F330
F308
F129
F131
18310_551_090309
090309
3104 313 6313.3
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 75
8 LED Low-Pow: Microcontroller Block Liteon
2
1
A
5
4
3
1
6
3
2
8
7
9
5
4
7
6
12
11
10
9
8
15
14
13
10
17
16
11
12
18
13
MICROCONTROLLER BLOCK LITEON
B
3134
+3V3
7101
LD2985BM18R
RES
2105
10K
10n
3137
3111
10n
3139
1K5 1%
100n
4
8
10K RES
C
5
10K
10K
6
10K
7
10K
5
10K
8
10K
8
7
10K
5
10K
7
10K
CD
NC
4
100n
2111
5
1
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
2
4
3102-4
3103-1
1
3
3102-3
3101-3 3
3102-2
5
10K
6
10K
8
10K
4
3101-4
3112
8
10K
1
10K
3115
3
3114
3106-3
3105-1
3102-1 1
RES
10K
3104-1 1
3106-2 2
4
3
1
3105-3
3106-1
3124-4
3128
3129
3124-1
3124-2
3124-3
3125-1
3142
3125-2
3125-4
3126-2
3126-4
4
5
1
2
3
1
8
7
6
8
2
4
2
4
7
5
7
5
3126-1
1
8
3127-1
3127-4
1
4
8
5
I124
100R
100R
100R
100R
100R
100R I125
100R
100R
100R
100R
100R
100R
I126
100R
E
CONTROL-1
PWM-CLOCK-BUF
SPI-CLOCK-BUF
SPI-DATA-RETURN
SPI-DATA-IN
SPI-LATCH
SPI-LATCH-2
TEMP-SENSOR
EEPROM-CS
BLANK-BUF
PROG
TEMP-SENSOR
F
CONTROL-2
SCL
SDA
100R
100R
100p
100p
2131
100p
2126
100p
2123
100p
2124 RES
100p
2122 RES
100p
2117
100p
2116
100p
2115
10K
3104-3 3
3104-2 2
3116
D
UD-MD
I111
I110
I113
I114
I115
3130
3103-4
3131
9106
RES
100n
2112
9119
10K
7
2
F112
G
5
4
3103-2
22R
100R
VLED1
3105-4
7
10K
100p
2110
3117
31
7
19
43
5
+3V3
3104-4 4
10K
9121 RES
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
RST
GND
6
3103-3
3
6
10K
10K
+3V3
VLED2
+3V3
15 16
F103
+1V8
100n
2113
100n
100n
2121
100n
2120
H
2119
H
3
IN
27
10K
7110
NCP303LSN10T1
3120
10K
3119
1u0
2130
1M2A
L
F104
+3V3
4
2114 RES
+3V3
VLED1
2
K
3141
1
2
10K
RES 9103
9104
RES
F102
10K
3132
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
26
10K
RES
9102
100p
3133
+3V3
+3V3
13
14
18
21
22
23
24
28
29
30
35
36
37
41
44
45
46
47
48
1
2
3
32
33
34
38
39
8
9
10
15
16
2118 RES
3118
F109
G
20
25
9101
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
100p
2109
F133
F135
F136
F139
F137
VSSA
P0.0|TXD0|MAT3.1
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
X2
P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
P0.5|MISO0|MAT0.1
RTXC1
P0.6|MOSI0|CAP0.2
RTXC2
P0.7|SSEL0|MAT2.0
P0.8|TXD1|MAT2.1
RTCK
P0.9|RXD1|MAT2.2
P0.10|RTS1|CAP1.0|AD0.3
VBAT
P0.11|CTS1|CAP1.1|AD0.4
P0.12|DSR1|MAT1.0|AD0.5
P0.13|DTR1|MAT1.1
DBGSEL
P0.14|DCD1|SCK1|EINT1
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
RST
P0.17|CAP1.2|SCL1
P0.18|CAP1.3|SDA1
P0.19|MAT1.2|MISO1
P0.20|MAT1.3|MOSI1
P0.21|SSEL1|MAT3.0
P0.22|AD0.0
P0.23|AD0.1
P0.24|AD0.2
P0.25|AD0.6
P0.26|AD0.7
P0.27|TRST|CAP2.0
P0.28|TMS|CAP2.1
P0.29|TCK|CAP2.2
P0.30|TDI|MAT3.3
P0.31|TDO
VDD_1V8 VDD_3V3
VDDA
MICROCTRL
42
1M84
Φ
VSS
X1
17
40
16M9
1101
12
2
7 3101-2
10K
10K
6
10K
6
10K
8
10K
6
10K 3113
RES
10K
100R
15 16
3105-2 2
F108
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RES
1K8 1%
RES
10K
F105
VLED2
15 16
47K
F107
VLED1
11
J
B
10n RES
3138
8
1K5 1%
RES
3140
EEPROM-CS
TEMP-SENSOR
PROG
10K
3107
3108
+3V3
+3V3
VLED2
3
+3V3
3123
+3V3
SDA
CONTROL-1
CONTROL-2
F138
F134
7116-1
LM393PT
F118
SCL
2108
+3V3
1.5A T
E
F
F117
2107
VLED1-F
VLED1
7102
LPC2103FBD48
I
+3V3
C140
33p
2125
9112
9114
10u 35V
2129
10u 35V
15 16
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7
6
2106
G
H
3136
5
F106
1105
3109
F
1%
1%
F116
VLED1
VLED2
100R
3110
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7116-2
LM393PT
1K5
+1V8
1M1A
E
A
100K RES
4
BLANK
EEPROM-CS
TEMP-SENSOR
PROG
3135
4
BP
COM
+3V3
+3V3
4u7
INH
100n
3
2102
SPI-LATCH
PWM-CLOCK
5
OUT
10n
9109
9110
IN
2104
CONTROL-1
CONTROL-2
1
+3V3
1u0
SPI-CLOCK
SDA
-T 10K
9113
RES
9107
9108
2
+3V3
SCL
SPI-DATA-RETURN
2101
SCL
SPI-DATA-IN
SDA
CONTROL-1
CONTROL-2
9111
RES
1u0
2128
D
B
F120
F121
F122
F123
F124
F125
F126
F127
F128
F129
F130
F131
F132
2127
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F101
1K5
IN
1M83
2103
A
M
1
2
3
4
5
6
7
8
9
10
11
12
20
19
1101 E4
1105 B5
1M1A C1
1M2A G1
1M83 A1
1M84 E1
2101 A6
2102 A7
2103 A8
2104 B7
2105 B10
2106 B13
2107 B11
2108 B12
2109 D7
2110 D7
2111 G4
2112 H7
2113 H7
2114 F9
2115 F9
2116 F9
2117 F9
2118 H8
2119 H6
2120 H6
2121 H6
2122 F9
2123 F10
2124 F10
2125 B3
2126 F10
2127 B1
2128 B1
2129 B2
2130 F2
2131 F10
3101-2 D7
3101-3 D9
3101-4 E9
3102-1 D9
3102-2 D9
3102-3 E9
3102-4 D9
3103-1 E9
3103-2 G10
3103-3 G11
3103-4 G10
3104-1 D8
3104-2 E8
3104-3 E8
3104-4 D9
3105-1 E9
3105-2 D8
3105-3 E8
3105-4 D8
3106-1 E8
3106-2 D8
3106-3 E8
3107 C7
3108 C7
3109 D7
3110 D7
3111 B10
3112 D9
3113 D8
3114 E8
3115 E8
3116 E8
3117 E7
3118 E5
3119 F4
3120 F5
3123 C11
3124-1 E11
3124-2 E11
3124-3 E11
3124-4 E11
3125-1 F11
3125-2 F11
3125-4 F11
3126-1 F11
3126-2 F11
3126-4 F11
3127-1 F11
3127-4 F11
3128 E11
3129 E11
3130 G8
3131 G7
3132 H8
3133 H8
3134 A13
3135 A11
3136 A12
3137 B11
3138 B13
3139 B12
3140 C11
3141 C13
3142 F11
7101 A7
7102 E6
7110 F4
7116-1 B11
A
7116-2 A12
9101 E5
9102 F5
9103 F5
9104 F5
9106 H8
9107 A5
9108 A5
9109 A5
9110 B5
9111 A3
9112 B2
9113 B3
9114 B2
9119 H6
9121 G4
C140 B10
F101 A8
F102 F5
F103 H7
F104 F5
F105 D7
F106 B12
F107 C7
F108 D7
F109 G3
F112 G8
F116 A10
F117 B13
F118 C11
F120 A1
F121 A1
F122 A1
F123 A1
F124 B1
F125 B1
F126 B1
F127 B1
F128 B1
F129 B1
F130 B1
F131 B1
F132 B1
F133 E1
F134 F1
F135 E1
F136 F1
F137 F1
F138 F1
F139 F1
I110 G8
I111 G8
I113 G10
I114 G10
I115 G10
I124 E11
I125 E11
I126 F11
B
C
D
E
F
G
H
I
J
K
L
M
13
N
N
1X03
REF EMC HOLE
O
O
SETNAME
5
4
3
2
1
CHN
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
NAME Peter Van Hove
CHECK
2
2008-06-10
2
2008-08-08
3
??
P
3
3104 313 6314.3
1
8204 000 8857
2K9
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
3
SUPERS.
DATE
16
2008-06-02
130
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_650_090508.eps
090507
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 76
8 LED Low-Pow: Microcontroller Block Liteon
1
2
1
A
4
3
2
3
7
6
5
4
8
9
5
11
10
6
7
12
14
13
9
8
16
15
10
11
18
17
12
13
MICROCONTROLLER BLOCK LITEON
INPUT BUFFER
A
+3V3
B
+3V3
14
100p
2217
7
9209
B
Φ
D
2
Q
9210 RES
SPI-DATA-RETURN
(64K)
7201-4
74HCT125PW
+3V3
14
C
7
HOLD
10K
W M95010-WDW6
10K RES
12
SPI-CLOCK
+3V3
3209
4
+3V3
F206
3220
11
13
RES
1K0
27R
EN
SPI-CLOCK-BUF
100p
3204
2218
S
GND
3205
PWM-CLOCK-BUF
9211
C
9212 RES
SPI-CLOCK-BUF
2
BLANK
F207
RES
1K0
3223
6
4
100R
EN
7
33p
2203
3211
+3V3
+3V3
14
E
7201-2
74HCT125PW
5
BLANK-BUF
100p
3
1
100R
EN
7
1
F203
EEPROM-CS-LOCAL
3219
3
1
8
33p
10K
3203
6
33p
2209
2
C
F205
RES
1K0
VCC
5
3
33p
2201
7214
D
+3V3
SPI-DATA-IN
SPI-CS
1
7210
PDTC144EU
100n
10K
SPI-CS
F202
+3V3
EEPROM-CS
PWM-CLOCK
3207
7212
PDTC144EU
3
7201-1
74HCT125PW
2
2202
7209
PDTC144EU
B
3210
2214
+3V3
10K
3213
C
A
9208 RES
2219
+3V3
9213
D
9214 RES
D
SPI-DATA-OUT-FIL
+3V3
7201-3
74HCT125PW
14
F
3121
G
9
8
100R
10
F208
3212
DATA-RETURN-SWITCH
100R
7
EN
100p
2220 RES
SPI-DATA-RETURN
E
E
H
F
A
B
C
D
E
F
G
H
I
+3V3
2216
2215
1u0
100n
28
7215
TLC5946PWP
Φ
3216
100R
SPI-DATA-OUT-FIL
L
3214
26
+3V3
10K
XLAT
SCLK
SIN
SOUT
XHALF
1
XERR
VIA
PWM-G2
F215
PWM-B2
F209
EEPROM-CS-LOCAL
DATA-RETURN-SWITCH
I
H
EEPROM-CS-LOCAL
DATA-RETURN-SWITCH
L
23
6216
33p
2211
GND GND_HS
K
+3V3
+3V3
F214
3K3
4
5
24
PWM-B1
PWM-R2
3221
3
IREF
F212
F213
3K3
1K2
SPI-CLOCK-BUF
SPI-DATA-IN
SPI-DATA-OUT
27
MODE
PWM-G1
3222
F204
BLANK
29
3218 RES
3215
1K2
SPI-LATCH
H
6
100R
PWM-R1
F211
470R
33p
3217
PROG
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SML-310
2
2210
K
0
1
2
3
4
5
6
7
OUT 8
9
10
11
12
13
14
15
GSCLK
30
31
32
33
25
J
G
F210
3224
VCC
LED DRIVER
PWM CONTROL
G
PWM-CLOCK-BUF
BLANK-BUF
M
2201 B8
2202 C8
2203 D8
2209 B2
2210 G6
2211 I6
2214 A6
2215 F7
2216 F7
2217 B12
2218 C12
2219 D12
2220 E9
3121 D9
3203 B5
3204 B7
3205 C5
3207 B9
3209 C9
3210 B3
3211 C9
3212 D11
3213 B3
3214 H6
3215 H6
3216 H6
3217 H6
3218 H6
3219 B11
3220 C11
3221 H11
3222 I8
3223 C11
3224 H11
6216 I8
7201-1 A10
7201-2 C10
7201-3 D10
7201-4 B10
7209 B2
7210 C2
7212 B3
7214 B6
7215 G7
9208 A10
9209 B9
9210 B10
9211 C9
9212 C10
9213 D9
9214 D10
F202 B3
F203 C5
F204 H6
F205 B10
F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
F211 G9
F212 G9
F213 H9
F214 H9
F215 H9
F
I
J
20
19
I
M
+3V3
1
N
2
3
4
5
6
7
8
9
10
11
12
13
N
O
O
CHN
SETNAME
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
3104 313 6314.3
CHECK
2
2008-06-10
2008-08-08
3
??
P
3
NAME Peter Van Hove
1
8204 000 8857
2K9
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
SUPERS.
DATE
16
2008-06-02
130
C
17
2
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_651_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 77
8 LED Low-Pow: LED Liteon
1
3
2
1
A
6
5
4
2
3
7
8
4
9
5
11
10
7
6
12
13
9
8
15
14
10
16
19
13
12
11
18
17
LED LITEON
B
A
A
VLED2
9308
9307
VLED1-F
C
B
RED
6
BLUE
GREEN
2
5
RED
1
6
BLUE
4
GREEN
2
5
RED
1
6
BLUE
3
7
7
GREEN
2
4
9305-4
5
5
RED
1
1
9305-1
8
6
BLUE
9318-3
3
4
GREEN
2
8
9318-1
1
5
RED
1
5
9318-4
4
6
BLUE
GND_HS
6
4
GREEN
2
4 9303-4
5
5
RED
2
4 9315-4
5
1
1 9303-1
8
6
BLUE
1
1 9315-1
8
2 9315-2
3
5
7
9313-4
9313-2
4
9313-1
2
B
3 9303-3
3
1
9312-1
1
8
8
9312-4
9312-3
4
6
5
6
3
3
9310-1
1
8
9310-4
5
9310-2
7
4
4
9309-4
4
7
2
9309-1
5
9309-2
9305-2
GND_HS
GND_HS
GND_HS
2
3
7005
LTW-E500T-PH1
G
R
7
C
GND_HS
GND_HS
G
7
5
4
3
7004
LTW-E500T-PH1
7
GREEN
7003
LTW-E500T-PH1
7
C
4
7002
LTW-E500T-PH1
7001
LTW-E500T-PH1
1
7000
LTW-E500T-PH1
7
R
B
F344
F340
F341
B
F
G
RED-1
9320-2 7
9319-1
9319-4
9319-3
2
1
4
3
6
5
9320-4 5
4
8
9320-1 8
1
3
9306-3
6
RED6
RED6
1
9304-1
8
4
9304-4
5
BLUE6
BLUE6
560R
1K5
3312
560R
3358
390R
3351
1K5
3313
560R
390R
1K5
3314
560R
1K5
3315
560R
1K5
3316
560R
1K5
3317
560R
1K5
3384
VLED1-F
VLED1-F
9325
PWM-B2
Place jumper 9325, 9326, 9327
VLED1-F
if VLED < 17V
VLED1-F
if VLED < 17V
F303
7315
BC847BW
3305
560R
3365
10K
PWM-R1
1K5
3320
560R
1K5
3321
560R
1K5
3322
560R
1K5
3323
560R
F328
VLED1-F
F329
1K0
3367
3368
G
F348
F349
GREEN-2
H
7316
BC847BW
3308
9316
F305
10K
3307
7306
BC847BW
10K
3327
F304
3333
F
3366
F347
PWM-R2
VLED1-F
H
3364
1K5
1K0
3306
1K0
560R
1K5
3319
RED-2
Place jumper 9314, 9316, 9317
9314
3328
K
3326
F327
1K5
3318
6
10K
3325
F302
7305
BC847BW
3362
3363
8
1K5
9326
G
3301
PWM-B1
1K5
3391
10K
3374
560R
BLUE-2
3361
F330
1K0
9327
1K5
3390
1K0
3304
560R
1K0
F326
E
10K
1K5
3389
3373
3302
3303
560R
F308
7317
BC847BW
9317
1K5
3388
3334
10K
560R
3372
7307
BC847BW
10K
1K5
3387
3371
F325
F307
3331
3370
560R
3359
3360
9311-1
1K5
3386
10K
3369
560R
D
3357
9311-3
1K5
3385
10K
560R
J
7
1K5
3311
3
560R
3355
F
390R
9304-2
390R
3345
390R
3348
1K5
3356
3352
H
1K5
3353
2
3354
1
560R
390R
3342
GREEN6
3310
5
560R
3349
1K5
3350
GREEN6
3335
9311-4
3346
4
390R
3339
1
1K5
3347
9306-4
560R
3343
BLUE-1
9306-1
390R
3337
5
1K5
3344
8
3341
560R
560R
E
3336
3338
3340
3332
G
L
R
GREEN-1
D
I
F346
F345
F343
F342
4
E
9302
9301
D
2
7
VLED2
8
B
VLED1-F
10K
3309
10K
3330
GREEN-2
RED-2
M
BLUE-2
PWM-G1
I
PWM-G2
I
N
1
3
2
4
5
6
7
8
9
10
11
12
20
3301 F9
3302 F9
3303 F9
3304 G9
3305 G9
3306 H9
3307 H9
3308 H9
3309 I9
3310 D12
3311 D12
3312 E12
3313 E12
3314 E12
3315 E12
3316 E12
3317 F12
3318 F12
3319 F12
3320 F12
3321 G12
3322 G12
3323 G12
3325 G4
3326 H4
3327 H4
3328 G4
3330 I4
3331 F4
3332 F4
3333 H4
3334 F4
3335 D12
3336 D2
3337 D2
3338 D1
3339 D2
3340 D1
3341 D1
3342 E2
3343 D1
3344 D1
3345 D12
3346 E1
3347 D1
3348 E12
3349 E1
3350 E1
3351 E12
3352 E1
3353 E1
3354 D13
3355 E1
3356 E1
3357 D13
3358 E13
3359 E13
3360 E13
3361 E13
3362 E13
3363 F13
3364 F13
3365 F13
3366 F13
3367 G13
3368 G13
3369 F1
3370 F1
3371 F1
3372 F1
3373 F1
3374 G1
3384 E1
3385 F1
3386 F1
3387 F1
3388 F1
3389 F1
3390 G1
3391 G1
7000 C2
7001 C3
7002 C4
7003 C6
7004 C8
7005 C11
7305 G4
7306 H5
7307 F4
7315 G9
7316 H10
7317 F9
9301 C1
9302 C1
9303-1 C10
9303-3 C10
9303-4 C10
9304-1 E10
9304-2 E10
9304-4 E10
9305-1 C6
9305-2 C6
9305-4 C6
9306-1 D5
9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
9309-4 B6
9310-1 B8
9310-2 B8
9310-4 B8
9311-1 H13
9311-3 H13
9311-4 H12
9312-1 B10
9312-3 B10
9312-4 B10
9313-1 B12
9313-2 B12
9313-4 B12
9314 G5
9315-1 C12
9315-2 C12
9315-4 C12
9316 H5
9317 F5
9318-1 C8
9318-3 C8
9318-4 C8
9319-1 D9
9319-3 D9
9319-4 D9
9320-1 D7
9320-2 D7
9320-4 D7
9325 F10
9326 G10
9327 H10
F302 G5
F303 G4
F304 H5
F305 H5
F307 F5
F308 F4
F325 F10
F326 F9
F327 G10
F328 G9
F329 H10
F330 H10
F340 D1
F341 D1
F342 D1
F343 D2
F344 D12
F345 D12
F346 D13
F347 G12
F348 G13
F349 G13
A
B
C
D
E
F
G
H
I
J
K
L
M
N
13
O
O
CHN
SETNAME
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
3104 313 6314.3
CHECK
2
2008-06-10
2008-08-08
3
??
P
3
NAME Peter Van Hove
1
8204 000 8857
2K9
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
SUPERS.
DATE
16
2008-06-02
130
C
17
3
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_652_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 78
8 LED Low-Pow: LED Drive Liteon
1
2
4
3
6
5
7
8
9
11
10
13
12
14
15
18
17
16
19
20
A
A
1
3
2
4
5
6
8
7
9
1M3A E2
1M85 D2
3536 E9
3537 E9
3538 E7
3539 E9
3540 E7
3541 E8
3542 E9
3543 E7
3544 E8
3546 E7
3547 E8
3549 F7
3550 E8
3552 F7
3553 F8
3555 F7
3556 F8
3569 F7
3570 F7
3571 G7
3572 G7
3573 G7
3574 G7
3584 F8
3585 F8
3586 F8
3587 G8
3588 G8
3589 G8
3590 G8
3591 G8
7006 A5
7007 A7
10
B
LED DRIVE
C
A
A
7006
LTW-E500T-PH1
D
B
7007
LTW-E500T-PH1
GREEN-1
4
GREEN
3
4
GREEN
RED-1
5
RED
2
5
RED
BLUE-1
6
BLUE
1
6
BLUE
2
1
B
7
GND_HS
7
GND_HS
3
E
C
D
E
C
C
F
B
F
1M85
1
2
3
4
5
6
7
8
9
10
11
12
13
14
G
D
H
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
+3V3
G
GREEN-2
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
VLED1
H
VLED2
15 16
1M3A
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J
F
3536
3538
3541
560R
1K5
3544
390R
3537
390R
3539
3540
E
D
RED-2
BLUE-2
560R
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
3543
1K5
3547
560R
3546
1K5
3550
390R
3542
560R
3549
1K5
3553
390R
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
+3V3
560R
E
I
1K5
3556
3552
J
VLED1
560R
VLED2
1K5
3584
3555
560R
15 16
3569
560R
1K5
3586
3570
K
560R
G
3571
1K5
3587
560R
3572
1K5
3588
560R
1K5
3589
3573
560R
L
F
1K5
3585
K
G
1K5
3590
3574
560R
L
1K5
3591
1K5
M
1
2
3
4
5
6
9
8
7
M
10
1X04
REF EMC HOLE
N
N
O
O
CHN
SETNAME
CLASS_NO
2LED + CONNECTOR
P
3104 313 6314.3
2008-05-23
1
2008-08-08
2
2008-10-31
3
2K9
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8204 000 8874
15
16
2008-05-23
2
2008-08-08
3
0
P
1
SUPERS.
DATE
1
2008-04-20
130
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_653_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 79
F326
F134
F328
F202
F133
F329
F325
F327
F118
F203
F136
F308
F330
I125
F103
F112
F210
F305
F122
F128
F102
F206
F340
F208
F205
F307
F304
F204
F302
F121
F138
F207
F211
F303
F117
7007
1M1A
F129
F131
F124
F137
F126
F212
F101
F213
3536
3537
3539
3542
3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
7006
F123
F127
I124
F343
F125
F342
F341
1M2A
F104
F109
1X04
F120
F132
F105
F139
F209
3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
3335
3345
3348
3351
F130
F108
F214
I126
F344
F106
F345
F107
F215
F349
F116
1M3A
F347
9311
9304
9319
9303
3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
7005
2127
7316
F135
F346
F348
1M85
3314
3320
3319
3318
3323
3322
3321
9315
3309
3308
3307
3303
3302
3301
9327
7317
3306
3305
3304
9326
3140 3135
9325
9312
3203 3205
3123
7116
7214
3134
3141
7315
2105
3137
3111
7004
7209
2214
3204
7212 7210
2107
3213
9320
3105
C140
9310
2111
3113
3125
3210
7102
3126
9318
2131
2115
3112
3101
2124
2121
2209
7003
2123
3131
2112
3116
9119
9106
2113
I111
I114
7110
3138 3136
2106 3139
2108
2118
3130
2120
3104
I115
I113
2122
9102
3117
3114
2119
3127
3317
3316
3315
3313
3312
3311
3310
2110 2109
3109
3108
3110
3107
3106
2117
2116
3115
2126
3103
3124
3142
7002
1101
9313
1M84
3120
3119
9121
9104
9103
3118
9101
2114
2102
2103
7101
3332
3331
9308
9307
9309
9317
7307 3334
9305
3330
3333
3327
7306
9306
2210
3326
3328
3325
9316
7305
I110
2104
7215
3215
2216
3214 2215
3217
9314
3222
3132
3133
3102
2125
3128
3129
2101
3218
2219
2129 2128
3221
3224
2211
3216
9213
3207
2217 9209
3223
7001
2220
2201
7201
9208
3219
2203
9212
3211
3121
6216
9113
1105
2130
9114
9110
9302
9107
2202
3385 3389
3384 3390
3356 3391
3350 3386
3347 3387
3344 3388
3341 3353
9108
3338 3374
3340 3369
3343 3373
3346 3372
3349 3371
3352 3370
3355
3337
3336
9301
3342
3339
2218
3220 3212
9211
3209 9210 9214
1X03
7000
1M83
9109
9112
9111
Layout 8 LED Low-Pow
18490_550_090326.eps
090326
31043136314.3
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 80
10 LED Low-Pow: Microcontroller Block Liteon
1
3
2
A
4
5
2
1
6
4
3
8
7
9
6
5
8
7
13
12
11
10
14
10
9
16
15
11
17
12
18
13
MICROCONTROLLER BLOCK LITEON
B
3134
RES
10n
3137
10K
2105
3111
10n
3139
1K5 1%
100n
4
8
C
5
10K
10K
6
10K
7
10K
5
10K
8
10K
8
7
10K
5
10K
7
10K
RST
GND
CD
NC
4
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
2
4
3102-4
3103-1
1
3
3102-3
3101-3 3
3102-2
5
10K
6
10K
8
10K
4
3101-4
3112
8
10K
10K
1
3114
3
3106-3
3115
1
3105-1
3102-1 1
RES
10K
3104-1 1
3106-2 2
4
3
3106-1
3104-3 3
3105-3
10K
5
1
2
3
1
8
7
6
8
2
4
2
4
7
5
7
5
3126-1
1
8
3127-1
3127-4
1
4
8
5
I124
100R
100R
100R
100R
100R
100R I125
100R
100R
100R
100R
100R
100R
I126
100R
E
CONTROL-1
PWM-CLOCK-BUF
SPI-CLOCK-BUF
SPI-DATA-RETURN
SPI-DATA-IN
SPI-LATCH
SPI-LATCH-2
TEMP-SENSOR
EEPROM-CS
BLANK-BUF
PROG
TEMP-SENSOR
F
CONTROL-2
SCL
SDA
100R
100R
100p
100p
2131
100p
2126
100p
2124 RES
100p
2123
100p
2122 RES
100p
2117
100p
2116
4
UD-MD
I111
I110
I113
I114
I115
3130
3103-4
22R
3131
F112
9106
RES
100n
2112
9119
G
5
4
10K
7
3103-2
2
100R
VLED1
3105-4
7
10K
3104-2 2
3116
2110
100p
100p
3117
7
19
43
5
+3V3
100p
2115
10K
1
100n
5
2111
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
IN
3104-4 4
10K
9121 RES
3
3120
10K
3119
1u0
2130
7110
NCP303LSN10T1
6
3103-3
3
6
10K
10K
+3V3
VLED2
+3V3
15 16
F103
+1V8
100n
2113
100n
2121
100n
H
2119
H
F104
+3V3
27
2114 RES
+3V3
VLED1
4
F102
100n
2120
L
10K RES
10K
RES 9103
9104
RES
10K
3132
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
1M2A
K
10K
RES
9102
+3V3
F109
G
3141
1
2
D
3124-4
3128
3129
3124-1
3124-2
3124-3
3125-1
3142
3125-2
3125-4
3126-2
3126-4
100p
3133
+3V3
26
13
14
18
21
22
23
24
28
29
30
35
36
37
41
44
45
46
47
48
1
2
3
32
33
34
38
39
8
9
10
15
16
2118 RES
3118
31
2109
9101
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
2
owner.
M
1
2
3
4
5
6
7
8
9
10
11
12
1101 E4
1105 B5
1M1A C1
1M2A G1
1M83 A1
1M84 E1
2101 A6
2102 A7
2103 A8
2104 B7
2105 B10
2106 B13
2107 B11
2108 B12
2109 D7
2110 D7
2111 G4
2112 H7
2113 H7
2114 F9
2115 F9
2116 F9
2117 F9
2118 H8
2119 H6
2120 H6
2121 H6
2122 F9
2123 F10
2124 F10
2125 B3
2126 F10
2127 B1
2128 B1
2129 B2
2130 F2
2131 F10
3101-2 D7
3101-3 D9
3101-4 E9
3102-1 D9
3102-2 D9
3102-3 E9
3102-4 D9
3103-1 E9
3103-2 G10
3103-3 G11
3103-4 G10
3104-1 D8
3104-2 E8
3104-3 E8
3104-4 D9
3105-1 E9
3105-2 D8
3105-3 E8
3105-4 D8
3106-1 E8
3106-2 D8
3106-3 E8
3107 C7
3108 C7
3109 D7
3110 D7
3111 B10
3112 D9
3113 D8
3114 E8
3115 E8
3116 E8
3117 E7
3118 E5
3119 F4
3120 F5
3123 C11
3124-1 E11
3124-2 E11
3124-3 E11
3124-4 E11
3125-1 F11
3125-2 F11
3125-4 F11
3126-1 F11
3126-2 F11
3126-4 F11
3127-1 F11
3127-4 F11
3128 E11
3129 E11
3130 G8
3131 G7
3132 H8
3133 H8
3134 A13
3135 A11
3136 A12
3137 B11
3138 B13
3139 B12
3140 C11
3141 C13
3142 F11
7101 A7
7102 E6
7110 F4
7116-1 B11
A
7116-2 A12
9101 E5
9102 F5
9103 F5
9104 F5
9106 H8
9107 A5
9108 A5
9109 A5
9110 B5
9111 A3
9112 B2
9113 B3
9114 B2
9119 H6
9121 G4
C140 B10
F101 A8
F102 F5
F103 H7
F104 F5
F105 D7
F106 B12
F107 C7
F108 D7
F109 G3
F112 G8
F116 A10
F117 B13
F118 C11
F120 A1
F121 A1
F122 A1
F123 A1
F124 B1
F125 B1
F126 B1
F127 B1
F128 B1
F129 B1
F130 B1
F131 B1
F132 B1
F133 E1
F134 F1
F135 E1
F136 F1
F137 F1
F138 F1
F139 F1
I110 G8
I111 G8
I113 G10
I114 G10
I115 G10
I124 E11
I125 E11
I126 F11
B
C
D
E
F
G
H
I
J
K
L
M
13
N
N
1X03
REF EMC HOLE
O
O
SETNAME
5
4
3
2
CHN
1
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
F133
F135
F136
F139
F137
VSSA
P0.0|TXD0|MAT3.1
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
RTXC1
P0.5|MISO0|MAT0.1
RTXC2
P0.6|MOSI0|CAP0.2
P0.7|SSEL0|MAT2.0
RTCK
P0.8|TXD1|MAT2.1
P0.9|RXD1|MAT2.2
VBAT
P0.10|RTS1|CAP1.0|AD0.3
P0.11|CTS1|CAP1.1|AD0.4
P0.12|DSR1|MAT1.0|AD0.5
DBGSEL
P0.13|DTR1|MAT1.1
P0.14|DCD1|SCK1|EINT1
P0.15|RI1|EINT2
RST
P0.16|EINT0|MAT0.2
P0.17|CAP1.2|SCL1
P0.18|CAP1.3|SDA1
P0.19|MAT1.2|MISO1
P0.20|MAT1.3|MOSI1
P0.21|SSEL1|MAT3.0
P0.22|AD0.0
P0.23|AD0.1
P0.24|AD0.2
P0.25|AD0.6
P0.26|AD0.7
P0.27|TRST|CAP2.0
P0.28|TMS|CAP2.1
P0.29|TCK|CAP2.2
P0.30|TDI|MAT3.3
P0.31|TDO
VDD_1V8 VDD_3V3
VDDA
MICROCTRL
42
20
25
1M84
Φ
VSS
X1
X2
17
40
16M9
1101
12
2
7 3101-2
10K
10K
6
10K
6
10K
8
10K
6
10K 3113
RES
10K
100R
15 16
3105-2 2
F108
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3123
10K
F105
VLED2
15 16
RES
F107
VLED1
11
J
47K
8
3140
EEPROM-CS
TEMP-SENSOR
PROG
10K
3107
3108
+3V3
VLED2
3
+3V3
+3V3
E
F
B
10n RES
3138
1K8 1%
RES
+3V3
SDA
CONTROL-1
CONTROL-2
F138
F134
7116-1
LM393PT
F118
SCL
2108
+3V3
1.5A T
7102
LPC2103FBD48
I
F117
2107
VLED1-F
1K5 1%
RES
VLED1
G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+3V3
C140
33p
2125
9112
9114
10u 35V
15 16
D
H
7
6
2106
1105
3109
F
3136
5
F106
VLED1
VLED2
100R
3110
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1%
1%
F116
1M1A
E
7116-2
LM393PT
1K5
+1V8
4
BLANK
EEPROM-CS
TEMP-SENSOR
PROG
3135
4
BP
COM
A
100K RES
+3V3
4u7
INH
2102
3
100n
SPI-LATCH
PWM-CLOCK
5
OUT
10n
9109
9110
IN
2104
CONTROL-1
CONTROL-2
1
+3V3
1u0
SPI-CLOCK
SDA
2101
9107
9108
-T 10K
9113
RES
SCL
SPI-DATA-RETURN
F101
2
+3V3
1u0
2128
B
SCL
SPI-DATA-IN
SDA
CONTROL-1
CONTROL-2
9111
RES
10u 35V
2129
D
F120
F121
F122
F123
F124
F125
F126
F127
F128
F129
F130
F131
F132
2127
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+3V3
+3V3
7101
LD2985BM18R
1K5
IN
1M83
2103
A
20
19
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
8204 000 8857
2K9
2
1
2008-06-10
2
2008-08-08
3
??
P
3
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATE
16
130
3
SUPERS.
2008-06-02
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_630_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 81
10 LED Low-Pow: Microcontroller Block Liteon
1
2
3
1
A
5
4
2
3
7
6
4
8
9
5
10
6
11
7
12
14
13
9
8
16
15
10
11
18
17
12
13
MICROCONTROLLER BLOCK LITEON
INPUT BUFFER
A
+3V3
B
+3V3
14
100p
2217
7
B
Φ
D
2
Q
9210 RES
SPI-DATA-RETURN
(64K)
7201-4
74HCT125PW
+3V3
14
C
HOLD
12
SPI-CLOCK
+3V3
10K
W M95010-WDW6
3209
4
+3V3
F206
3220
11
13
RES
1K0
27R
EN
SPI-CLOCK-BUF
100p
3204
7
2218
S
9211
C
9212 RES
2
BLANK
F207
RES
1K0
3223
6
4
100R
EN
7
33p
2203
3211
+3V3
+3V3
14
E
7201-2
74HCT125PW
5
BLANK-BUF
2219
SPI-CLOCK-BUF
100p
10K RES
3205
PWM-CLOCK-BUF
9209
GND
3
100R
EN
7
3
1
33p
2201
1
F203
EEPROM-CS-LOCAL
3219
3
1
8
33p
10K
3203
6
33p
2209
2
C
F205
RES
1K0
VCC
5
D
+3V3
SPI-DATA-IN
7214
1
7210
PDTC144EU
100n
SPI-CS
2202
SPI-CS
F202
+3V3
EEPROM-CS
PWM-CLOCK
3207
7212
PDTC144EU
3
7201-1
74HCT125PW
2
10K
3210
2214
7209
PDTC144EU
B
10K
3213
C
A
9208 RES
+3V3
+3V3
9213
D
9214 RES
D
SPI-DATA-OUT-FIL
+3V3
7201-3
74HCT125PW
14
F
3121
G
9
8
100R
10
F208
3212
DATA-RETURN-SWITCH
100R
7
EN
100p
2220 RES
SPI-DATA-RETURN
E
E
H
F
B
C
D
E
F
G
H
I
2216
2215
1u0
100n
28
Φ
3216
100R
SPI-DATA-OUT-FIL
L
3214
26
+3V3
10K
XLAT
SCLK
SIN
SOUT
XHALF
1
XERR
VIA
+3V3
I
+3V3
F214
PWM-G2
F215
PWM-B2
F209
EEPROM-CS-LOCAL
DATA-RETURN-SWITCH
H
EEPROM-CS-LOCAL
DATA-RETURN-SWITCH
L
23
6216
33p
2211
GND GND_HS
K
PWM-R2
3K3
4
5
24
IREF
PWM-B1
F213
3221
3
F212
3K3
1K2
SPI-CLOCK-BUF
SPI-DATA-IN
SPI-DATA-OUT
27
BLANK
MODE
3222
F204
29
3218 RES
3215
1K2
SPI-LATCH
H
6
100R
PWM-G1
470R
33p
3217
PROG
PWM-R1
F211
SML-310
2
2210
K
0
1
2
3
4
5
6
7
OUT 8
9
10
11
12
13
14
15
GSCLK
30
31
32
33
25
J
G
F210
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
3224
VCC
LED DRIVER
PWM CONTROL
G
PWM-CLOCK-BUF
BLANK-BUF
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
A
+3V3
7215
TLC5946PWP
M
2201 B8
2202 C8
2203 D8
2209 B2
2210 G6
2211 I6
2214 A6
2215 F7
2216 F7
2217 B12
2218 C12
2219 D12
2220 E9
3121 D9
3203 B5
3204 B7
3205 C5
3207 B9
3209 C9
3210 B3
3211 C9
3212 D11
3213 B3
3214 H6
3215 H6
3216 H6
3217 H6
3218 H6
3219 B11
3220 C11
3221 H11
3222 I8
3223 C11
3224 H11
6216 I8
7201-1 A10
7201-2 C10
7201-3 D10
7201-4 B10
7209 B2
7210 C2
7212 B3
7214 B6
7215 G7
9208 A10
9209 B9
9210 B10
9211 C9
9212 C10
9213 D9
9214 D10
F202 B3
F203 C5
F204 H6
F205 B10
F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
F211 G9
F212 G9
F213 H9
F214 H9
F215 H9
F
I
J
20
19
I
M
+3V3
1
N
2
3
4
5
6
7
8
9
10
11
12
13
N
O
O
CHN
SETNAME
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
8204 000 8857
2K9
2
1
2008-06-10
2
2008-08-08
3
??
P
3
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
SUPERS.
DATE
16
2008-06-02
130
C
17
2
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_631_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 82
10 LED Low-Pow: LED Liteon
1
1
A
6
5
4
3
2
2
3
7
9
8
4
5
11
10
7
6
12
13
9
8
15
14
10
16
19
13
12
11
18
17
LED LITEON
B
A
A
VLED2
9308
9307
VLED1-F
C
B
RED
6
BLUE
GREEN
2
5
RED
1
6
BLUE
4
GREEN
2
5
RED
1
6
BLUE
GND_HS
4
GREEN
2
4
9305-4
5
5
RED
1
1
9305-1
8
6
BLUE
3
4
GREEN
2
8
9318-1
1
5
RED
1
5
9318-4
4
6
BLUE
GND_HS
GREEN
2
4 9303-4
5
5
RED
2
4 9315-4
5
1
1 9303-1
8
6
BLUE
1
1 9315-1
8
2 9315-2
3
5
9313-4
4
8
4
7
9313-1
9313-2
B
6
GND_HS
2
9312-1
1
7005
LTW-E500T-PH1
3 9303-3
3
1
9312-4
9312-3
8
6
5
9318-3
3
7004
LTW-E500T-PH1
6
3
4
9310-1
1
8
9310-4
5
9310-2
7
7
4
9309-4
4
9305-2
2
9309-1
5
9309-2
7003
LTW-E500T-PH1
2
3
GND_HS
7
7
GND_HS
7002
LTW-E500T-PH1
3
G
R
7
C
GND_HS
G
7
5
4
3
7
GREEN
7
C
4
1
7001
LTW-E500T-PH1
7000
LTW-E500T-PH1
7
R
B
F344
F340
F341
B
F
5
9319-3
3
6
8
9319-1
9319-4
9320-2 7
1
9320-4 5
2
1
9304-1
8
4
9304-4
5
BLUE6
390R
3351
1K5
3313
560R
390R
1K5
3314
560R
1K5
3315
560R
1K5
3316
560R
1K5
3317
560R
1K5
3318
560R
1K5
3319
560R
3365
VLED1-F
VLED1-F
Place jumper 9325, 9326, 9327
VLED1-F
if VLED < 17V
VLED1-F
if VLED < 17V
F303
3305
1K5
3320
560R
1K5
3321
560R
1K5
3322
560R
1K5
3323
560R
3306
PWM-R1
F328
VLED1-F
F329
3368
G
F349
F348
GREEN-2
H
F330
1K0
9327
1K0
3367
7316
BC847BW
3308
9316
3333
10K
3307
7306
BC847BW
10K
3327
F304
F305
3366
F347
PWM-R2
VLED1-F
H
F
1K5
1K0
10K
3326
1K0
3363
3364
RED-2
7315
BC847BW
9314
3328
K
owner.
F327
Place jumper 9314, 9316, 9317
9326
10K
3325
F302
7305
BC847BW
3362
6
1K5
E
3361
8
1K5
3391
G
10K
PWM-B2
PWM-B1
10K
560R
1K0
3304
3374
F326
9325
1K0
1K5
3390
3302
3359
3360
10K
560R
3301
1K5
3389
3373
F308
10K
560R
3334
3303
1K5
3388
BLUE-2
7317
BC847BW
9317
560R
3372
F325
F307
7307
BC847BW
10K
3371
1K5
3387
10K
560R
D
3357
9311-3
1K5
3386
3370
L
4
9320-1 8
1
4
3
9306-3
RED6
BLUE6
1K5
3385
3369
560R
10K
10K
3309
GREEN-2
3330
All rights reserved. Reproduction in whole or in parts
RED6
560R
3358
1K5
3384
560R
is prohibited without the written consent of the copyright
7
560R
1K5
3312
9311-1
560R
J
9304-2
1K5
3311
3
3352
F
2
390R
3345
390R
3348
1K5
3356
3355
I
390R
GREEN6
3354
1
1K5
3353
560R
GREEN6
3310
5
560R
3349
390R
3342
3335
9311-4
1K5
3350
6
390R
3339
4
1K5
3347
1
560R
3343
3346
H
RED-1
BLUE-1
9306-4
390R
3337
9306-1
1K5
3344
5
3341
560R
3340
8
3338
560R
E
G
3336
3331
G
R
GREEN-1
3332
D
F346
F345
F343
F342
4
E
9302
9301
D
2
7
VLED2
8
B
VLED1-F
RED-2
M
BLUE-2
PWM-G2
PWM-G1
I
I
N
1
3
2
4
5
6
7
8
9
10
11
12
20
3301 F9
3302 F9
3303 F9
3304 G9
3305 G9
3306 H9
3307 H9
3308 H9
3309 I9
3310 D12
3311 D12
3312 E12
3313 E12
3314 E12
3315 E12
3316 E12
3317 F12
3318 F12
3319 F12
3320 F12
3321 G12
3322 G12
3323 G12
3325 G4
3326 H4
3327 H4
3328 G4
3330 I4
3331 F4
3332 F4
3333 H4
3334 F4
3335 D12
3336 D2
3337 D2
3338 D1
3339 D2
3340 D1
3341 D1
3342 E2
3343 D1
3344 D1
3345 D12
3346 E1
3347 D1
3348 E12
3349 E1
3350 E1
3351 E12
3352 E1
3353 E1
3354 D13
3355 E1
3356 E1
3357 D13
3358 E13
3359 E13
3360 E13
3361 E13
3362 E13
3363 F13
3364 F13
3365 F13
3366 F13
3367 G13
3368 G13
3369 F1
3370 F1
3371 F1
3372 F1
3373 F1
3374 G1
3384 E1
3385 F1
3386 F1
3387 F1
3388 F1
3389 F1
3390 G1
3391 G1
7000 C2
7001 C3
7002 C4
7003 C6
7004 C8
7005 C11
7305 G4
7306 H5
7307 F4
7315 G9
7316 H10
7317 F9
9301 C1
9302 C1
9303-1 C10
9303-3 C10
9303-4 C10
9304-1 E10
9304-2 E10
9304-4 E10
9305-1 C6
9305-2 C6
9305-4 C6
9306-1 D5
9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
9309-4 B6
9310-1 B8
9310-2 B8
9310-4 B8
9311-1 H13
9311-3 H13
9311-4 H12
9312-1 B10
9312-3 B10
9312-4 B10
9313-1 B12
9313-2 B12
9313-4 B12
9314 G5
9315-1 C12
9315-2 C12
9315-4 C12
9316 H5
9317 F5
9318-1 C8
9318-3 C8
9318-4 C8
9319-1 D9
9319-3 D9
9319-4 D9
9320-1 D7
9320-2 D7
9320-4 D7
9325 F10
9326 G10
9327 H10
F302 G5
F303 G4
F304 H5
F305 H5
F307 F5
F308 F4
F325 F10
F326 F9
F327 G10
F328 G9
F329 H10
F330 H10
F340 D1
F341 D1
F342 D1
F343 D2
F344 D12
F345 D12
F346 D13
F347 G12
F348 G13
F349 G13
A
B
C
D
E
F
G
H
I
J
K
L
M
N
13
O
O
CHN
SETNAME
CLASS_NO
DRIVER 6LED LITEON
P
2008-08-08
8204 000 8857
2K9
2
1
2008-06-10
2
2008-08-08
3
??
P
3
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
SUPERS.
DATE
16
2008-06-02
130
C
17
3
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_632_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 83
10 LED Low-Pow: LED Drive Liteon
1
2
3
4
7
6
5
9
8
11
10
13
12
14
15
17
16
18
20
19
A
A
2
1
B
3
4
5
6
7
8
9
10
LED DRIVE
C
A
A
4
GREEN
RED-1
5
RED
BLUE-1
6
BLUE
3
1
4
GREEN
5
RED
6
BLUE
3
1
4
GREEN
5
RED
6
BLUE
GND_HS
3
1
4
GREEN
5
RED
6
BLUE
3
1
B
GND_HS
GND_HS
7
7
GND_HS
7009
LTW-E500T-PH1
7
B
GREEN-1
7008
LTW-E500T-PH1
7007
LTW-E500T-PH1
2
7
7006
LTW-E500T-PH1
D
E
2
2
2
C
F
C
1M3A E2
1M85 D2
3536 E9
3537 E9
3538 E7
3539 E9
3540 E7
3541 E8
3542 E9
3543 E7
3544 E8
3546 E7
3547 E8
3549 F7
3550 E8
3552 F7
3553 F8
3555 F7
3556 F8
3569 F7
3570 F7
3571 G7
3572 G7
3573 G7
3574 G7
3584 F8
3585 F8
3586 F8
3587 G8
3588 G8
3589 G8
3590 G8
3591 G8
7006 A2
7007 A4
7008 A5
7009 A6
B
C
D
E
F
1M85
1
2
3
4
5
6
7
8
9
10
11
12
13
14
G
D
H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F
D
RED-2
BLUE-2
VLED1
H
VLED2
15 16
3536
3538
3541
560R
1K5
3544
390R
3537
560R
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
3543
1K5
3547
390R
3539
560R
3546
1K5
3550
390R
3542
560R
3549
1K5
3553
390R
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
+3V3
560R
E
I
1K5
3556
3552
J
VLED1
560R
VLED2
1K5
3584
3555
560R
15 16
1K5
3586
3570
K
560R
G
3571
1K5
3587
560R
3572
1K5
3588
560R
1K5
3589
3573
560R
L
F
1K5
3585
3569
560R
owner.
All rights reserved. Reproduction in whole or in parts
G
GREEN-2
BLANK-BUF
EEPROM-CS
TEMP-SENSOR
PROG
1M3A
I
is prohibited without the written consent of the copyright
+3V3
3540
E
J
SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN
SPI-LATCH
PWM-CLOCK-BUF
K
G
1K5
3590
3574
560R
L
1K5
3591
1K5
M
1
3
2
N
5
4
6
7
8
9
M
10
N
1X04
REF EMC HOLE
O
O
CHN
SETNAME
1
CLASS_NO
4 LED + CONNECTOR
P
2008-08-14
2
2008-10-31
3
LITEON 2K9
NAME Peter Van Hove
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8204 000 8897
15
16
2
2008-10-24
3
2008-10-31
P
1
SUPERS.
DATE
2008-08-14
2008-07-29
130
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_633_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 84
F108
F104
F109
I124
F137
F126
F212
1M1A
F122
F128
F129
F131
F326
F134
F328
F202
F133
F329
F325
F327
F118
F203
F136
F308
F330
I125
F103
F112
F210
F305
F102
F206
F340
F208
F205
F307
F304
F204
F302
F121
F138
F207
F211
F303
F117
7009
3536
3537
3539
3542
F123
F127
F139
F209
F213
3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
F120
F132
F105
F214
F124
F130
1M2A
F101
F344
I126
F345
F107
F215
F349
F106
F347
F116
F348
1X04
F343
F125
F342
F341
F135
F346
1M3A
7008
7007
7006
9311
9319
9304
9303
9312
3335
3345
3348
3351
3317
3316
3315
3313
3312
3311
3310
7005
2127
3303
3302
3301
3309
3308
3307
9327
1M85
3314
3320
3319
3318
3323
3322
3321
9315
7316
7317
3306
3305
3304
9325
9326
3140 3135
3123
7116
9318
3134
3141
7315
2105
3137
3111
7004
7209
3204
2214
9310
2111
7212 7210
3213
7214
3203 3205
C140
2107
9320
3105
3210
9106
3113
3125
3138 3136
2106 3139
2108
2209
7003
2124
2121
3126
2118
7102
3131
2112
3116
9119
3104
2113
7110
2122
3130
2120
I111
2115
3112
2131
3127
I115
2123
3101
3117
3114
9102
3106
2119
I114
3124
3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
3107
3110
2110 2109
3109
3108
1101
9313
1M84
3120
3119
9121
2117
2116
3115
2126
3103
3142
7002
I110
I113
9104
9103
3118
9101
2114
2102
2103
7101
9317
3332
7307 3334
3331
9309
9305
3330
3333
3327
9306
3326
3328
3325
9316
7306
9308
9307
2104
7215
2210
3217
9314
2216
3214 2215
7305
3221
3224
3222
3132
3133
3102
2125
3128
3129
2101
3215
2219
2129 2128
3218
2211
3216
9208
3219
3207
2217 9209
3223
7001
2220
2201
7201
9213
2203
9212
3211
3121
6216
9113
1105
9110
2130
9114
9302
9107
2202
3385 3389
3384 3390
3356 3391
3350 3386
3347 3387
3344 3388
3341 3353
9108
3338 3374
3340 3369
3343 3373
3346 3372
3349 3371
3352 3370
3355
3337
3336
9301
3342
3339
2218
3220 3212
9211
3209 9210 9214
1X03
7000
1M83
9109
9112
9111
Layout 10 LED Low-Pow
18310_553_090309
090309
3104 313 6315.2
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 85
SSB: DC/DC
1
2
2U06 B10
2U07 E11
2U0B H9
2U0D H6
A
3
2U0V E12
2U0W A5
2U0Y A12
2U0Z B10
2U0R G10
2U0S F1
2U0T E11
2U0U E12
2U0F A5
2U0H C9
2U0J E9
2U0K F9
2U10 C14
2U11 C14
2U12 C9
2U14 A12
1
2U15 B13
2U16 E13
2U17 E13
2U19 A13
6
5
4
2U55 D4
2U56 D4
2U57 D2
2U58 D3
2U1B E14
2U39 B6
2U50 D7
2U54 C2
2
2U63 F6
2U64 G9
2U65 G8
3U06 B6
2U59 E2
2U60 E6
2U61 E4
2U62 F2
3
3U0J B9
3U0K E9
3U13 C7
3U15 C5
3U09 H9
3U0A H10
3U0F H5
3U0G H6
4
3U16 C5
3U17 D3
3U18 D5
3U19 D5
3U20 D5
3U21 E2
3U22 E3
3U23 F2
3U1D F6
3U1J G14
3U1M B9
3U1V F1
5
3U24 F7
3U25 F8
3U30 E6
3U31 G8
6
11
10
9
8
7
3U74 E9
3U75 G10
3U76 E11
5U00 E9
5U01 B9
5U02 A13
5U03 C13
5U32 A13
7
5U33 B13
6U02 E2
6U03 D5
7U02 B6
13
12
7U03 D3
7U05 C8
7U06 D8
7U08 A6
FU06 F5
FU07 B9
FU08 G14
FU0A E8
7U09 E1
CU77 G2
FU04 E2
FU05 A8
8
FU0B E14
FU0C B14
FU0E C14
IU06 G9
IU07 E9
IU08 B9
IU0K D7
IU0N C7
IU0P B6
IU0S G5
IU0T G9
IU0U E1
10
9
15
14
IU1D G10
IU1E F9
IU1P B6
IU1R F1
IU11 B6
IU12 D7
IU19 H9
IU1B C9
17
16
IU1T A13
IU30 E6
IU31 G9
IU55 C4
11
IU56 D3
IU57 D3
IU58 E3
IU59 E3
18
20
19
IU60 E3
IU61 D5
IU62 F6
IU63 D5
12
A
14
13
15
B
B
DC / DC
C A
A C
+12VF1
FU05
IU1T
5U02 RES
IU1P
5 6 7 8
SI4800BDY
1 2 3
4
12V/3V3 CONVERSION
1u0
2U19
D
30R
2U39
FU07
B
30R
5U33
VSW
3U06
3R3
D
10u
5U32 RES
22u
2U14
7U08
RES 22u
2U0Y
22u
2U0F
RES 22u
2U0W
+12VF
5U01
FU0C
1n0
IU11
2U15
22u
22u
2U0Z
2U06
22R
22R
5 6 7 8
SI4800BDY
1 2 3
E
IU08
1n0
2U0H
4
220u 25V
IU0P
3U1M
3U0J
7U02
E
FU0E
5U03
FU04
IU0U
2
+1V2-PNX85XX
1
TEST
2
NC
PGND
GND-SIG
2U61
2U63
RES 100u 6.3V
2U17
RES 330u 6.3V
2U16
RES 330u 6.3V
2U0V
22u
RES 22u
2U0T
2U07
10R
RES
3U76
2U1B
E
I
3U24
IU1E
+3V3
3n3
GND-SIG
IU62
33K
FU06
F J
3U1D
10K
3U25
GND-SIG
IU0S
IU06
2U64
K
1n0
2U65
+1V2-STANDBY
1u0
3n3
CU77
2U0R
K
GND-SIG
G
3U1J
FU08
IU1D
IU31
G
SENSE+1V2-PNX85XX
GND-SIG
GND-SIG
1% 470R
3U75
3U0A
22K
3U09
100p
RES 2U0B
2U0D
47K
3U0G
GND-SIG
RES 100p
H
1% 1K0
3U0F
IU0T
L
1% 1K0
4K7
3U31
120R 1%
L
M
+1V2-PNX85XX
IU07
GND-SIG
3K3
RES
3U1V
100n
RES
22R
IU30
3U30
4K7
2
6
9
13
3U74
3U0K
+1V2-PNX85XX
+3V3
22R
4
5
11
10
22
H
FU0B
10u
2U0U
FU0A
1% 3K3
J F
2U11
10R
3U18
10R
RES 6U03
3U19
3R3
BAT54 COL
3U20
100n
5U00
27
16
RES 22u
V5FILT
12V/1V2 CONVERSION
22u
VO2
VFB2
VREG5
1u0
RES
2U62
3
10R
1
2U0S
owner.
All rights reserved. Reproduction in whole or in parts
IU1R
8
20
GND-SIG
RES 3U23
7U09
BC847BW
TRIP2
15
17
5 6 78
4
1 2 3
SI4800BDY
1n0
21
VO1
VFB1
EN2
IU0K
1n0
20K
GND-SIG
19
LL1
LL2
VBST2
IU63
2U0J
IU60
TRIP1
D
2U0K
1n0
RES
2U59
12
3U22
I
24
14
6U02 RES
ENABLE-3V3-5V
E
IU59
28
26
1n0
G
1n0
BAT54 COL
F
2U50
2U60
20K
DRVH2
DRVL2
EN1
C
7U06
GND
3
IU58
3U21
GND-SIG
is prohibited without the written consent of the copyright
VBST1
7
H
VIN
DRVH1
DRVL1
1
IU12
4u7
Φ
100n
100n
2U58
RES
2U57
7U03
TPS53124PW
23
IU57
D
RES 2U56
100n
25
18
GND-SIG
IU61
2U55
3R3
3U17
G
3R3
10R
IU56
+3V3F
1 2 3
3U13
2u2
2U54
3U16
5 6 7 8
SI4800BDY
RES 100u 4V
4
2U10
IU0N
10R
2U12
3U15
IU55
1n0
C
10u
7U05
RES 100u 4V
IU1B
F
B
+3V3
10u
IU19
GND-SIG
GND-SIG
H
GND-SIG
M
N
N
2
1
O
3
4
5
6
7
8
9
10
11
12
13
14
15
O
1X08
REF EMC HOLE
CHN
SETNAME
2
CLASS_NO
2008-11-21
DC/DC
P
8204 000 8932
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
3
SUPERS.
DATE
16
2007-11-20
130
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_500_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 86
SSB: DC/DC
2
1
2
10
9
6
7
12
11
8
13
9
RES
IU34
2U44
7U10
RES
RES
IU20
IU53
9U07
RES
100p
2U21 RES
RES
3U41
LED2
1K0
RES
3U59
LED2
10K
3
+3V3
3U4B
LED1
3U35
LED1
10K
A
100p
2U46
IU21
22n
IU35
4
REF
100p
+1V2-STANDBY
FU1F
7U0N
TS431AILT
10K
BC847BW
7U11
BC847BW
2U25
1
K
10K
3U95
100R
10K
2U45
IU3C
3U4A
IU52
3U94
3U93
+5V
100n
IU50
9U08
100p
7U0M
BC847BW
2
1u0
9U06
RES
+5V +3V3-STANDBY
3
1
2U26
100R
+3V3-STANDBY
A
2U24
30R
5U12
5U13
30R
5U14
5U15 30R
30R
IU51
3U46
3U92
+3V3-STANDBY
68K
100p
RC
+3V3-STANDBY
+3V3
4K7
100R
RESERVED
3U3W
2U43
100K
IU49
NC
3U91
LIGHT-SENSOR
+3V3
B
1K0
3U3V
NC
100p
LIGHT-SENSOR
3U37
1u0
100R
IU48
10K
2U42
5U11
30R
FU33
FU34
FU35 30R
FU36
5U16
FU38
30R
5
3U97
3U90
5U10
30R
FU30
2U2C
4
5U07
FU32
FU31
C B
10K
2
5
+12VD
3U98
LAMP-ON-OUT
100R
FU17
3U55
FU18
3U57
5
OUT
INH
+1V2-STANDBY
IU3T
4
BP
COM
2U49
1u0
10n
2U31
3U58
IN
100n
1n0
3
2U47
10n
2U30
1
+3V3-STANDBY
BACKLIGHT-PWM-ANA-DISP
2
10n
100R
2U23
RES
1K0
3U65
100p
2U53
100p
100R
BACKLIGHT-BOOST
FU15
RES
RES
3U56
1K0
3U64
1-1735446-2
100R
C
7U50
LD3985M122
BACKLIGHT-OUT
2U22
FU24
2U52
E
1u0
FU16
100p
C
KEYBOARD
FU1H
10R
FU19
FU14
2U51
D
2U37
FU13
1
2
3
4
5
6
7
8
9
10
11
12
1u0
1M99
2U48
POWER-OK
D
FU25 100R
RES
3U66
FU26
D
SCL-SET
100R
F
RES
SDA-SET
3U67
CU71
CU70
FU1G
6U0B
*
*
I
5U20
3U45
RES 33K
RES 33K
2U2B
RES 220n
3U44
220n
6U0C
2U29
220u
IU3B
3U42
+12V
10K
2K2
100K
1u0
3U43
2U2A
68R
3U40
3
DETECT-12V
7U0P
2N7002
68R
3U47
IU38
1K0
RES
3U61
3U83
6K8
3U82
FU40
7U0Q
BC847BW
22K
30R
5U21
IU54
2
3K3
3U86
10K
3U85
33p
IU39
220p
22K
2U28
ENABLE-3V3
2U27
3U62
10K
5
2
F
* IN CASE OF ONLY-ANALOG TUNER
6
7U41-1
BC847BS(COL)
1
30R
IU45
IU47
7U41-2
BC847BS(COL)
4
IU36
3U3Z
3U89
2K8 supplies 10K
IU37
1
3
10K
2U40
IU44
RES
3U63
10n
10n
2U36
*
10K
3U81
1
3U88
100p
2U35
100p
2U34 RES
+1V2-STANDBY
30R
5U17
22K
IU43
6
7U40-1
BC847BPN(COL)
1u0 RES
FU12
* 5U06
ENABLE-3V3-5V
2
+AUDIO-POWER
1-1735446-1
FU39
3U3Y
IU40
3U60
IU42
10K RES
3.0A T 32V
FU10
BZX384-C8V2
+12V
FU11
F
6U40
3.0A T 32V
1U01
E
3
1K0
H
VSW
5
+3V3-STANDBY
FU1A
FU1B
FU20
FU23
FU1C
FU22
FU21
FU1D
1
2
3
4
5
6
7
8
9
10
11
4
IU41
+12VF
3U84
G E
1U03
10n
1M95
5U08
2U32
7U40-2
BC847BPN(COL)
10K
3U80
BAS316
BZX384-C27
+33VTUN
STANDBY
GND-AUDIO
2U33 RES
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
100p
TO
LED PANEL
1
2
3
4
5
6
7
8
B
3
8
7
2U41
DC / DC
1M20
6
5
10K
A
A
4
3
3U96
1
2K9 supplies
30R
1
2
4
3
5
6
7
CHN
8
1M20 A1
1M95 E1
1M99 C1
1U01 E2
1U03 E2
2U21 B1
2U22 D2
2U23 D2
2U24 A7
2U25 B8
2U26 B9
2U27 F7
2U28 F8
2U29 E8
2U2A E8
2U2B E8
2U2C B1
2U30 D2
2U31 D3
2U32 E1
2U33 F1
2U34 F1
2U35 F1
2U36 F1
2U37 C1
2U40 F3
2U41 A2
2U42 A2
2U43 A2
2U44 A2
2U45 B2
2U46 B2
2U47 D8
2U48 D8
2U49 D7
2U51 D1
2U52 D1
2U53 C1
3U35 B6
3U37 A6
3U3V B8
3U3W A8
3U3Y E6
3U3Z F6
3U40 E8
3U41 B5
3U42 E9
3U43 E8
3U44 E9
3U45 E9
3U46 A8
3U47 E8
3U4A B8
3U4B B4
3U55 C3
3U56 C3
3U57 C3
3U58 C3
3U59 B6
3U60 E5
3U61 E5
3U62 F5
3U63 F5
3U64 C2
3U65 C2
3U66 D1
3U67 D2
3U80 E3
3U81 E3
3U82 E4
3U83 E4
3U84 F2
3U85 F4
3U86 F4
3U88 F3
3U89 F3
3U90 A3
3U91 A3
3U92 A3
3U93 B2
3U94 B3
3U95 B3
3U96 A4
3U97 A4
3U98 C3
5U06 F2
5U07 A1
5U08 E7
5U10 A1
5U11 A1
5U12 A1
5U13 A1
5U14 A1
5U15 B1
5U16 B1
5U17 F2
5U20 F2
5U21 F2
6U0B E8
6U0C E8
6U40 E3
7U0M A9
7U0N B7
7U0P E7
7U0Q E9
7U10 B4
7U11 B3
7U40-1 E3
7U40-2 E4
7U41-1 F4
7U41-2 F5
7U50 C7
9U06 A2
9U07 B3
9U08 B5
CU70 D1
CU71 D1
FU10 F1
FU11 F1
FU12 F1
FU13 C1
FU14 C1
FU15 C2
FU16 C1
FU17 C2
FU18 C2
FU19 C1
FU1A E1
FU1B E1
FU1C E1
FU1D F1
FU1F B9
FU1G E9
FU1H C4
FU20 E1
FU21 E1
FU22 E1
FU23 E1
FU24 C1
FU25 D1
FU26 D1
FU30 A1
FU31 A1
FU32 A1
FU33 A1
FU34 A1
FU35 A1
FU36 B1
FU38 B1
FU39 E5
FU40 F4
IU20 B4
IU21 B4
IU34 A8
IU35 B8
IU36 F7
IU37 F8
IU38 E7
IU39 F9
IU3B E8
IU3C B8
IU3T C8
IU40 E3
IU41 E3
IU42 E4
IU43 E3
IU44 F3
IU45 F4
IU47 F3
IU48 A4
IU49 A4
IU50 A5
IU51 A3
IU52 B3
IU53 B4
IU54 F5
A
B
C
D
E
F
G
H
I
9
SETNAME
2
CLASS_NO
2008-11-21
DC/DC
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8932
TV543 R2 LDIPNX
8
3
SUPERS.
DATE
9
2007-11-20
130
C
10
2
A3
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_501_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 87
SSB: DC/DC
A
2U00 A12
2U01 A4
2U02 C4
2U03 D2
3
2
1
2U04 D3
2U05 D2
2U08 E6
2U09 E4
2U13 E3
2U18 E6
2U20 F8
2U38 F8
2U66 B6
2U67 C7
2U80 C4
2U81 C2
1
B
5
4
2U83 G7
2U8A A5
2U8C B10
2U8D B10
2
2U8E A10
2U8F B12
2U8G D10
2U8H D10
2U8T H6
2U8U C8
2U8V C8
2U8Y F9
2U8K D10
2U8M D10
2U8Q E9
2U8R E9
3
8
7
6
2U90 A12
3U00 C5
3U01 C5
3U02 C6
4
3U03 C5
3U04 C3
3U05 C5
3U07 D2
9
3U08 D3
3U10 E2
3U11 E7
3U12 E8
5
3U14 B6
3U26 G9
3U27 G10
3U28 C6
3U2C H6
3U2D H6
3U2F F10
3U2G B8
6
11
10
3U2H D9
3U32 E6
3U33 F8
3U3A B12
3U3F E11
3U3G F11
3U3J B9
3U3N D9
7
13
12
5U19 C11
5U30 A11
5U31 A11
6U00 C5
5U04 D9
5U05 B9
5U09 A11
5U18 B11
8
6U01 D2
6U09 B11
7U01 C3
7U0D-1 B7
14
7U0D-2 C7
7U0H-1 A6
7U0H-2 B6
CU25 G2
9
FU87 D8
FU8B A14
FU8C B8
FU8D B14
FU00 E2
FU0D F13
FU80 B14
FU85 D14
10
16
15
FU90 E5
IU00 C4
IU01 C3
IU02 C5
11
IU03 C3
IU04 D5
IU05 D3
IU09 E8
IU16 C7
IU25 D6
IU28 C7
IU29 B6
IU10 D3
IU13 D3
IU14 B6
IU15 E6
12
IU2A B6
IU2C E5
IU2D D5
IU2T G7
13
20
A
IU33 F8
IU82 C9
IU85 E9
IU2V C9
IU2Y F9
IU2Z E9
IU32 D6
14
DC / DC
C
19
18
17
15
B
FU8B
+12VF2
A
C
A
5U09 RES
+12V
7 8
SI4936BDY
2
FU8C
7U0H-2
1
220u 25V
RES
2U8F
220u 25V
1%
3U3A
2K7
22u
2U8C
22u
2U8D
SI4936BDY
2
E
30R RES
1n0
3R3
3U28
2u2
2U81
5U18 RES
2U67
IU2V
GND-SIG1
2U8U
10R
10R
3U02
3U03
RES 6U00
3R3
100n
3U05
23
NC
10R RES
3U3F
2U8M
RES 22u
2U8H
2U8K
22u
2U8G
22R
IU85
4K7
2
6
9
13
3U3N
IU32
3U32
IU2C
22R
3U2H
+5V5-TUN
22u
11
10
22
IU2D
1n0
+1V2-PNX5100
RES 22u
1
TEST
2
1u0
2U13
10R
3U10
VO2
VFB2
VREG5
V5FILT
PGND
RES
I
TRIP2
D
+1V2-PNX5100
10u
4
5
2U8Q
8
20
GND-SIG1
E
19
21
FU00
FU85
H
IU2Z
2U18
3U11
+5V5-TUN
3n3
GND-SIG1
IU15
22K
FU90
E
1n0
IU13
18K
VO1
VFB1
EN2
G
5U04
FU87
27
16
2U8R
1n0
3U08
GND-SIG1
VBST2
12V/1V2 CONVERSION
IU25
15
17
10K
12
IU04
1n0
14
LL1
LL2
F
3
2U08
IU10
6U01 RES
TRIP1
7
BAT54 COL
EN1
25
18
20K
ENABLE-3V3-5V
24
DRVH2
DRVL2
28
26
C
SI4936BDY
4
4u7
3
IU05
3U07
GND-SIG1
VIN
DRVH1
DRVL1
VBST1
GND
1
2U09
Φ
100n
100n
2U04
RES 2U03
G
7U01
TPS53124PW
RES 2U80
100n
IU03
7U0D-2 5 6
BAT54 COL
3R3
3U04
GND-SIG1
1n0
IU02
2U02
1n0
IU16
IU01
3U12
C
RES
2U05
B
FU80
30R
5U19
7 8
2U8V
IU28
10R
6U09
IU82
10R
3U01
SS36
10u
22R
22R
3
7U0D-1
IU29
3U00
IU00
5U05
+5V
5 6
SI4936BDY
3U3J
1n0
E
H
1u0
+5V5-TUN
IU14
D
D
FU8D
2U66
4
F
RES
2U00
30R
3U2G
3R3
3U14
B
30R
5U31
12V/5V CONVERSION
1
D
2U90
7U0H-1
IU2A
22u
2U8E
22u
2U8A
220u 25V
RES
2U01
10u
5U30 RES
I
GND-SIG1
IU09
2U20
2U8Y
1n0
2U38
IU33
SENSE+1V2-PNX5100
3U2F
1% 470R
3U27
6K8
1% 1K0
4K7
3U26
K
IU2T
GND-SIG1
G
GND-SIG1
H
1
N
2
3
4
5
GND-SIG1
GND-SIG1
G
GND-SIG1
L
2U8T
RES 100p
100K
3U2D
3U2C
1% 470R
GND-SIG1
L
J
F
120R 1%
100p
RES 2U83
CU25
K
M
FU0D
3U3G
IU2Y
F
3U33
J
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
3n3
1u0
GND-SIG1
GND-SIG1
H
6
7
9
8
10
11
12
13
14
M
15
N
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
DC/DC
P
8204 000 8932
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
3
SUPERS.
DATE
16
2007-11-20
130
C
17
3
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_502_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 88
SSB: Front End
1
2
3
1
A
6
5
4
2
3
8
7
4
5
FRONT-END
9
6
11
10
7
1T01
UV1316E
16
17
18
19
8
12
13
9
15
14
10
17
16
11
12
18
13
19
20
14
14
MT
15
A
13
MT
12
A
1
2
3
4
5
6
7
8
9
10
11
B
AGC
TU
AS
SCL
SDA
NC
+5V
ADC
+33V_TUN
IF2
IF1
TUNER
RF-IN
TUN-P1
TUN-P2
TUN-P3
TUN-P4
TUN-P5
100R
+VTUN
47R
B
220n
IT13
+5V-TUN-PIN
18p
TUN-P7
9T40
2T22
TUN-P10
IT16
IT0D
RES
10n
14
MT
15
MT
D
9T18
ANTENNA-SUPPLY
IT28
2T23
4n7
+5V-TUN-PIN
9T20
RF-AGC
TUN-P3
AT11
18p
2T28
2T29
47R
18p
4n7
IT26
GND
9T31
2T15
IT20
10n
2T17
IT23
IT30
TUN-P7
MT
15
I
TUN-P5
4
VAGC
OUTPUT2
2T16
IT22
IT24
10n
2T18
IT25
6
IF-
IF+
10n
AGC CONTROL
D
+5V-TUN
TUN-P4
10K
3T17 RES
IF-AGC
2T21
13
MT
12
2T19
1
2
3
4
5
6
7
8
9
10
11
B-IF-_N-IFTUN-P1
TUN-P2
TUN-P3
TUN-P4
TUN-P5
9T25
TUN-P3
9T27
9T45
9T29
PDP
F
9T33
RES
5T12
2T20
B-IF+_N-IF+
ANTENNA-SUPPLY
10n
PDN
IT36
9T34
FT18
PDN
TUN-P8
IT34
10n
TUN-P11
TUN-P10
TUN-P9
TUN-P8
TUN-P7
TUN-P6
IT15
RF-AGC
TUN-P2
E
+3V3A
6K8
9T30
IF 1T21 IS USED THEN 2T23,2T25,3T14, 3T15, 9T13, 9T11 AND 9T21 ARE ALSO STUFFED
G
+5V-TUN
6K8
3T22
K
owner.
RF-AGC
L
22n
FT21
2T39
All rights reserved. Reproduction in whole or in parts
DC_PWR
NC1
RF_AGC
NC2
AS
SCL
SDA
XTAL_OUT
+5V
IF_OUT1
IF_OUT2
14
is prohibited without the written consent of the copyright
INPUT2
IT21
7
IT32
TUNER
RF-IN
IF-AGC
TUN-P9
3
OUTPUT1
RES
1T21
HD1816AF/BHXP
G
INPUT1
9T22
TUN-P2
IF 1T11 IS USED THEN 2T25 AND 9T11 ARE ALSO STUFFED
J
C
3T98
TUN-SDA
F
2
10n
TUN-P9
9T41
47R
5
4
O1
O2
OFWX6966M
36M125
4n7
2T26
I
IGND
B-IF+_N-IF+
TUN-P10
9T23
3T16
TUN-P6
H
9T21
2T27
IT14
3T15
TUN-SCL
E
3
TUN-P11
TUN-P10
TUN-P9
TUN-P8
TUN-P7
TUN-P6
TUN-P1
G
1
2
B-IF-_N-IFB-IF+_N-IF+
TUN-P1
TUN-P2
TUN-P3
TUN-P4
TUN-P5
F
IT19
1T25
12
1
2
3
4
5
6
7
8
9
10
11
100n
7T10
UPC3221GV-E1
13
9T32
RES
RF-IN
GND2
+5V-TUN-PIN
22u
2T14
5
TUNER
FT17
1
30R
2T12
+5V-TUN
4n7
VCC
C
2T13
TUN-P6
9T43
RES
5T11
+5V-TUN
DC_PWR
NC1
RF_AGC
NC2
AS
SCL
SDA
XTAL_OUT
+5V
IF_OUT1
IF_OUT2
E
1T11
HD1816AF/BHXP
9T14
TUN-P8
4n7
2T37
IT08
IT17
GND1
47R
TUN-P5
9T13
RES
2T36
8
IT10
3T14
TUN-SDA
RES
220n
220n
2T11
30R
2T25
2T35
18p
TUN-P4
2T10
BZX384-C33
6T10
D
IT04
3T13
TUN-SCL
FT22
TUN-P9
22K
3T12
100R
B-IF-_N-IFTUN-P11
IT12
+VTUN
3T19
FT23
100R
BZX384-C33
6T11
IT05
9T12
AT10
220K
3T11
+33VTUN
9T11
5T10
9T44
B
IT11
22n
3T18
TUN-P3
IT09
820n
3T10
IT03
9T10
RF-AGC
TUN-P1
RES
RESERVED
9T24
RES
C
TUN-P11
TUN-P10
TUN-P9
TUN-P8
TUN-P7
TUN-P6
H
H
M
I
1T01 A5
1T11 C5
1T21 E5
1T25 C10
2T10 B3
2T11 B3
2T12 C2
2T13 C12
2T14 C2
2T15 C10
2T16 C13
2T17 C10
2T18 C13
2T19 F10
2T20 G10
2T21 E11
2T22 B7
2T23 D5
2T25 B7
2T26 E5
2T27 D7
2T28 E5
2T29 E7
2T35 B5
2T36 B5
2T37 C7
2T39 H9
3T10 B2
3T11 B2
3T12 B2
3T13 B5
3T14 B5
3T15 E5
3T16 E5
3T17 E11
3T18 E11
3T19 E11
3T22 G9
3T98 E11
5T10 B7
5T11 C2
5T12 F11
6T10 B2
6T11 B2
7T10 C11
9T10 B5
9T11 B7
9T12 B5
9T13 B7
9T14 C10
9T18 D5
9T20 D5
9T21 D7
9T22 D10
9T23 D7
9T24 E9
9T25 F5
9T27 G5
9T29 G7
9T30 G5
9T31 C13
9T32 D13
9T33 F11
9T34 G11
9T40 B7
9T41 E7
9T43 C10
9T44 D10
9T45 G7
AT10 B7
AT11 D7
FT17 C2
FT18 G5
FT21 H9
FT22 B3
FT23 B2
IT03 B5
IT04 B5
IT05 B1
IT08 C1
IT09 B5
IT0D B7
IT10 B5
IT11 B7
IT12 B7
IT13 B7
IT14 E5
IT15 F5
IT16 B9
IT17 B11
IT19 C10
IT20 C11
IT21 C12
IT22 C13
IT23 C11
IT24 C12
IT25 C13
IT26 D10
IT28 D7
IT30 D9
IT32 D11
IT34 F11
IT36 G11
A
B
C
D
E
F
G
H
I
J
K
L
M
I
N
N
1
2
3
4
5
6
7
8
9
11
10
12
14
13
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
FRONT-END
P
8204 000 8929
TV543 R2 LDIPNX
2008-10-10
NAME Randal De Keyzer
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
3
2008-06-03
130
C
17
A2
1
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_503_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 89
SSB: Demodulator
1
4
3
2
1
A
5
2
6
4
3
8
7
9
6
5
8
7
14
13
12
11
10
9
15
10
16
11
17
12
18
13
DEMODULATOR
IT50
2T50
+3V3E
1T50
2T51
2T58
10n
RES
100n
32
2R2
BAS316
2R2
3T62
470R
FT61
3T56
+5V-TUN-CVBS
2
10K
3T76
4
IT80
7T52-2
BC847BPN(COL)
3T73
IT83
7T53-1
RES
BC857BS(COL)
6
2
100R
5
7T52-1
BC847BPN(COL) 3
1
3T77
IT81
1
IT96
220R
CVBS-TER-OUT
180R
3T95
3T78
2K2
100R
E
+5V-TUN-CVBS
FT62
9T63
3T74
6
150R
18K
3T75
68R
3T71
4
IT97
7T53-2
RES
BC857BS(COL)
3
5
3T79
IT77
22u
22u
2T63
2T61
IT76
CVBS4
FT55
+5V-TUN-CVBS
7T54
LD1117DT12
RESERVED
3
+3V3
IN
3T88
10K
6K8
3T91
27K
J
2
OUT
+1V2
F
COM
RES 100n
2T64
2
7T55-1
LM393PT
1
IT91
4
IT90
8
IT88
3
3T90
3p3
2T62
D
100R
9T62
+12V
IT89
27K
3T89
RES 10K
3T81
3T70
9T64
3T87
F
IF-P
150R
RESERVED
150R
+1V2-PNX85XX
220R
3T86
I
IT75
RES
1
3T84
3T82
3T64
150R
150R
3T83
3
3T69
6T51
RES 10K
3T80
RES 10K
2
16
27
56
52
36
VDDAL_AFE1
46
VDDAL_AFE2
42
8
18
26
53
VSSL
7T51-2
BC847BPN(COL)
7T51-1
RES
BC847BPN(COL) 3
RES
FT60
3T65
10K
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
C
4
IT73
5
100K
7T56
BCP56
IT85
22n
2T85
VSSH
+5V-TUN-CVBS
18K
3T63
29
VIA
IT86
FT56
5T51
+1V2A
+1V2
5
2u2
7T55-2
LM393PT
100n
100n
2T72
2u2
2T71
2T70
100n
100n
2T69
100n
2T68
2T66
100n
2T67
G
7
6
5T52
FT57
+3V3E
+3V3
5T53
H
100n
30R
4K7
3T94
2K7
RESERVED
FT58
H
+3V3D
+3V3
100n
2u2
2T76
30R
2T75
5T54
FT59
+3V3A
+3V3
M
100n
2T81
100n
100n
2T80
2u2
2T79
2u2
2T78
2T77
600R
2u2
2T82
L
IT95
2T73
+3V3
10K
2u2
2T74
K
3T93
IT94
4
ANTENNA-CTRL
3T92
2T24
IT93
8
+12V
G
100u 4V
2T65
600R
owner.
is prohibited without the written consent of the copyright
100n
43
FT20
1
B
RF-AGC
IF-AGC
IT70 3T60
2T60
64
63
1
VSYNC
38
2
4
+5V-TUN
IT84
4K7
All rights reserved. Reproduction in whole or in parts
IT63
IT69
DA
I2S CL
WS
VIA
IT98
+12V
IT62
3T72
100n
2T83
6T50
100n
2T84
BZX384-C6V8
ANTENNA-SUPPLY
IT79
+5V-TUN
3T68
IT58
470R
+3V3
4K7
E
FE-CLK
FE-VALID
FE-DATA0
FE-DATA1
FE-DATA2
FE-DATA3
FE-DATA4
FE-DATA5
FE-DATA6
FE-DATA7
IT59
44
SIF
GPIO1
GPIO2
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
3T67
H
FE-SOP
33
34
CVBS
TCK
TDI
TDO
TMS
4
30
+3V3
G
SCL2
I2C
SDA2
59
60
57
58
7
8
3T66-1
1
+3V3
+3V3
+3V3
4K7
62
61
GND_HS
3T61
ANTENNA-CTRL
D
RF_AGC
IF_AGC
10K
FT50
65
+3V3
RES 10K
RES 10K
3 3T66-3 6
F
4 3T66-4 5
FT51
FT52
FT53
FT54
23
24
FT24
4K7
3
15
28
55
FT25
JTAG-TCK-DRXK
JTAG-TDI-DRXK
JTAG-TDO-DRXK
JTAG-TMS-DRXK
IT67
3T59
RES 10K
9T70
9T71
TUN-SCL
TUN-SDA
VSSAH_AFE1
100R
3T66-2
C
TUN-SCL
TUN-SDA
+3V3
3T58
100R
RES 10K
E
9T15 RES
9T16 RES
SCL1
I2C
SDA1
RSTN
5
6
9
10
11
12
13
14
19
20
21
22
3T51
IT66
3T57
IT68
2
IT65
SCL-SSB
SDA-SSB
SAW_SW
P
PD
N
31
SCL-SSB
SDA-SSB
VDDL
7
17
25
54
IT61
RESET-SYSTEM
47
48
IT60
2T57
35
VSSAL_AFE1
45
VSSAL_AFE2
560R
40
39
RES
100n
VDDH
Φ
DEMODULATOR
VSSAH_OSC
3T55
XO
IT57
2T56
A
+3V3
+1V2
MSTRT
MERR
MCLK
MVAL
0
1
2
3
MD
4
5
6
7
51
D
50
VSSAH_CVBS
3T54
10n
XI
VDDAH_OSC
22p
2p2
2T53
2T55
560R
PDN
49
IT55
100p
IT56
470R
3T53
PDP
IT53
2T54
220R
B
7T50
DRX3926K-XK-A2
100p
AT51
+3V3
IT51
12p
41
IF-
680n
3T52
2T59
C
5T50
220R
2T52
37
AT50
3T50
IF+
+1V2A
+3V3D
+3V3A
VDDAH_AFE1
A
27M
12p
VDDAH_CVBS
B
I
I
5T55
FT63
+5V-TUN-CVBS
+5V-TUN
N
30R
1
2
4
3
5
7
6
8
9
10
11
12
20
19
1T50 A5
2T24 G5
2T50 A4
2T51 A4
2T52 A4
2T53 B3
2T54 B4
2T55 B3
2T56 B4
2T57 B3
2T58 B4
2T59 B3
2T60 C8
2T61 E10
2T62 D12
2T63 D9
2T64 F6
2T65 G6
2T66 G6
2T67 G7
2T68 G7
2T69 G7
2T70 G7
2T71 G8
2T72 G8
2T73 H6
2T74 H7
2T75 H6
2T76 H7
2T77 I6
2T78 I6
2T79 I6
2T80 I7
2T81 I7
2T82 I7
2T83 E4
2T84 E3
2T85 E2
3T50 A2
3T51 A10
3T52 B2
3T53 B2
3T54 B3
3T55 B2
3T56 D11
3T57 C3
3T58 C4
3T59 C4
3T60 C9
3T61 C4
3T62 C9
3T63 C9
3T64 C9
3T65 C9
3T66-1 D4
3T66-2 D4
3T66-3 D3
3T66-4 D4
3T67 D4
3T68 E2
3T69 E3
3T70 D9
3T71 D9
3T72 E9
3T73 E11
3T74 E12
3T75 E9
3T76 E9
3T77 E9
3T78 E11
3T79 E12
3T80 A9
3T81 A9
3T82 A9
3T83 E3
3T84 F3
3T86 F3
3T87 F3
3T88 F5
3T89 F3
3T90 F3
3T91 F5
3T92 G3
3T93 G3
3T94 H3
3T95 E9
5T50 B3
5T51 G7
5T52 G6
5T53 H6
5T54 I7
5T55 I6
6T50 E3
6T51 F2
7T50 A6
7T51-1 C9
7T51-2 C10
7T52-1 E9
7T52-2 E10
7T53-1 E11
7T53-2 E11
7T54 F7
7T55-1 F4
7T55-2 G4
7T56 E3
9T15 C1
9T16 C1
9T62 F6
9T63 E11
9T64 F6
9T70 C2
9T71 C2
AT50 A4
AT51 B4
FT20 E6
FT24 C5
FT25 C3
FT50 B8
FT51 C3
FT52 C3
FT53 C3
FT54 C3
FT55 F7
FT56 G8
FT57 G6
FT58 H7
FT59 I7
FT60 C10
FT61 D11
FT62 E11
FT63 I6
IT50 A5
IT51 A5
IT53 B5
IT55 B4
IT56 B3
IT57 B4
IT58 B10
IT59 B9
IT60 B4
IT61 B3
IT62 B9
IT63 B9
IT65 C3
IT66 C4
IT67 C4
IT68 C3
IT69 C8
IT70 C9
IT73 C9
IT75 D9
IT76 D8
IT77 D9
IT79 D3
IT80 E9
IT81 E10
IT83 E9
IT84 E2
IT85 E3
IT86 F6
IT88 F6
IT89 F3
IT90 F3
IT91 F4
IT93 G2
IT94 G3
IT95 G3
IT96 E11
IT97 E11
IT98 E5
A
B
C
D
E
F
G
H
I
J
K
L
M
N
13
O
O
SETNAME
2
CLASS_NO
2008-11-21
FRONT-END
P
8204 000 8929
TV543 R2 LDIPNX
2008-10-10
NAME Randal De Keyzer
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
3
SUPERS.
DATE
16
2008-06-03
130
C
17
2
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_504_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 90
SSB: PNX8543 - Stand-by Controller
1
1
A
4
3
2
5
3
2
8
7
6
4
9
6
5
11
10
7
13
12
8
9
14
16
15
11
10
18
17
12
13
1HF0 A4
2H00 C3
2H01 E3
2H03 F6
2H10 D11
2H11 H7
2H12 H6
2HC0 H13
2HD0 F12
2HF0 A3
2HF1 B3
3H00 E2
3H01 E2
3H02 B11
3H03 B11
3H04 B11
3H05 B11
3H06 C11
3H07 C11
3H08 C11
3H10 B2
3H12 C12
3H13 B1
3H14 B2
3H15 B1
3H16 B2
3H17 B1
3H19 B2
3H20 C1
3H21 C2
3H22 C13
3H23 C1
3H24 C2
3H25 C13
3H26 C1
3H27 C2
3H28 C1
3H30 D2
3H31 D1
3H32 B11
3H36 D2
3H39 C2
3H41 H6
3H42 C1
3H43 H7
3H44 I4
3H46 C2
3H48 C1
3H51 C2
3H52 I13
3H53 I13
3H54 C7
3H56 C7
3H58 D2
3H60 D1
3H64 D2
3H65 B7
3H66 B7
3H67 B7
3H68 B7
3H69 C7
3H70 E2
3H72 G7
3H78-1 E6
3H78-2 E5
3H78-3 H4
3H78-4 H4
3H86-1 F4
3H86-2 F4
3H86-3 F3
3H86-4 F2
3H87-1 I2
3H87-2 I3
3H87-3 I3
3H87-4 I4
3H92-1 G4
3H92-2 G4
3H92-3 G3
3H92-4 H3
3HC2-1 H12
3HC2-2 G12
3HC2-3 H12
3HC2-4 H13
3HD4 E13
6H10 H7
6HW2 F5
7H00-6 A5
7H02 D10
7H03 C13
7H11 H8
7H14 F6
7H16-1 F5
7H16-2 G5
7H93-1 H5
7H93-2 I5
7HC3 H12
7HC4 H12
7HD0 E12
9H05 D13
9H13 G8
9H14 E11
9H15 F11
9H25 E3
9H26 E3
9H27 E3
9H28 H13
FH09 H12
FHC1 H13
FHC2 I14
FHC3 C5
FHC6 H11
14
PNX 8543 : STANDBY CONTROLLER
A
7H00-6
PNX85439EH/M2/24182
STANDBY
I
XTAL
RES
10K
C
10K
3H46
27K
3H51
3H21
10K
RES
10K
3H24 RES
10K
3H27
10K
3H30
10K
3H23
+3V3-STANDBY
10K
3H26
10K RES
RES
10K
3H28
3H31
10K
+3V3-STANDBY
F
3H60
10K
MHP-SWITCH
EJTAG-DETECT
LAMP-ON
STANDBY
DETECT1
DETECT2
POWER-OK
ENABLE-3V3
3H58
IH02
RESET-SYSTEM
3H70
KEYBOARD
100K
2H01
100n
3H00
3H01
SPI-PROG
SPI-WP
3H05
10K
AE2
PSEN
0
1
2 P1
3
7
AE3
ALE
AF4
EA
3H54
100R
100R
3H56
PSEN
ALE
EA
100R
AF3
3H06
PSEN
ALE
IH32
10K
3H07
IH37
3H08
10K
EA
+3V3-PER
+5V
+3V3-PER
C
10K
RESET-STBY
+3V3-STANDBY
IH09
7H03
BC847BW
FHD2
0 UA_RX
1 UA_TX
2
P3
3
4
5
7H02
M25P05-AVMN6
5
6
SPI-CLK
IH06
1
SPI-CSB
IH07
3
SPI-WP
AK2
4
AK4
P6
5
7
D
C
Φ
512K
FLASH
LAMP-ON
Q
D
LAMP-ON-OUT
IH01
2
SPI-SDI
S
W
HOLD
VSS
+3V3-STANDBY
SPI-PROG
SPI-WP
9H05
RES
VCC
IH00
SPI-SDO
+3V3-STANDBY
E
+3V3-STANDBY
IH16
10K
9H14
1
10K
3H78-1
2
7H16-1
BC847BS(COL)
1
NC GND
3
2
CD
RESET-STBY
1
OUTP
5
4
IH19
7
10K
INP
IHD0
FHD0
F
100n
3H86-2
1
2HD0
2
3
10K
FHD1
DETECT2
RES
3H86-3
DETECT1
7H14
PDTC114EU
1
9H15
6
6HW2
5
10K
BAS316
3H86-4
10K
4
1 3H86-1 8
+3V3
IH92
IH20
3
IH14
6
F
7HD0
NCP303LSN30
2
8
*
2
*
9H27
3H78-2
9H26
7
* HOTEL TV
RC
RC-UP
RC
RC-OUT
RC-UP
RC-IN
3HD4
+3V3-STANDBY
H
2H03
1u0
3
IH04
3
RES
+3V3-STANDBY
10K
IH33
BAS316
IH36
6H10
IH35
5
INP
OUTP
CD
3H87-1
10K
8
10K
10K
10K
7 3H87-2 2
3 3H87-3 6
5 3H87-4 4
3 3HC2-3 6
100n
2H11
3K3
IH21
7H93-2
BC847BS(COL)
3
IH18
9H28
10K
7HC3
M24C64
10K
3H43
2H12
2HC0 RES
IHC1
+3V3-PER
1
2
3
100n
Φ
(8Kx8)
EEPROM
0
1
2
ADR
SDA
5
4
3H44
I
WC
SCL
H
7
6
5
FHC1
3H52
100R 3H53
FHC2
SCL-UP-MIPS
SDA-UP-MIPS
100R
4
1
10K
1
NC GND
RES
BC857BW
7HC4
I
FHC7
10K
+5V
M
IH08
100n
IH91
FH09
8 3HC2-1 1
10K
3H41
DETECT-12V
FHC6
4 3HC2-4 5
7H93-1
BC847BS(COL)
1
4
H
5 3H78-4 4
L
2
10K
3 3H78-3 6
10K
RESET-NVM
8
IH26
5 3H92-4 4
9H13
7H11
NCP303LSN30
2
10K
IH34
2 3HC2-2 7
IHC2
6
+1V2-PNX5100
G
+3V3-PER
IH17
3
K
7H16-2
BC847BS(COL)
4
4K7
1 3H92-1 8
G
5
3H72
10K
10K
3H92-3
10K
6
7 3H92-2 2
J
+1V2-PNX85XX
owner.
All rights reserved. Reproduction in whole or in parts
4K7
10K
4
10K
3H03 RES
3H04
LED2
10K
9H25
is prohibited without the written consent of the copyright
RES
LED1
IH15
3H69
AN3
0
AN2
1
AP2
CADC
2
AP1
3
RESET-SYSTEM
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS
10K
I
4K7
IH03
3H64 RES
E
LED1
LED2
B
10K
3H02 RES
SCL-UP-MIPS
SDA-UP-MIPS
0
1
2
3
P2
4
5
6
7
AG1
AH5
AH4
AH3
AH2
AH1
RXD-UP
TXD-UP
BOLT-ON-IO
0
1
RESET_IN
AC4
AC3
AE1
AD5
AD4
AD3
AE5
AE4
BOLT-ON-IO
10K
G
AF2
AF1
AG4
AG3
AG2
IHWB
IHWC
IHWD
IHWF
IHWG
IHWH
IHWM
IHWN
MHP-SWITCH
EJTAG-DETECT
LAMP-ON
STANDBY
DETECT1
DETECT2
POWER-OK
ENABLE-3V3
RXD-UP
TXD-UP
10K
3H36 RES
D
RC-UP
REGIMBEAU_CVBS-SWITCH
CEC-HDMI
SUPPLY-FAULT
SDM
3H67
100R
100R
3H68
10K
E
3H42
3H48
10K
FHC3
AJ3
AJ2
PWM
SCL-UP-MIPS
SDA-UP-MIPS
10K
+3V3-STANDBY
3H39
3H65
100R
3H25
10K
3H66
1
3H20
AL5
SCL
AK5
SDA
100R
MC
0
1
2
3
P0
4
5
6
7
2
3H19
4K7
AC2
AC1
AB3
AB2
AB1
AD2
AD1
AC5
+3V3-STANDBY
3H22
3H16
IHW1
IHW3
IHW4
IHW5
IHW2
IHW6
IHW9
IHWA
BOLT-ON-TS-ENn
RESET-NVM
RESET-PNX5100
RESET-ETHERNET
UART-SWITCH
WP-NANDFLASH
RESET-AUDIO
AUDIO-MUTE
3H32
SPI-SDI
3
3H17
D
BOLT-ON-TS-ENn
RESET-NVM
RESET-PNX5100
RESET-ETHERNET
UART-SWITCH
10K
WP-NANDFLASH
RESET-AUDIO
AUDIO-MUTE
2H00
1n0
RC-UP
REGIMBEAU_CVBS-SWITCH
CEC-HDMI
SUPPLY-FAULT
SDM
10K
3H14 RES
10K
10K
RES
10K
RES
10K
3H15
SPI-CLK
SPI-CSB
SPI-SDI
SPI-SDO
3H12
3H10
3H13
+3V3-STANDBY
AJ1
CLK
AK3
CSB
AK1
SDI
AJ4
SDO
4K7 RES
B
VSS_XTAL
4K7
W3
RES
SPI
O
100n
RES
W2
2H10
22p
2HF1
W1
C
8
22p
1HF0
27M
A
2HF0
B
MAIN NVM
N
1
2
4
3
5
6
O
7
9
8
10
11
13
12
20
19
FHC7 I13
FHD0 E13
FHD1 F11
FHD2 D13
IH00 D10
IH01 D11
IH02 D3
IH03 D10
IH04 G4
IH06 D10
IH07 D10
IH08 H5
IH09 C13
IH14 F5
IH15 C10
IH16 F5
IH17 G5
IH18 I4
IH19 F4
IH20 F7
IH21 I12
IH26 H4
IH32 C10
IH33 H7
IH34 G8
IH35 H7
IH36 H7
IH37 C10
IH91 H4
IH92 F9
IHC1 H12
IHC2 G12
IHD0 F12
IHW1 B4
IHW2 B4
IHW3 B4
IHW4 B4
IHW5 B5
IHW6 B4
IHW9 B4
IHWA C5
IHWB C4
IHWC C4
IHWD C4
IHWF C5
IHWG C4
IHWH C4
IHWM D4
IHWN D5
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
1X03
EMC HOLE
CHN
SETNAME
2
CLASS_NO
2008-11-21
STANDBY CONTROLLER
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Randal De Keyzer
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
130
16
2007-11-29
C
17
A2
1
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_505_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 91
SSB: PNX8543 - Debug
1
Personal Notes:
4
3
2
6
5
A
A
1H11 C2
B
2H06 C3
2H07 D3
3HF3 A3
6HF0 B3
1
FH00 C2
FH08 D3
IH93 C2
IH94 C3
B
IH95 D2
4
3
C
PNX8543 : DEBUG
A
A
+3V3-PER
SML-310
6HF0
E B
D
330R
3HF3
D
BE
7HF2
PDTC114EU
RESET-SYSTEM
SPI-PROG
G
SDM
D
F
2H06 RES
TSTPOINT
FOR DEBUG
C
100p
SPI-PROG
IH94
GND TSTPOINT
FOR DEBUG
3
SKHUBHE010
1H11
2
C
IH93
FH00
1
F
4
owner.
FH01 D2
2
C
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
7HF2 B3
IH95
FH01
TSTPOINT
FOR DEBUG
SDM
G
2H07 RES
D
100p
FH08
H
H
1
2
3
4
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
DEBUG STBY CTRL
J
2008-10-10
J
8204 000 8927
PNX8543 TV543 R2 LDIPNX
3
NAME Maelegheer Ingrid
CHECK
1
SUPERS.
DATE
2
16
2007-11-29
130
3
A4
2
ROYAL PHILIPS ELECTRONICS N.V. 2005
C
4
5
10000_012_090121.eps
090121
6
18310_506_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 92
SSB: PNX8543 - Control
1
4
3
2
1
2
5
6
3
8
7
4
5
9
6
7
12
11
10
8
13
9
A
PNX8543 : CONTROL
A
A
10K
B
3HF9
+3V3-PER
7H00-8
PNX85439EH/M2/24182
+3V3-PER
C
+3V3-PER
E
EJTAG-TCK
EJTAG-TDI
EJTAG-TDO
EJTAG-TMS
EJTAG-TRSTN
10K
3HFY
IHS8
BOOTMODE
10K
10K
10K
10K
3H11
3HP8
3HPC
3HPL
10K
10K
3HPP
3HPR
IH12
IRQ-PCI
IRQ-CA
RXD-MIPS
TXD-MIPS
TXD-MIPS2
RXD-MIPS2
EJTAG-TCK
EJTAG-TDI
EJTAG-TDO
EJTAG-TMS 33R
EJTAG-TRSTN
AN4
AP3
AP4
AM4
AL4
3HPW
U2
U3
U4
IHF7 L34
L32
L31
V2
V3
V4
V5
BOOTMODE
WC-EEPROM-PNX5100
IRQ-PCI
IRQ-CA
RXD-MIPS
TXD-MIPS
IHF6
IHF8
IHF9
IHFA
RESET_SYS
TCK
TDI
EJTAG
TDO
TMS
TRSTN
9H17
RES
AP29
F33
SCL 1
H33
SDA 1
SCL1
SDA1
D32
SCL 2
B33
SDA 2
SCL2
SDA2
D33
SCL 3
G32
SDA 3
SCL3
SDA3
B
USB20-DM
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
DM
DP
FAULT
USB
PWR_EN
RREF
AN16
AP16
AL16
AK16
AM16
USB20-DM
USB20-DP
USB-OC
FH03
3HP2
AM17 3H37
USB_RPU
AP17
USB_ID
AN17 3H45
USB_VBUS
CLK_27_OUT
1K5
3H38
10K
C
USB20-DP
12K 1%
AK27
AL27 UA2_TX
UA2_RX
TXD-MIPS2
RXD-MIPS2
PCI-CLK-OUT
CONTROL
BL_PWM
15K
D
3HP3
3HP4
3HP6
3HPA
3HPB
AN28
3H33
RESET-SYSTEM
10K
10K
10K
10K
10K
AP27
IHFB
15K
IHF4
3H09
B
+3V3-PER
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
10K
+3V3-PER
+3V3-PER
D
D
F
3HPD
SCL1
G
E
SDA1
3HPE
100R
100R
3HPF RES
SCL2
SDA2
RES 3HPG
100R
100R
3HPH
3HPJ
100R
SCL3
SDA3
SCL-UP-MIPS
SCL-UP-MIPS
SDA-UP-MIPS
SDA-UP-MIPS
H
SDA2
F
D
E
F
3H50
E
4K7
G
SCL-UP-MIPS
SCL-SSB
SCL-SSB
SDA-SSB
SDA-SSB
SCL-SET
SCL-SET
SDA-SET
SDA-SET
FH04
3HPK
+3V3-PER
FH05
1K5
3HPM
1K5
100R
FH11
3HPT
FH12
4K7
+3V3-PER
3
H
3HPV
F
4K7
2
1
C
+3V3-PER
4K7
100R
I
B
SDA-UP-MIPS
3HPS
3HPU
A
3H49
100R
SCL2
3H09 C6
3H11 C1
3H33 C6
3H37 D4
3H38 D5
3H45 D4
3H49 E4
3H50 E4
3HF9 A3
3HFY C1
3HP2 C4
3HP3 B1
3HP4 B1
3HP6 B1
3HP8 C1
3HPA C1
3HPB C1
3HPC C1
3HPD E2
3HPE E2
3HPF E2
3HPG E2
3HPH E2
3HPJ F2
3HPK E4
3HPL C1
3HPM F4
3HPP D1
3HPR D1
3HPS F2
3HPT F4
3HPU F2
3HPV F4
3HPW B3
7H00-8 B3
9H17 D3
FH03 C5
FH04 E4
FH05 F4
FH11 F4
FH12 F4
IH12 C1
IHF4 B3
IHF6 C3
IHF7 C3
IHF8 C3
IHF9 C3
IHFA C3
IHFB B3
IHS8 C1
4
5
7
6
CH N
8
9
I
SETNAME
2
CLASS_NO
2008-11-21
MIPS , I2C & EJTAG
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8927
PNX8543 TV543 R2 LDIPNX
8
9
130
16
SUPERS.
DATE
2007-11-29
C
10
A3
5
ROYAL PHILIPS ELECTRONICS N.V. 2005
11
12
13
18310_507_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 93
SSB: PNX8543 - Control
2
1
3
4
6
5
8
7
9
10
11
12
13
A
A
1
2
3
4
A
D
A29
B29
C29
D29
A28
B28
C28
D28
E28
A27
B27
C27
D27
E27
A26
B26
E24
D24
C24
B24
A24
E23
D23
C23
B23
A23
E22
D22
C22
B22
A22
E21
PCI-AD0
PCI-AD1
PCI-AD2
PCI-AD3
PCI-AD4
PCI-AD5
PCI-AD6
PCI-AD7
PCI-AD8
PCI-AD9
PCI-AD10
PCI-AD11
PCI-AD12
PCI-AD13
PCI-AD14
PCI-AD15
PCI-AD16
PCI-AD17
PCI-AD18
PCI-AD19
PCI-AD20
PCI-AD21
PCI-AD22
PCI-AD23
PCI-AD24
PCI-AD25
PCI-AD26
PCI-AD27
PCI-AD28
PCI-AD29
PCI-AD30
PCI-AD31
B
E
C
F
PCI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCI_AD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D21
0
C21
1
PCI_CBE
B21
2
A21
3
CLK
DEVSEL
FRAME
IDSEL
INTA_OUT
IRDY
PAR
TRDY
PERR
SERR
STOP
TRDY
PCI-CBE0
PCI-CBE1
PCI-CBE2
PCI-CBE3
A30
A25
C26
B30
C30
D26
E25
C25
D25
B25
E26
PCI-CLK-PNX8535
PCI-DEVSEL
PCI-FRAME
PCI-AD24
IH30
PCI-IRDY
PCI-PAR
PCI-PERR
PCI-SERR
PCI-STOP
PCI-TRDY
3HEU
100R
D30
REQ
E30
GNT
REQ_B
GNT_B
PLL_OUT
PCI-REQ
PCI-GNT
E31
E29
AP28
PCI-REQ-B
PCI-GNT-B
IHS7
9HG3
7
2HF5 D7
2HF6 D7
2HF7 D7
3HES-1 C5
3HES-2 B5
3HES-3 C5
3HES-4 C5
3HEU B3
3HF2 E2
3HF4 E2
3HF5 C3
3HFD-1 A6
3HFD-2 A5
3HFD-3 A6
3HFD-4 A5
3HFE-1 A6
3HFE-2 A6
3HFE-3 A6
3HFG D2
3HFH E2
3HFK E7
3HFM E7
3HFN E7
3HFP E7
3HFR E5
7H00-3 A2
7HF1 D6
9HF4 C6
9HF5 C6
9HF6 B6
9HF7 B6
9HG3 C3
IH30 B4
IHF0 E2
IHF1 C3
IHF2 C3
IHF3 D3
IHF5 E2
IHS7 C3
8
4
3HFD-1 8
2
3HFD-3 6
2 3HFE-2
3 3HFE-3
3HFE-1 8
A
1
4K7
3
4K7
+3V3-PER
1
4K7
B
9HF6
2
4K7
7 3HES-2
3
4K7
6 3HES-3
1
4K7
8 3HES-1
4
4K7
5 3HES-4
PCI-REQ-ETH
+3V3-PER
9HF7
PCI-REQ
PCI-GNT
PCI-GNT-ETH
+3V3-PER
9HF4
PCI-REQ-B
PCI-REQ-MINI
+3V3-PER
9HF5
PCI-GNT-B
PCI-CLK-OUT
A20
XIO_ACK
B19
XIO_AD25
3HFD-4 5
4K7
3HFD-2 7
4K7
7
4K7 6
4K7
PCI-DEVSEL
PCI-FRAME
PCI-IRDY
PCI-TRDY
PCI-STOP
PCI-PERR
PCI-SERR
7H00-3
PNX85439EH/M2/24182
C
PCI-GNT-MINI
+3V3-PER
C
XIO-ACK
B20
0
C20 IHF1
1
D20 IHF2
XIO_SEL
2
E20 IHF3
3
3HF5
B
C
D
E
XIO-SEL-NAND
100R
F
RESERVED
+3V3-PER
2HF5
D
3HFG
PCI-CLK-OUT
Φ
PCI-CLK-ETHERNET
3HFH
PCI-CLK-PNX5100
10R
IHF5
3HF2
E
3HFR
PCI-CLK-OUT
1
REF
1
2
CLK
33R
3
PCI-CLK-PNX8535
4
10R
3HF4
*
GND
PCI-CLK-MINI
10R
G
VDD
ZERO
DELAY
BUFFER
10R
IHF0
100n
6
7HF1
CY2305S
G
H
D
10n
2HF6
CLKOUT
3
2
2HF7
10p
3HFK
PCI-CLK-ETHERNET
33R
7
8
PCI-CLK-PNX8535
3HFP 33R
5
4
owner.
6
PNX 8543 : CONTROL
B
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
5
E
3HFM
H
PCI-CLK-PNX5100
33R
3HFN
PCI-CLK-MINI
33R
I
I
1
2
3
4
5
6
CHN
7
8
SETNAME
2
CLASS_NO
2008-11-21
CONTROL
J
2008-10-03
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
8
SUPERS.
DATE
9
16
2007-11-29
130
C
10
J
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2
6
A3
ROYAL PHILIPS ELECTRONICS N.V. 2005
11
12
13
18310_508_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 94
SSB: PNX8543 - SDRAM
1
1
A
3
2
4
2
6
5
3
7
4
9
8
5
6
11
10
7
12
8
14
13
9
10
15
16
11
17
12
19
18
13
20
2HG0 E3
2HG1 E3
2HG2 E3
2HG3 E3
2HG4 E3
2HG5 E4
2HG6 E4
2HG7 E4
2HG8 E4
2HG9 E6
2HGA E7
2HGB E7
2HGC E7
2HGD E7
2HGE E7
2HGF E8
2HGG E8
2HGH E9
2HGJ E9
2HGK E9
2HGM E9
2HGN E10
2HGP E10
2HGR E10
2HGS E10
2HGT E10
2HGU E12
2HGV E13
2HGW E13
2HGY E13
2HGZ E13
2HH0 E13
2HH1 E14
2HH2 E14
2HH3 H13
2HH4 C8
2HH5 C8
2HHA H7
2HHB A11
2HHK E6
2HHM E6
2HHN E11
2HHP E12
3HGP F7
3HGR F7
3HGS F8
3HGT G7
3HGU G8
3HGV G7
3HGW G8
3HGY G7
3HGZ G8
3HH0 G7
3HH1 G8
3HH2 G7
3HH3 G8
3HH4 G7
3HH5 G8
3HH6 G7
3HH7 H3
3HH8 H4
3HH9 H3
3HHA H4
3HHB F13
3HHC F13
3HHD G14
3HHE F13
3HHF G13
3HHG G13
3HHH G14
3HHJ G13
3HHK G14
3HHM G13
3HHN G14
3HHP G13
3HHR G14
3HHS G13
3HHT G14
3HHU G13
3HHV H10
3HHW H10
3HHY H9
3HHZ H10
3HJ0 C1
3HJ1 A11
3HJ2 B11
3HJ3 A13
3HJ4 B13
3HJ5 C8
3HJY C8
3HKM G3
3HKN G10
7H00-2 A7
7HG0 F5
7HG1 F11
FH06 A12
FH07 A11
IHG0 C7
14
PNX 8543 : SDRAM
7H00-2
PNX85439EH/M2/24182
B
D
3HJ0
DDR2-CLK_P
DDR2-CLK_N
220R
E
C
F
W31
DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3
AJ34
0
AJ31
1
R34
M_DQM
2
R31
3
M_CKE
M_CSB
DDR2-DQS0_N
DDR2-DQS0_P
AG33
N
AG34 M_DQS0
P
DDR2-DQS1_N
DDR2-DQS1_P
AH31
N
AH32
M_DQS1
P
DDR2-DQS2_N
DDR2-DQS2_P
N34
N
N33
M_DQS2
P
DDR2-DQS3_N
DDR2-DQS3_P
N31
N
N32
M_DQS3
P
IREF
ODT
WEB
DDR2-VREF-DDR
B
C
+1V8-PNX85XX
3HJ5
5K6
V31
2HH4
3HJY
V32
M RASB
VREF
IHG0
AA31
3HJ3
DDR2-CS
M_CASB
1K0 1%
AB33
N
AB34
M_CLK
P
FH06
FH07
DDR2-VREF-CTRL
3HJ4
AE31
DDR2-CLK_N
DDR2-CLK_P
2HHB
W32
DDR2-CKE
330u 6.3V
DDR2-CAS
+1V8-PNX85XX
A
3HJ1
AC34
0
AD33
1 M_BA
AA32
2
+1V8-PNX85XX
1K0 1%
DDR2-BA0
DDR2-BA1
DDR2-BA2
DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29
1K0 1%
C
AH34
0
AK33
1
AH33
2
AL34
3
AL33
4
AE34
5
AK34
6
AF34
7
AG32
8
AK31
9
AJ32
10
AL32
11
AL31
12
AF31
13
AK32
14
AF32
15
P34
M_DQ
16
T34
17
R33
18
U34
19
V34
20
M33
21
T33
22
M34
23
P31
24
T32
25
P32
26
U31
27
U32
28
M31
29
R32
30
M32
31
3HJ2
A
AA34
0
AE33
1
AA33
2
AD31
3
Y34
4
AD32
5
W33
M_A
6
AC32
7
W34
8
Y31
9
AD34
10
V33
11
Y32
12
1K0 1%
B
MEMORY
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
820R
2HH5
AB32
100n
DDR2-VREF-CTRL
100n
AE32
DDR2-ODT
DDR2-RAS
DDR2-WE
D
DDR2-DQS0_P
DDR2-DQS0_N
L H
DDR2-DQS1_P
DDR2-DQS1_N
3HH9
33R
J8
K8
F7
E8
3HHA
33R
3HH7
33R
B7
A8
3HH8
33R
0
1
2
3
4
5
6 A
7
8
9
10
11
12
DQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
UDM
LDM
CK
VREF
LDQS
A3
E3
J3
N1
P9
VSS
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
33R
3HGT
33R
3HGV
33R
3HGY
33R
3HH0
33R
3HH2
33R
3HH4
33R
3HH6
DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
33R
3HGS
33R
3HGU
33R
3HGW
33R
3HGZ
33R
3HH1
33R
3HH3
33R
3HH5
33R
J2
2HHA
100n
L2
L3
L1
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-DQM1
DDR2-DQM0
DDR2-VREF-DDR
RES
220R
DDR2-CLK_P
DDR2-CLK_N
DDR2-DQS2_P
DDR2-DQS2_N
3HHY
33R
EDE1116AEBG-8E
0
1
2
3
4
5
6 A
7
8
9
10
11
12
DQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
UDM
LDM
CK
3HHW
B7
A8
UDQS
VREF
VSS
22u
100n
2HH2
100n
2HH1
100n
2HH0
100n
2HGZ
100n
2HGY
100n
2HGW
A2
E2
R3
R7
R8
NC
0
1 BA
2
LDQS
100n
2HGV
2HGU
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDDQ
Φ
SDRAM
F7
E8
33R
VSSQ
VDD
ODT
CKE
WE
CS
RAS
CAS
3HHZ
33R
3HHV
33R
DDR2-DQS3_P
DDR2-DQS3_N
J8
K8
VDDL
DDR2-BA0
DDR2-BA1
DDR2-BA2
3HKN
33R
B3
F3
K9
K2
K3
L8
K7
L7
A1
E1
J9
M9
R1
100n
100n
2HGT
100n
2HGS
100n
2HGR
100n
2HGP
100n
2HGN
100n
2HGM
100n
2HGK
100n
2HGJ
2HGH
22u
100n
2HGG
100n
2HGF
100n
2HGE
100n
2HGD
100n
2HGC
3HGP
3HGR
1u0
330u 6.3V
2HHP
RES 2HHN
EDE1116AEBG-8E
UDQS
100n
2HGB
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
SDRAM
0
1 BA
2
100n
2HGA
2HG9
RES
220R
NC
E
F
3HHB
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
3HHC
3HHE
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D29
DDR2-D27
DDR2-D31
33R
33R
33R 33R
3HHF
3HHG
33R
3HHJ
33R
3HHM
33R
3HHP
33R
3HHS
33R
3HHU
3HHD
33R
3HHH
33R
3HHK
33R
3HHN
33R
3HHR
33R
3HHT
33R
33R
B3
F3
G
DDR2-DQM3
DDR2-DQM2
J2
DDR2-VREF-DDR
2HH3
100n
H
VSSDL
3HKM
DDR2-CLK_P
DDR2-CLK_N
Φ
A2
E2
R3
R7
R8
DDR2-ODT
DDR2-CKE
DDR2-WE
DDR2-CS
DDR2-RAS
DDR2-CAS
J7
K
7HG1
VDDQ
A3
E3
J3
N1
P9
G
1u0
330u 6.3V
2HHM
RES 2HHK
J
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
VDDL
L2
L3
L1
ODT
CKE
WE
CS
RAS
CAS
VSSDL
DDR2-BA0
DDR2-BA1
DDR2-BA2
owner.
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
F
VDD
J7
I
K9
K2
K3
L8
K7
L7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
7HG0
DDR2-ODT
DDR2-CKE
DDR2-WE
DDR2-CS
DDR2-RAS
DDR2-CAS
A1
E1
J9
M9
R1
100n
100n
2HG8
100n
2HG7
100n
2HG6
100n
2HG5
100n
2HG4
100n
2HG3
100n
2HG2
100n
2HG1
E
2HG0
H
+1V8-PNX85XX
+1V8-PNX85XX
VSSQ
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
G
D
A
B
C
D
E
F
G
H
I
J
K
L
M
M
I
I
N
N
1
2
3
4
5
6
7
9
8
10
11
13
12
14
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
DDR2 INTERFACE
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
16
2007-11-29
130
C
17
7
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_509_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 95
SSB: PNX8543 - Digital Video In
1
2
3
5
4
1
A
6
2
8
7
3
10
9
4
6
5
12
11
3HK0 B2
7H00-4 A3
9HK0 D2
IHSM B2
TH01 C2
TH02 C2
TH03 C2
TH04 C2
TH05 C2
TH06 C2
TH07 D2
TH08 D2
TH09 B2
TH10 B2
TH11 B2
TH12 B2
TH13 B2
TH14 C2
TH15 C2
TH16 C2
7
PNX 8543 : DIGITAL VIDEO IN
B
A
A
7H00-4
PNX85439EH/M2/24182
B
C18
E19
DDC-SCL
DDC-SDA
RREF-PNX85XX
C15
D15
HDMIA-RX0HDMIA-RX0+
D
C
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
DDCA-SCL
DDCA-SDA
E
TH09
IHSM
3HK0
12K
TH11
HDMIA-RX2HDMIA-RX2+
TH13
HDMIA-RXCHDMIA-RXC+
TH15
HDMIB-RX0HDMIB-RX0+
TH01
HDMIB-RX1HDMIB-RX1+
TH03
HDMIB-RX2HDMIB-RX2+
TH05
HDMIB-RXCHDMIB-RXC+
TH07
HDMI_DV
DDC_SCL_A
DDC_SDA_A
DDC_SCL_B
DDC_SDA_B
HDMI_RREF
B18
P
HDMI_RX0_A
B17
N
TH10
HDMIA-RX1HDMIA-RX1+
C16
DV
0
1
2
3
4
P
HDMI_RX2_A DV_UVIN
N
5
6
P HDMI_RXC_A
7
N
8
9
P HDMI_RX0_B
N
DV_VALID
DV_VS
P
HDMI_RX1_B
0
N
1
P
2
HDMI_RX2_B
N
3
4
DV_YIN
P
5
HDMI_RXC_B
N
6
7
HOT_PLUG_A
8
HOT_PLUG_B
9
A17
P
HDMI_RX1_A
A16
N
TH12
TH14
B16
B15
TH16
A19
A18
TH02
B14
B13
TH04
A13
A12
TH06
B12
B11
TH08
A15
A14
9HK0
HOT-PLUG-A
HOT-PLUG
D19
E15
CLK
FID
HS
B8
C9
D9
A
B
C
B
B6
A6
E7
D7
C7
B7
A7
E8
D8
C8
D
A8
E9
C
B4
A4
E5
D5
C5
B5
A5
E6
D6
C6
E
D
D
F
13
F
G
G
E
E
H
H
1
2
3
4
5
7
6
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
VIDEO IN
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8927
PNX8543 TV543 R2 LDIPNX
8
SUPERS.
DATE
9
16
2007-11-29
130
C
10
8
A3
ROYAL PHILIPS ELECTRONICS N.V. 2005
11
12
13
18310_510_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 96
SSB: PNX8543 - Audio
3
2
1
5
4
7
6
10
9
8
13
12
11
14
16
15
18
17
20
19
A
A
1
2
4
3
5
6
8
7
9
10
12
11
13
B
PNX 8543 : AUDIO
A
A
AUDIO-VDD
2HMJ
C
FHR3
100n
IHMW
3
ADAC(7)
IHMV
4
7HM1-1
LM324 1
FHM0
AUDIO-CL-L
2
9HM0
11
B
B
22K
3HM0-2
7
AUDIO-VDD
2
1
2
IHM0
6HM0
4R7
2HMG
IHM6
BZX384-C6V8
+AUDIO-POWER
1u0
D
7HM5
BC807-25W
2
3
3HMF
3HME-2
7
8
3HME-1
10K
1
10K
2HMP
IHM8
C
22K
8 3HM0-1 1
33p
E
C
IHM7
6
IHM2
3HM0-3
22K
3
AUDIO-VDD
7HM6
BC847BW
IHM4
F
IHM5
IHN3
5
4
IHN6
7HM1-2
LM324 7
FHM1
AUDIO-CL-R
6
22K
10K
3HM1
D
5 3HM0-4 4
ADAC(8)
D
11
G
3 3HME-3 6
5 3HME-4 4
10K
10K
2HMT
33p
E
H
E
AUDIO-VDD
AUDIO-VDD
I
4
IHN8
7HM1-3
LM324 8
IHNA
FHM2
AUDIO-OUT-L
9
3
3n3
1
10
ADAC(5)
2HN1
F
2K2
3HMY
IHNB
2
BC857BW
7HM3
F
11
IHN0
2
7HM2-1
BC847BS(COL)
1
IHNG
22K
2HM1
J
3HMA
100n
2HM4
3n3
2HM3
1u0
IHM1
3HML
+AUDIO-L
3
2K2
470R
ADAC(1)
3HMZ
3HMM-3
5
6
3HMM-4
4
10K
2HMW
10K
33p
G
G
B
C
D
E
F
G
H
I
J
K
AUDIO-VDD
3HMW
AUDIO-VDD
2K2
K
22K
3HMC
IHNJ
owner.
1
2
BC857BW
7HM4
IHNF
3
3
5
7HM2-2
BC847BS(COL)
4 IHNH
22K
2HM2
M
3HMB
100n
2HM5
1u0
3n3
IHND
12
ADAC(6)
IHN4
3HMU
IHMG
-AUDIO-R
FHM3
L
H
AUDIO-OUT-R
11
2K2
2
3HMM-2
10K
22K
3HMD
7HM1-4
LM324 14
13
IHNK
I
4
IHNE
3n3
ADAC(2)
3HMV
470R
H
IH23
2HMY
L
2HM8
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
6
IH22
2HM1 G5
2HM2 H5
2HM3 G4
2HM4 G5
2HM5 H5
2HM8 H4
2HMG B3
2HMJ A10
2HMP C10
2HMT E10
2HMW G10
2HMY H9
2HMZ I10
2HN1 F9
3HM0-1 C5
3HM0-2 B4
3HM0-3 C4
3HM0-4 D5
3HM1 D4
3HMA G6
3HMB H6
3HMC G5
3HMD I5
3HME-1 B10
3HME-2 B9
3HME-3 E9
3HME-4 E10
3HMF B3
3HML G6
3HMM-1 I10
3HMM-2 I9
3HMM-3 G9
3HMM-4 G10
3HMU H6
3HMV H5
3HMW H5
3HMY F5
3HMZ F5
6HM0 B4
7HM1-1 B10
7HM1-2 D10
7HM1-3 F10
7HM1-4 H10
7HM2-1 F5
7HM2-2 H5
7HM3 F7
7HM4 H7
7HM5 B5
7HM6 C5
9HM0 B5
FHM0 B11
FHM1 D11
FHM2 F11
FHM3 H11
FHR3 A10
IH22 F4
IH23 H4
IHM0 B3
IHM1 F7
IHM2 C4
IHM4 C4
IHM5 D5
IHM6 B3
IHM7 C5
IHM8 C5
IHMG H7
IHMV B9
IHMW B9
IHN0 F5
IHN3 D9
IHN4 H5
IHN6 D10
IHN8 F6
IHNA F10
IHNB F9
IHND H9
IHNE H10
IHNF H6
IHNG F6
IHNH H6
IHNJ G5
IHNK I5
7
8
3HMM-1
M
1
10K
2HMZ
I
33p
N
N
1
3
2
4
5
7
6
8
9
11
10
12
13
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
AUDIO
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
16
2007-11-29
130
C
17
9
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_511_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 97
SSB: PNX8543 - Analogue AV
2
1
3
4
A
8
7
6
9
6
5
7
13
12
11
10
8
9
14
10
3H95
5H80
2H80
3HRS
100p
2HTR
5HR2
3HRU
330n
27R
100p
IHSS
AV1-Y
IHR0
56R
2HS2
5HR0
3HRR
330n
27R
IHST
AV1-PB
5HRG
IHRC
22n
100p
2HTV
100p
C
100p
2HSM
3HS2
56R
2HSK
100p
56R
100p
100p
56R
2HSD
3HRY
100p
3H93
2H98
100p
2H97
3HS0
47R
2H99
9H54
9H55
2HT8
2HT5
IHSC
22n
22n
2HA5
IHR6
3HS9
FRONT-Y_CVBS
27R
22n
IHS5
IHRF
2HSP
2HS0
22n
IHRB
2HSV
RES
5HRL
IHRE
2HSN
22n
3HSR
R-VGA
3H40
18R
120n
18R
2HTB
IH46
5HR9
3HSB
120n
18R
22n
22n
2HSY
G-VGA
3H47
22n
IHSH
IHV3
2HTE
22n
22n
2HUP
22n
22n
IHV6 2HST
G
18R
2HUN
2HTK
F
FRONT-C
27R
18R
F1
F2
F3
F4
G1
G2
3HST
22n
3H34
22n
47R
2HU8
22n
2HT6
IHSD
22n
IHR8
5HRA
3HSE
120n
18R
100p
GND_A3_TG
2HA4
22n
G3
G4
H1
H2
H3
H4
D2
D1
E1
E2
2HT7
22n
2HTG
J5
AI1N_IF
AI1P_IF
AI2P_IF
AI2N_IF
E
IHS4
2HU5
22n
100p
G
22n
56R
2HTF
J
AV2-Y_CVBS
27R
IHRD
2HSB
9H53
3HRZ
3HSD
AI5N
AI51
AI52
AI53
AI54
REF 5
9H52
22n
IHR4
3HSV
AI4N
AI41
AI42
AI43
AI44
REF 4
22n
2HT1
22n
100p
F
22n
2HA3
M1
M3
M4
M5
L1
L2
L3
L4
K1
K3
K4
K5
J1
J2
J3
J4
D
9H51
2HSF
2HTH
IHSA
AV3-PB
27R
AV3-Y
2HTD
PC3_AI1
PC3_AI2
PC3_AI3
PC3_AID
AI31
AI32
AI33
REF 3
27R
100p
P
CVBS2C
N
3HS1
330n
330n
47R
P
CVBS1Y
N
5HR5
56R
2HTC
IHS3
IHSE
A2
B2
22n
9H50
P1
P3
P4
P5
N1
N2
N3
N4
IHR5
2HSJ
R1
R3
3HSA
2HKL
270p
A3
B3
IHSB
22n
22n
100p
H
3HS6
75R
3HSW
75R
PC2_AI1
PC2_AI2
PC2_AI3
PC2_AID
AI21
AI22
AI23
REF 2
2H96
2HU0
2HUK
270p
3HS7
75R
AGC
IH87
3HRW
47R
E
BIAS DAC
330n
100p
C3
C2
4K7
5H87
3HSQ
10K
IHSG
4K7
3HT9
18R
18R
3HS8
3HS5
CURREF
3H91
AV5-Y
56R
2HTZ
G
A1
PC1_AI1
PC1_AI2
PC1_AI3
PC1_AID
AI11
AI12
AI13
REF 1
HSYNCIN
IN
VSYN
OUT
AV5-Y
5HR3
IHR3
2HSE
2HSC
3HSU
3HSK
T2
U1
IH43
2H86
10n
SYNC_IN_1
SYNC_IN_2
2HSW IHVE
22n
B-VGA
K
IHS6
22n
3HT4
CVBS4
H
27R
2HUC
L
100p
3HS3
2HSR
IF-N
100n
12p
2HSU
820R
M
3HT3
2HUB
H
47R
owner.
All rights reserved. Reproduction in whole or in parts
10n
ANALOG_VIDEO
D
T1
is prohibited without the written consent of the copyright
27R
AV4-Y
7H00-1
PNX85439EH/M2/24182
I
AV3-PR
22n
3H29
F
56R
2HTU
3HSN
2H93
56R
330n
100p
3H90
18R
IH45
2H95
5H86
2H94
E
3H89 18R
3HSM
330n
3H99
IH42
AV5-PB
A
AV1-PR
2HSA
C
AV1-Y_CVBS
27R
IHSR
56R
2H92
100p
3H88
22n
100p
2H91
330n
22n
3HRP
18R
13
B
2H90
IH85
100p
3HSJ
56R
2HS8
22n
2HS1
5H85
3H85 18R
D
FHR1
3HRV
22n
3H98
IH41
AV5-PR
27R
100p
H-SYNC-VGA
V-SYNC-VGA
2H84
56R
330n
100p
3H84
18R
IH81
2H85
5H82
100p
FHR5
FHR6
3H83
2H89
C
56R
2HTP
22n
2HS7
18R
3HSH
330n
2HS3
56R
2H83
100p
3H82
330n
2H82
IH44
5HRC
22n
3H97
IH40
AV4-Y
B
18R
100p
Y_CVBS-MON-OUT
270p
3HSF
75R
2HTL
IHS2
3H81
5H81
2H88
18R
AV4-PB
IHPF
2HRZ
3H96
IH39
2HS9
A
B
IHR1
19
56R
22n
100p
3H80
100p
2H87
330n
22n
100p
18R
IH80
100p
3H79
18
17
12
11
2HS4
18R
AV4-PR
2H81
IH38
PNX 8543 : ANALOGUE AV
16
15
100p
5
47R
4
3
3HRT
2
1
3HS4
820R
2HSS
IF-P
100n
I
I
N
1
2
4
3
5
7
6
8
10
9
11
12
20
2H80 A6
2H81 A5
2H82 A5
2H83 A5
2H84 B6
2H85 B5
2H86 D3
2H87 A5
2H88 A4
2H89 B4
2H90 B5
2H91 C4
2H92 C5
2H93 C5
2H94 C4
2H95 C4
2H96 D5
2H97 D4
2H98 D4
2H99 D3
2HA3 E3
2HA4 E3
2HA5 F5
2HKL E1
2HRZ A8
2HS0 G4
2HS1 B8
2HS2 B8
2HS3 B9
2HS4 A10
2HS7 B8
2HS8 B8
2HS9 B9
2HSA C10
2HSB E8
2HSC C10
2HSD D10
2HSE D11
2HSF D10
2HSJ D8
2HSK D8
2HSM D9
2HSN G8
2HSP F10
2HSR H10
2HSS I10
2HST G3
2HSU I9
2HSV G4
2HSW D1
2HSY G3
2HT1 E5
2HT5 F3
2HT6 F3
2HT7 E5
2HT8 F8
2HTB G9
2HTC G10
2HTD G10
2HTE G10
2HTF G11
2HTG G11
2HTH D3
2HTK G3
2HTL B2
2HTP A8
2HTR A9
2HTU C10
2HTV C11
2HTZ G8
2HU0 G9
2HU5 E3
2HU8 F3
2HUB H11
2HUC H9
2HUK E1
2HUN G4
2HUP G4
3H29 C4
3H34 F9
3H40 G10
3H47 G11
3H79 A4
3H80 A5
3H81 A4
3H82 A5
3H83 B4
3H84 B5
3H85 B4
3H88 C5
3H89 C4
3H90 C5
3H91 D4
3H93 D5
3H95 A4
3H96 A4
3H97 B4
3H98 B4
3H99 C4
3HRP B8
3HRR B9
3HRS A12
3HRT A10
3HRU B9
3HRV B8
3HRW C12
3HRY D10
3HRZ D12
3HS0 E10
3HS1 D9
3HS2 D8
3HS3 H9
3HS4 I9
3HS5 E1
3HS6 E1
3HS7 E1
3HS8 F8
3HS9 F12
3HSA G9
3HSB G10
3HSD G10
3HSE G11
3HSF B2
3HSH A9
3HSJ A8
3HSK E1
3HSM C12
3HSN C10
3HSQ E8
3HSR G10
3HST F12
3HSU G8
3HSV F10
3HSW E1
3HT3 H11
3HT4 H11
3HT9 E1
5H80 A5
5H81 A5
5H82 B5
5H85 B4
5H86 C4
5H87 D4
5HR0 B9
5HR2 B9
5HR3 C11
5HR5 D9
5HR9 G10
5HRA G11
5HRC A9
5HRG C11
5HRL F9
7H00-1 D2
9H50 D4
9H51 D5
9H52 E4
9H53 E5
9H54 E4
9H55 E5
FHR1 B8
FHR5 B2
FHR6 B2
IH38 A4
IH39 A4
IH40 B4
IH41 B4
IH42 C4
IH43 D4
IH44 A5
IH45 C5
IH46 G10
IH80 A5
IH81 B5
IH85 B5
IH87 D5
IHPF A8
IHR0 B8
IHR1 A10
IHR3 C11
IHR4 D10
IHR5 D8
IHR6 F9
IHR8 G11
IHRB F4
IHRC C10
IHRD E8
IHRE F8
IHRF F10
IHS2 A2
IHS3 E1
IHS4 E3
IHS5 F4
IHS6 H11
IHSA E3
IHSB E1
IHSC F3
IHSD F3
IHSE E1
IHSG E1
IHSH G3
IHSR A12
IHSS B12
IHST B12
IHV3 G3
IHV6 G3
IHVE D1
A
B
C
D
E
F
G
H
I
J
K
L
M
N
13
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
ANALOG AV
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
16
2007-11-29
130
C
17
11
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_512_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 98
SSB: PNX8543 - Audio
1
2
3
1
A
4
5
2
6
3
7
8
5
4
10
9
6
7
13
12
11
9
8
14
15
10
16
17
12
11
PNX 8543 : AUDIO
B
A
A
C
B
B
D
VDDA-AUDIO
VDDA-DAC
7HP0
LD2985BM33R
3HR8-4
4
AUDIO-IN3-L
3
RES
6
33K
4
2HRB
AUDIO-IN5-L
AUDIO-IN5-R
33K
RES
6
33K
RES
2HRE
33p
2HRF
5
AK6
L
AIN_2
AL6
R
1u0
5
2HRC
RES
33p
1u0
AM11
AL11
ADAC4 N
AK11
P
AP6
L
AIN_4
AM5
R
2HRH
1u0
2HRK
3H62
VDDA-AUDIO
U5
1
SPDIF_IN
C19
2
47K
1u0
SPDIF-IN1
47K
AN15
OSCLK
I2S_IN
AL14
SCK
AK14
SD1
AP15
SD2
I2S_IN
AM15
SD3
AL15
SD4
AM14
B1
G
AM7
IHRK
IHRL
C1
D3
AP10
AN10
ADAC6 N
AM10
P
ADAC7BUF
ADAC8BUF
7
8
ADAC
SPDIF_OUT
I2S_IN_WS
I2S_OUT
RESREF
VCOM_ADC
AOUT
AGND1
OSCLK
SCK
10u
2HPA
IHSY
2
2HP4
10u
2HPB
100n
ADAC(2)
3HP5-1
33R
I2S_OUT_SD
22K
E
ADAC(3)
3HP5-2
33R
ADAC(4)
3HP5-3
33R
ADAC(5)
3HP5-4
33R
ADAC(6)
F
3HP0
RES
AL9
AL8
AA2
Y2
ADAC(8)
ADAC(7)
3HT8-4
33R
AP9
AN9
V1
ADAC(1)
RES
33R
3HT8-2
3HP1
33R
ADAC(7)
ADAC(8)
ADAC(7)
ADAC(8)
33R
3HPN
IHPD
3HT8-1
33R
SPDIF-OUT
68R
Y3
1
AA1
2
AA3
3
AA4
4
I2S_OUT_WS
G
Y1
3HRK
75R
10u
100n
2HRY
2HRW
4K7
3HRN
K
4K7
IHRM
3HT8-3
33R
AN11
AP11
ADAC5 N
AL10
P
AN5
L
AIN_5
AP5
R
J
L
D
AM12
AN12
ADAC3 N
AP12
P
AM6
L
AIN_3
AN6
R
2HRD
3HRM
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
owner.
10u
2HR9
33p
3H63
F
AUDIO
AK7
L
VREF_AADC
AK9
AL7
VDDA_3V3_DAC
R
AJ10
VSSA_ADAC
AM8
NEG
AN14
VREF
AM9
POS
AP14
ADAC1 N
AL13
AP8
VRNEG
P
AADC
AN8
AADC
AP13
AN13
AN7
L
ADAC2 N
AIN_1
AM13
AP7
R
P
1u0
2
7
1 3HRC-1
33K
IHRW
8
33K
2
2HRG
3HRJ-2
7
1 3HRJ-1
33K
RES 33p
IHRU
8
33K
3HRJ-3
2HRJ
6
3
4 3HRJ-4
RES 33p
33K
IHRT
AUDIO-IN4-R
VDDA-AUDIO
1u0
3HRC-2
H
I
33K
5HRW 30R IHSZ
2HR5
33p
2HR8
3HR8-2
2
7
33K
IHRZ
22K
VDDA-AUDIO
2HRA
33p
RES
7H00-7
PNX85439EH/M2/24182
IHSV
5HRZ 30R
1u0
3
3HRC-3
IHRV
3HRC-4
AUDIO-IN4-L
3HAG
2HR4
33K
E
COM
2HR7
5
1 3HR8-18
AUDIO-IN3-R
3
+3V3
2HR6
33p
1u0
3HR8-3
IHRY
33K
INH
C
+5V
1
3HAH
RES
33K
G
BP
IN
3n3
6
33K
2 3HR3-2 7
1 3HR3-1 8 IHS1
33K
AUDIO-IN2-R
4
OUT
3n3
2HRT
3
3HR3-3
IHS0
33K
D
IH11
2HRS
5
100n
4
2HRN
3HR3-4
AUDIO-IN2-L
5
1u0
33K
F
100n
2HP5
2HR1
33p
100n
2HP7
RES
100n
2HRP
1u0
2HR0
33K
IH13
FHPE
30R
2HP8
4 IHRJ
RES
2HR3
100n
2HRV
5
3HR0-4
AUDIO-IN1-R
2HR2
33p
2HRU
AUDIO-IN1-L
5HP2
IHSU
3HR0-2 2
7
3HR0-1 1 IHRH
33K
9H11
33K
3HR0-3 6
3
100n
8
IHSW
10n
9H12
100n
2HP6
C
2HRM
E
H
H
M
I
18
19
20
2HP4 D10
2HP5 D9
2HP6 D9
2HP7 D9
2HP8 D9
2HPA C11
2HPB D10
2HR0 C4
2HR1 D5
2HR2 C4
2HR3 C5
2HR4 D4
2HR5 D4
2HR6 D4
2HR7 D4
2HR8 E4
2HR9 E4
2HRA D4
2HRB D4
2HRC E4
2HRD E4
2HRE E4
2HRF E4
2HRG E3
2HRH F4
2HRJ F3
2HRK F4
2HRM D6
2HRN D6
2HRP C6
2HRS E11
2HRT E11
2HRU C6
2HRV C6
2HRW G6
2HRY G6
3H62 F6
3H63 F6
3HAG D11
3HAH D11
3HP0 F9
3HP1 F10
3HP5-1 E10
3HP5-2 E9
3HP5-3 F10
3HP5-4 F9
3HPN G9
3HR0-1 C3
3HR0-2 C4
3HR0-3 C3
3HR0-4 D3
3HR3-1 D3
3HR3-2 D4
3HR3-3 D3
3HR3-4 D3
3HR8-1 E3
3HR8-2 E3
3HR8-3 D3
3HR8-4 D3
3HRC-1 E3
3HRC-2 E3
3HRC-3 E3
3HRC-4 E2
3HRJ-1 F2
3HRJ-2 E3
3HRJ-3 F3
3HRJ-4 F2
3HRK H6
3HRM G5
3HRN G5
3HT8-1 F9
3HT8-2 F9
3HT8-3 D10
3HT8-4 E9
5HP2 C10
5HRW D6
5HRZ D6
7H00-7 D7
7HP0 C10
9H11 C4
9H12 C4
FHPE C10
IH11 C10
IH13 C11
IHPD F9
IHRH C4
IHRJ D4
IHRK G5
IHRL G6
IHRM G6
IHRT F3
IHRU F3
IHRV E3
IHRW E3
IHRY D3
IHRZ E3
IHS0 D3
IHS1 D3
IHSU C6
IHSV D6
IHSW C9
IHSY D11
IHSZ D6
A
B
C
D
E
F
G
H
I
J
K
L
M
I
N
N
1
2
3
4
5
6
7
8
9
10
11
12
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
AUDIO
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
16
SUPERS.
DATE
16
2007-11-29
130
C
17
A3
12
ROYAL PHILIPS ELECTRONICS N.V. 2006
18
19
20
18310_513_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 99
SSB: PNX8543 - Audio
2
1
3
A
4
1
6
5
2
3
8
7
4
5
9
11
10
7
6
12
AUDIO-VDD
A
A
6
1 IH51
2HVA
2H04
33p
1 3H18-1 8
100R
2HYC
470R
3H77
FHV4
3H75
1u0
22K
4
1HV9
3
FH50
100R
470R
+AUDIO-POWER
FHV5
7HV0
TPA6111A2DGN
IH48
ADAC(4)
IH24
100n 2HVE
3H18-3
3
22K 3H18-2
7
2
IH25
Φ
IHWL
2
IHWE
6
22K
5
2H02
3n3
IH27
3
1
F
D
C
VDD
AMPLIFIER
1
IHWJ
AUDIO-HDPH-L-AP
IHV1
AUDIO-HDPH-R-AP
IH31
VO
2
SHUTDOWN
BYPASS
7
2
VIA
GND GND_HS
1u0
1
IN-
4
3n3
2H26
2H25
100n
6
IHW7
8
10
11
3HV4-1
22K
3HV3
RESET-AUDIO
2 3HV4-2 7
ADAC(3)
2HVD
10K
IH47
22K
C
E
3H35
3H94
1u0
+3V3
1735446-3
8
IH54
3H76
2HVC
IH55
2H05
4
100n
5K6
B
33p
1
2
3
7H01-2
BC847BS(COL)
5
2HYD
D
IH53
5
22K
2HVB
B
3H74
3H18-4
100n
AUDIO-VDD
1
IHVA
5
4
BC847BPN(COL)
7HVA-2
D
A-PLOP
3
10K
IH29
A-STBY
6
IHW8
2
22K
E
7HVA-1
BC847BPN(COL)
1
1n0
RESET-AUDIO
FHV3
3HV4-4
4
5
22K
2HVG
G
3 3HV4-3 6
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
IH52
9
2
5K6
100p
3H71
7H01-1
BC847BS(COL)
A
1HV9 B3
2H02 D4
2H04 A2
2H05 B2
2H25 D1
2H26 D1
2HVA A5
2HVB B5
2HVC C5
2HVD C1
2HVE C2
2HVG E6
2HYC B3
2HYD C3
3H18-1 B5
3H18-2 C2
3H18-3 C2
3H18-4 B5
3H35 C7
3H71 A1
3H74 B1
3H75 A3
3H76 B2
3H77 B2
3H94 C2
3HV3 D2
3HV4-1 D7
3HV4-2 C8
3HV4-3 E6
3HV4-4 E6
7H01-1 A2
7H01-2 B2
7HV0 C4
7HVA-1 E7
7HVA-2 D8
FH50 B3
FHV3 E6
FHV4 A3
FHV5 C3
IH24 C2
IH25 C2
IH27 D4
IH29 D8
IH31 C8
IH47 C1
IH48 C1
IH51 A2
IH52 A2
IH53 B1
IH54 C2
IH55 B2
IHV1 C5
IHVA D8
IHW7 D7
IHW8 E7
IHWE C2
IHWJ C5
IHWL C2
8
PNX 8543 : AUDIO
B
13
E
B
C
D
E
F
G
H
H
1
2
3
4
5
6
7
8
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
AUDIO
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8927
PNX8543 TV543 R2 LDIPNX
8
16
SUPERS.
DATE
9
2007-11-29
130
C
10
13
A3
ROYAL PHILIPS ELECTRONICS N.V. 2005
11
12
13
18310_514_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 100
SSB: PNX8543 - Video Streams
1
2
3
4
5
6
7
8
11
10
9
12
13
14
16
15
17
18
20
19
A
A
1
B
2
3
4
5
6
7
8
9
10
2H08 D3
2H09 F3
3H73 F2
3HB1 C2
3HB2 C2
3HB3 C2
3HB4 D2
3HB5 D2
3HB6 F2
3HB7 F4
3HWK D5
3HWN-1 B11
3HWN-2 B11
3HWP C10
3HWR-1 B11
3HWR-2 B11
3HWR-3 C10
3HWR-4 B10
3HWV-1 B10
3HWV-2 C10
3HWV-3 C10
3HWV-4 B10
7H00-12 B9
7H04 D3
7H05 F3
9H06-1 B2
9H06-2 B2
9H06-3 B2
9H06-4 B2
9H07-1 B2
9H07-2 B2
9H07-3 B2
9H07-4 B2
9H08-1 C2
9H08-2 C2
9H08-3 C2
9H08-4 B2
9HW0 D6
9HW1 D10
9HW2 C8
IH50 F2
IHW0 D6
11
PNX 8543 : VIDEO STREAMS
C
A
A
D
FE-ERR
4
9H06-4
5
TSO-BIT-ERR
FE-CLK
FE-VALID
FE-SOP
FE-DATA0
FE-DATA1
FE-DATA2
FE-DATA3
FE-DATA4
FE-DATA5
FE-DATA6
FE-DATA7
3
2
1
4
3
2
1
4
3
2
1
9H06-3
9H06-2
9H06-1
9H07-4
9H07-3
9H07-2
9H07-1
9H08-4
9H08-3
9H08-2
9H08-1
6
7
8
5
6
7
8
5
6
7
8
TSO-BIT-CLK
TSO-BIT-VALID
TSO-SYNC
TSINO-DATA0
TSINO-DATA1
TSINO-DATA2
TSINO-DATA3
TSINO-DATA4
TSINO-DATA5
TSINO-DATA6
TSINO-DATA7
7H00-12
PNX85439EH/M2/24182
B
E
3HB1
SCL-BOLT-ON
SDA-BOLT-ON
F
C
100R
3HB3
BOLT-ON-IO
I2C-SCL
I2C-SDA
3HB2
100R
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
E33
C32
B32
J30
K34
K33
H30
J33
CA-MOSTRT
E34
CA-MOVAL
D34
9HW2
CA-MOCLK_VS2
H31
RESET-BOLT-ON
TUN_CA
G33
2
G31
1
83HWV-1
G30
47R 2
H34 3HWR-4
4
5 47R
F34
47R
1
F32 3HWV-4 4
5
F31
47R
1
G34 3HWR-3
3
6 47R
47R
J31
2
7 3HWV-2
CA_MISTRT
47R
3HWV-3 3
E32
CA_MIVAL
0
1
2
3
CA_MDO
4
5
6
7
0
1
2
3
CA_MDI
4
5
6
7
CA_MOSTRT
CA_MOVAL
CA_MOCLK
100R
CA_MICLK
CA_ADD_EN
D10
E10
A9
A11
C11
D11
E11
A10
FE-DATA0
FE-DATA1
FE-DATA2
FE-DATA3
FE-DATA4
FE-DATA5
FE-DATA6
FE-DATA7
G
0
1
2
3
TNR_TSDI
4
5
6
7
+3V3
+3V3
7H04
74LVC245A
1
10K
E
2
FE-DATA6
FE-DATA5
FE-DATA4
FE-DATA3
FE-DATA2
FE-DATA1
FE-DATA0
3
4
5
6
7
8
9
C12
FE-CLK
B10
FE-SOP
B9
FE-VALID
C10
4K7
3EN1
3EN2
G3
1
2
18
TSINO-DATA7
17
16
15
14
13
12
11
TSINO-DATA6
TSINO-DATA5
TSINO-DATA4
TSINO-DATA3
TSINO-DATA2
TSINO-DATA1
TSINO-DATA0
3HWP
33R
CA-MIVAL
CA-MICLK
B31
CA-CD1
CA-CD2
CA-DATADIR
CA-DATAEN
CA_RST
TNR_ERROR
TNR_MICLK
CA_VCCEN
TNR_MISTRT
CA_VPPEN
C
CA-ADDEN
D
E
F
G
C31
J34
IRQ-CA
C34
CA-RST
D
C33
TNR_MIVAL
CA_VSN
A33
J32
0
A34
1
H
CA-VS1
CA-MOCLK_VS2
9HW1
E
I
IH50
J
J
+3V3
+3V3
2H09
19
BOLT-ON-TS-ENn
K
3HB6
3
4
5
6
7
8
9
FE-SOP
FE-VALID
FE-CLK
FE-ERR
G
3EN1
3EN2
G3
2
10K
18
1
2
17
16
15
14
13
12
11
K
3HB7
10K
TSO-SYNC
TSO-BIT-VALID
TSO-BIT-CLK
TSO-BIT-ERR
G
L
10
L
F
100n
20
7H05
74LVC245A
1
10K
3H73
F
owner.
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
10
I
19
FE-DATA7
FE-ERR
9HW0
3HB5
FE-ERR
CA-MISTRT
6
47R
D31
DIR
A31
CA_DATA
EN
CA_OOB_EN
B
C
IHW0
3HWK
+3V3-PER
100n
20
H
10K
3HB4
2H08
8 3HWR-1
47R
8
3HWN-1
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
K32
0
A32
1
CA_CDN
CA_RDY
D
H32
7 3HWR-2
47R
7 3HWN-2
B
M
M
1
2
3
4
5
6
8
7
9
10
11
N
N
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
CONDITIONAL ACCESS
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
16
2008-06-05
130
C
17
14
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_515_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 101
SSB: PNX8543 - Digital Video Out/LVDS
1
2
3
1
A
4
3
2
6
5
4
8
7
5
10
9
6
7
11
12
13
3HP9 A7
7H00-11 B2
7H00-5 A6
IHPG A7
9
8
A
PNX8543 : DIGITAL VIDEO OUT / LVDS
A
A
B
B
7H00-5
PNX85439EH/M2/24182
LVDS
IHPG
7H00-11
PNX85439EH/M2/24182
NC
Y4
R2
C4
R4
T4
W4
R5
W5
F11
NC
F12
F13
F14
F15
C14
AJ11
AL12
AK15
C B
D
C
NC
3HP9
AK19
VDDA-LVDS
12K 1%
AN18
N
A
AP18
P
AK28
AL28
AM28
AK29
AL29
AM29
AN29
K29
L29
NC
M29
N29
P29
R29
T29
U29
V29
E
TX851ATX851A+
B
N
P
AK18
AL18
TX851BTX851B+
C
AN19
N
AP19
P
TX851CTX851C+
D
AN20
N
AP20
P
TX851DTX851D+
E
AL20
N
AM20
P
TX851ETX851E+
CLK
AL19
N
AM19
P
TX851CLKTX851CLK+
AN22
N
AP22
P
TX852ATX852A+
AK22
N
LOUT2_B
AL22
P
TX852BTX852B+
LOUT2_C
AN23
N
AP23
P
TX852CTX852C+
LOUT2_D
AN24
N
AP24
P
TX852DTX852D+
LOUT2_E
AL24
N
AM24
P
TX852ETX852E+
LOUT2_CLK
AL23
N
AM23
P
TX852CLKTX852CLK+
LOUT2_A
NC
AL17
AN21
AP21
AL25
AM25
AN25
AP25
AK26
AL26
AM26
AN26
AP26
AM27
AN27
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
W29
Y29
AA29
AB29
AC29
AD29
AE29
AF29
AG29
AM30
AN30
AP30
AN31
AP31
AP32
M30
K31
IREF_LVDS
D
C
B
D
C
E
D
F
G
F
E
E
G
H
H
F
F
I
1
2
4
3
5
6
7
CHN
8
I
9
SETNAME
2
CLASS_NO
2008-11-21
LVDS
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8927
PNX8543 TV543 R2 LDIPNX
8
SUPERS.
DATE
9
130
16
2007-11-29
C
10
A3
15
ROYAL PHILIPS ELECTRONICS N.V. 2005
11
12
13
18310_516_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 102
SSB: PNX8543 - Power
1
A
4
3
2
1
2
5
3
8
7
6
4
5
10
9
6
7
12
11
8
14
13
9
10
16
15
11
17
12
PNX 8543 : POWER
IHY4
19
18
13
+3V3
A
100n
1u0
2HU2
100n
2H38
100n
2H37
100n
2H36
100n
2HVU
100n
2H35
100n
2H34
100n
2H33
100n
2HVV
100n
2H32
100n
2H31
100n
2H30
2HVW
30R
B
A
2HZK
2H22
100n
2H23
100n
2H21
100n
2HZL
100n
2H19
100n
2H20
100n
2H17
100n
2H18
100n
2H16
100n
2H15
100n
2HZM
100n
1u0
100n
2HUA
+1V2-PNX85XX
5HY6
IHSP
+1V2-PNX85XX
100n
2HVN
1u0
1u0
100n
2HY8
CH53
7H00-10
PNX85439EH/M2/24182
2HVY
330u 6.3V
SENSE+1V2-PNX85XX
2HVZ
330u 6.3V
+1V8-PNX85XX
5HY4
IHY1
VDDA-AUDIO
VDDA-DAC
2HZH
100n
30R
M
5HY7
IHY2
VDDA-ADC
VDDA-AUDIO
2HZV
30R
100n
VSS
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA5
AB31
AB4
AB5
AC31
AC33
AE6
AF33
AG31
AH29
VSS
AH6
AJ15
AJ24
AJ25
AJ29
AJ33
AJ5
AJ9
AK10
AK13
AK23
AK25
AL1
AL2
AL3
AL30
AM1
AM18
G
I
1u0
F
U6
V14
V15
V16
V17
V18
V19
V20
W14
W15
W16
W17
W18
W19
W20
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y33
Y5
Y6
IHYP
H
2HYB
100n
100n
2H24
1
8
100n
2HZD
100n
2HZC-1
2
7
4
3
100n
2HZC-3
6
100n
2HZB
100n
2HZE
100n
2HZF
1u0
2HZG
2HU6
1u0
2HU4
IHY3
100n
1u0
2HYF
30R
+1V2-PNX85XX
K
100n
2HVP
100n
1u0
2HVL
2HU3
2HY9
E
+1V8-PNX85XX
IHYM
5HV3
100n
2HY5
100n
100n
2H41
100n
2H40
2HY7
+1V2-PNX85XX
30R
100n
2HZC-2
IH10
100n
1u0
2HVJ
2HU7
5HG0
+1V2-PNX85XX
2HYE
100n
2HV9
1u0
2HV2
RREF-PNX85XX
owner.
VSS
VSS
L5
M2
N5
P14
P15
P16
P17
P18
P19
P2
P20
P21
P33
R14
R15
R16
R17
R18
R19
R20
T14
T15
T16
T17
T18
T19
T20
T31
U14
U15
U16
U17
U18
U19
U20
U33
G
H
I
VSS
N
AM2
AM21
AM22
AM31
AM32
AM33
AM34
AN1
AN32
AN33
AN34
AP33
AP34
B34
D12
D13
D17
D18
E12
E18
E3
E4
F21
F22
F27
F29
F30
F5
F7
F8
G29
G5
G6
H6
K2
L33
All rights reserved. Reproduction in whole or in parts
1u0
IHSK
30R
J
L
2HY6
Y30
AJ30
P30
AF30
AC30
AD30
AB30
AA30
W30
AK30
N30
AE30
2HH6
VDDA_3V3_DDRPLL0
VSSA_DDRPLL0
VDD_1V2_DDRPLL0
VSS_DDRPLL
0
1
VSSA_DLL
4
7
VDD_1V8_DDR
D
+3V3
30R
100n
VDDA_1V2_DLL
VDDA-ADC
VDDA-DAC
+3V3
F
is prohibited without the written consent of the copyright
IHYN
5HV8
I
100n
2H39
+1V2-PNX85XX
5HY5
IHSN
100n
VDDA_1V2_HDMI_EQ
VDD_3V3_HDMI_TERM_2
VDDA_HDMI_3V3_BIAS
VDDA_3V3_HDMI_PLL_2
VDD_1V2_HDMI_1
VDD_1V2_HDMI_2
VDDA_1V2_HDMI_EQ
VDD_3V3_HDMI_TERM_1
VDDA_3V3_HDMI_PLL_1
30R
30R
AJ7
VDDA_1V2_AADC
AJ6
VDDA_3V3_AADC
AK8
VDDA_3V3_ACT
AK12
VDDA_3V3_ADAC
100n
2H29
VDDA_1V2_VID
+1V2-PNX85XX
5HVB
IHK2
+3V3
30R
2HY4
100n
2HVR
AJ18
AK20
AK21
VDD_3V3_LVDS AK24
AL21
VDDA_3V3_LVDS AJ19
VSS_CL
5HY3
30R
VDDA_1V2_LVDS_PLL
C
5HVC
+3V3
IHY6
2HH9
100n
2HVH
VDDA_3V3_VID_1_1
VDDA_3V3_VID_1_2
VDDA_3V3_VID_4
VDDA_3V3_DCSCCO
VDDA_1V2_DCS_A
AJ26
VPP_ID_8542
F17
VPP_ID_8543
D4
VDDA_3V3_VIDOUT
K6
VDDA_1V2_ADC4A
IH05
+3V3
30R
AG30
AH30
R21
R30
T21
T30
U21
V21
W21
Y21
IHY7
1u0
100n
RES 9H18
RES 9H19
9H20
RES 9H21
+3V3-PER
+1V2-PNX85XX
+3V3-PER
+1V2-PNX85XX
RREF-PNX85XX
5HVA
IHY0
30R
JTAG_VSST1
100n
2H28
100n
2HV5
6.3V
2HV6
+1V2-PNX85XX
2HY2
100n
2HV7
100n
5HYB
1u0
IHYA
100n
2HY3
2HVF
5HV7
+3V3
E
D16
E17
F16
E16
C13
C17
D14
E13
E14
IHY8
5HV9
2H13
+3V3
30R
30R
FHK1
22u
30R
2H14
2HV8
100n
100n
30R
5HV5
IHYH
+1V2-PNX85XX
G
10u 35V
2H43
2H44
2R2
10u
3H55
5HV6
+1V2-PNX85XX
5HVD
IHK4
IHK3
AK17
VDDA_1V2_USB_PLL
AJ17
VDDA_3V3_USB
AJ16
GNDA_USB
VDD_3V3_SBPER
B
+3V3
30R
+1V2-PNX85XX
30R
AM3
100n
2H27
10u
100n
2H51
IHYC
RES
D
P6
R6
H5
T5
T3
L6
M6
N6
T6
5HVE
AA6
VDDA_1V2_CAB
AB6
VDDA_3V3_MCAB
VDD_1V2_SBCORE
5HVF
VDDA-LVDS
VDD
2HVM
2HV0
100n
2HV3
2H50
30R
AC6
AD6
1u0
+1V2-PNX85XX
IH61
F
10u
100n
30R
5HV4
100n
OUT
COM
2HV4
2H52
IN
68R
2H42
30R
1
+3V3
IH49
+3V3
3H57
3
5H50
2
4
IH60
5HV2
10u 6.3V
C
AF5
AF6
AG5
AG6
IHSL
5
7H06
LD1117
2HV1
IHYF
30R
IHK1
100n
2HVT
1u0
100n
2HVS
100n
2HZY-1
1
5HV1
+3V3
H
30R
+3V3
D
IHY9
+1V2-PNX85XX
30R
2HVK
8
7
6
3
2
2HZY-3
100n
2HZY-2
100n
5
4
1u0
100n
2HZY-4
100n
2HU9
2HU1
5HV0
30R
5HVG
IH28
AJ21
AJ22
AJ27
AJ28
AJ8
F10
F23
VDD_3V3_PER
F24
F28
F6
H29
J29
J6
W6
AJ12
AJ13
AJ14
AJ20
AJ23
F18
F19
F20
VDD_1V2_CORE
F25
F26
F9
K30
L30
U30
V30
V6
+3V3-STANDBY
100n
7H00-9
PNX85439EH/M2/24182
+1V2-STANDBY
B
E
+3V3
100n
2HZC-4
C
2HYA
30R
5HY2
IHY5
1
O
3
2
4
5
7
6
8
9
10
11
12
CHN
13
5HVB D11
5HVC C13
5HVD C13
5HVE B12
5HVF B13
5HVG B10
5HVH A12
5HY2 A12
5HY3 C11
5HY4 H3
5HY5 D12
5HY6 A13
5HY7 I3
5HYB E4
7H00-10 F6
7H00-9 A6
7H06 C2
9H18 E5
9H19 E5
9H20 E5
9H21 E5
CH53 F3
FHK1 D4
IH05 E5
IH10 E5
IH28 B10
IH49 C4
IH60 C2
IH61 D2
IHK1 B12
IHK2 D11
IHK3 C12
IHK4 C12
IHSK E11
IHSL B11
IHSN D11
IHSP A13
IHY0 E5
IHY1 H3
IHY2 I4
IHY3 F11
IHY4 A12
IHY5 A11
IHY6 C10
IHY7 E4
IHY8 D4
IHY9 B5
IHYA E2
IHYC D4
IHYF C3
IHYH D2
IHYM F5
IHYN F2
IHYP F3
2H13 E4
2H14 D2
2H15 A3
2H16 A3
2H17 A3
2H18 A3
2H19 A4
2H20 A4
2H21 A4
2H22 A4
2H23 A5
2H24 F11
2H27 D10
2H28 D11
2H29 D11
2H30 A9
2H31 A9
2H32 A10
2H33 A10
2H34 A10
2H35 A10
2H36 A11
2H37 A11
2H38 A11
2H39 C10
2H40 C11
2H41 C11
2H42 C2
2H43 D2
2H44 D2
2H50 C4
2H51 C4
2H52 C3
2HH6 E11
2HH9 E11
2HU1 B3
2HU2 A12
2HU3 C12
2HU4 F9
2HU6 F9
2HU7 F3
2HU9 B2
2HUA A2
2HV0 B4
2HV1 C3
2HV2 F2
2HV3 C4
2HV4 C3
2HV5 D4
2HV6 D4
2HV7 E2
2HV8 D2
2HV9 F2
2HVF E3
2HVH E5
2HVJ F4
2HVK D10
2HVL C12
2HVM C10
2HVN B11
2HVP B13
2HVR B10
2HVS B3
2HVT B4
2HVU A11
2HVV A10
2HVW A9
2HVY G3
2HVZ G3
2HY2 E2
2HY3 E3
2HY4 B11
2HY5 B12
2HY6 C10
2HY7 C11
2HY8 D11
2HY9 D12
2HYA A13
2HYB A13
2HYE F4
2HYF F5
2HZB F10
2HZC-1 F11
2HZC-2 F11
2HZC-3 F10
2HZC-4 F10
2HZD F11
2HZE F10
2HZF F9
2HZG F9
2HZH H4
2HZK A5
2HZL A4
2HZM A3
2HZV I4
2HZY-1 B3
2HZY-2 B2
2HZY-3 B2
2HZY-4 B2
3H55 D2
3H57 C2
5H50 C3
5HG0 E12
5HV0 B4
5HV1 C3
5HV2 C1
5HV3 F4
5HV4 C3
5HV5 D3
5HV6 D1
5HV7 E1
5HV8 F2
5HV9 E3
5HVA E3
14
5HVH
+3V3-PER
20
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
SETNAME
2
CLASS_NO
2008-11-21
POWER
P
8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
16
SUPERS.
DATE
16
2007-11-29
130
C
17
16
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_517_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 103
SSB: PNX5100 - SDRAM
2
1
4
3
5
77
6
9
8
10
11
12
13
16
15
14
18
17
20
19
A
A
2
1
B
5
4
3
6
3C10
3K3 RES
IC04
5K6 1%
PNX5100-DDR2-VREF-CTRL
IREF
VREF
2C01
P26
P25
100n
P
N
CLK
RES
3C02
DQM
DQS0
P
N
DQS1
P
N
100R
G
PNX5100-DDR2-DQS1_P
PNX5100-DDR2-DQS1_N
3C13
33R
3
3C06-3
LDQS
33R
B7
A8
UDQS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
UDM
LDM
VREF
A2
E2
L1
R3
R7
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
B3
F3
J2
8
3C07-3 3
3C07-2 2
3C06-1 8
3C06-2 7
3C09-3 3
3C09-2 2
3C08-1 8
3C08-2 7
5
6
3
6
33R
7
33R
1
33R
2
33R
6
33R
7
33R
1
33R
2
33R
3C05-4
4
33R
7
1
4
6
1
4
1 3C05-1
33R
2 3C05-2
33R
8 3C07-1
33R
5 3C07-4
33R
3 3C08-3
33R
3C11
33R
8 3C09-1
33R
5 3C09-4
33R
PNX5100-DDR2-D0
PNX5100-DDR2-D1
PNX5100-DDR2-D2
PNX5100-DDR2-D3
PNX5100-DDR2-D4
PNX5100-DDR2-D5
PNX5100-DDR2-D6
PNX5100-DDR2-D7
PNX5100-DDR2-D8
PNX5100-DDR2-D9
PNX5100-DDR2-D10
PNX5100-DDR2-D11
PNX5100-DDR2-D12
PNX5100-DDR2-D13
PNX5100-DDR2-D14
PNX5100-DDR2-D15
PNX5100-DDR2-DQM1
PNX5100-DDR2-DQM0
33R 3C05-3
PNX5100-DDR2-VREF-DDR
2C40
33R
VSS
A3
E3
J3
N1
P9
I
E
PNX5100-DDR2-DQS3_P
PNX5100-DDR2-DQS3_N
100n
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
3C04
PNX5100-DDR2-DQS2_P
PNX5100-DDR2-DQS2_N
150R
3
5
4
3C27-3
6
33R
3C27-4 33R 3C30-4
4
5
33R
3
6
22u
100n
2C38
100n
2C36
100n
2C35
100n
2C34
100n
2C33
2C32
VDD
ODT
CKE
WE
CS
RAS
CAS
J1
VDDQ
Φ
NC
0
1
2
3
4
5
6 A
7
8
9
10
11
12
CK
F7
E8
LDQS
B7
A8
UDQS
A2
E2
L1
R3
R7
R8
SDRAM
0
BA
1
J8
K8
3C30-3 33R
VSSQ
1u0
100n
L2
L3
A1
E1
J9
M9
R1
6
5
100n
2C44-4
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
PNX5100-DDR2-CLK_P
PNX5100-DDR2-CLK_N
F
4
2
3
100n
2C44-3
7
8
100n
2C44-2
100n
2C44-1
1
6
5
100n
2C43-4
4
7
100n
2C43-3
2
K9
K2
K3
L8
K7
L7
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A2
PNX5100-DDR2-A3
PNX5100-DDR2-A4
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A8
PNX5100-DDR2-A9
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
330u 6.3V
2C30
RES 2C29
DQ
CK
F7
E8
3
8
100n
2C43-2
100n
100n
2C18
100n
2C17
100n
2C16
100n
2C15
100n
2C14
1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
NC
0
1
2
3
4
5
6 A
7
8
9
10
11
12
6
33R
3C12
Φ
SDRAM
PNX5100-DDR2-ODT
PNX5100-DDR2-CKE
PNX5100-DDR2-WE
PNX5100-DDR2-CS
PNX5100-DDR2-RAS
PNX5100-DDR2-CAS
DQ
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B3
F3
UDM
LDM
G
8
3C26-3
3
3C26-2
2
3C27-1
8
3C27-2
7
3C28-2
7
3C28-3
6
3C30-1
8
3C30-2
7
6
33R
7
33R
1
33R
2
33R
2
33R
3
33R
1
33R
2
33R
7
1
4
5
8
5
3C25-3 6
1 3C25-1
33R
2 3C25-2
33R
8 3C26-1
33R
5 3C26-4
33R
3C31
33R
3C32
33R
4 3C28-4
33R
1 3C28-1
33R
PNX5100-DDR2-D16
PNX5100-DDR2-D17
PNX5100-DDR2-D18
PNX5100-DDR2-D19
PNX5100-DDR2-D20
PNX5100-DDR2-D21
PNX5100-DDR2-D22
PNX5100-DDR2-D23
PNX5100-DDR2-D24
PNX5100-DDR2-D25
PNX5100-DDR2-D26
PNX5100-DDR2-D27
PNX5100-DDR2-D28
PNX5100-DDR2-D29
PNX5100-DDR2-D30
PNX5100-DDR2-D31
3C25-4
3
4
33R
H
PNX5100-DDR2-DQM3
PNX5100-DDR2-DQM2
33R
J2
VREF
B
C
D
E
F
G
H
I
J
K
L
PNX5100-DDR2-VREF-DDR
M
2C39
VSS
A3
E3
J3
N1
P9
3C06-4 4
150R
5
7C02
HYB18TC512160CF-2.5
VDDQ
0
BA
1
J8
K8
3C03
PNX5100-DDR2-DQS0_P
PNX5100-DDR2-DQS0_N
1u0
2C13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A2
PNX5100-DDR2-A3
PNX5100-DDR2-A4
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A8
PNX5100-DDR2-A9
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
ODT
CKE
WE
CS
RAS
CAS
1K0 1%
PNX5100-DDR2-DQS3_P
PNX5100-DDR2-DQS3_N
3C22
E24
E23
1K0 1%
PNX5100-DDR2-DQS2_P
PNX5100-DDR2-DQS2_N
5
L2
L3
PNX5100-DDR2-CLK_P
PNX5100-DDR2-CLK_N
M
PNX5100-DDR2-DQS1_P
PNX5100-DDR2-DQS1_N
E25
E26
+1V8-PNX5100
100n
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
VDD
VDDL
3
100n
2C42-4
6
RES
2C00
H
K9
K2
K3
L8
K7
L7
VSSDL
L
PNX5100-DDR2-ODT
PNX5100-DDR2-CKE
PNX5100-DDR2-WE
PNX5100-DDR2-CS
PNX5100-DDR2-RAS
PNX5100-DDR2-CAS
J7
K
Y24
Y23
D
1C00
HOOK1
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
G
PNX5100-DDR2-DQS0_P
PNX5100-DDR2-DQS0_N
4
7
100n
2C42-2
2
100n
2C42-3
5
8
100n
2C42-1
1
7
8
6
100n
2C41-4
4
3
100n
2C41-3
100n
2C41-2
2C41-1
1
7C01
HYB18TC512160CF-2.5
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
F
2
I
J
P
N
W26
W25
+1V8-PNX5100
330u 6.3V
2C02
H
P
N
DQS3
PNX5100-DDR2-DQM0
PNX5100-DDR2-DQM1
PNX5100-DDR2-DQM2
PNX5100-DDR2-DQM3
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
E
DQS2
AA26
AA23
G26
G23
VDDL
D
0
1
2
3
B
C
VSSDL
1%
PNX5100-DDR2-VREF-DDR
100n
VSSQ
J7
3C01
820R
PNX5100-DDR2-CLK_P
PNX5100-DDR2-CLK_N
ODT
CKE
N23
P24
FC05
FC06
PNX5100-DDR2-VREF-CTRL
I
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
3C00
D
RASB
CASB
WEB
CSB
K23
U23
PNX5100-DDR2-ODT
PNX5100-DDR2-CKE
+1V8-PNX5100
F
BA0
BA1
BA2
PNX5100-DDR2-D0
PNX5100-DDR2-D1
PNX5100-DDR2-D2
PNX5100-DDR2-D3
PNX5100-DDR2-D4
PNX5100-DDR2-D5
PNX5100-DDR2-D6
PNX5100-DDR2-D7
PNX5100-DDR2-D8
PNX5100-DDR2-D9
PNX5100-DDR2-D10
PNX5100-DDR2-D11
PNX5100-DDR2-D12
PNX5100-DDR2-D13
PNX5100-DDR2-D14
PNX5100-DDR2-D15
PNX5100-DDR2-D16
PNX5100-DDR2-D17
PNX5100-DDR2-D18
PNX5100-DDR2-D19
PNX5100-DDR2-D20
PNX5100-DDR2-D21
PNX5100-DDR2-D22
PNX5100-DDR2-D23
PNX5100-DDR2-D24
PNX5100-DDR2-D25
PNX5100-DDR2-D26
PNX5100-DDR2-D27
PNX5100-DDR2-D28
PNX5100-DDR2-D29
PNX5100-DDR2-D30
PNX5100-DDR2-D31
3C23
K24
L24
U24
L23
A
Y26
AB25
Y25
AC26
AC25
U26
AB26
V26
W24
AB23
AA24
AC24
AC23
V23
AB24
V24
F26
H26
G25
J26
K26
D25
H25
D26
F23
H24
F24
J23
J24
D23
G24
D24
1K0 1%
PNX5100-DDR2-RAS
PNX5100-DDR2-CAS
PNX5100-DDR2-WE
PNX5100-DDR2-CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3C20
R26
T25
N24
DDR2
+1V8-PNX5100
1K0 1%
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
0
1
2
3
4
5
6
7
8
9
10
11
12
3C21
N26
U25
N25
T23
M26
T24
L25
R24
L26
M23
T26
K25
M24
2C43-1
C
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A2
PNX5100-DDR2-A3
PNX5100-DDR2-A4
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A8
PNX5100-DDR2-A9
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
22u
E
13
12
+1V8-PNX5100
7C00-8
PNX5100E
2C19
D
11
10
A
Φ
B
9
PNX5100 : SDRAM
A
C
8
7
1C00 D9
2C00 E4
2C01 D4
2C02 E4
2C13 F4
2C14 F5
2C15 F5
2C16 F5
2C17 F5
2C18 F6
2C19 F6
2C29 E10
2C30 E10
2C32 F11
2C33 F11
2C34 F12
2C35 F12
2C36 F12
2C38 F12
2C39 I12
2C40 I6
2C41-1 F1
2C41-2 F1
2C41-3 F2
2C41-4 F2
2C42-1 F2
2C42-2 F2
2C42-3 F2
2C42-4 F3
2C43-1 F8
2C43-2 F8
2C43-3 F8
2C43-4 F8
2C44-1 F9
2C44-2 F9
2C44-3 F9
2C44-4 F9
3C00 C2
3C01 D2
3C02 D3
3C03 H2
3C04 H8
3C05-1 G6
3C05-2 G6
3C05-3 I5
3C05-4 H5
3C06-1 H5
3C06-2 H5
3C06-3 H2
3C06-4 I2
3C07-1 G6
3C07-2 G5
3C07-3 G5
3C07-4 H6
3C08-1 H5
3C08-2 H5
3C08-3 H6
3C09-1 H6
3C09-2 H5
3C09-3 H5
3C09-4 H6
3C10 C4
3C11 H6
3C12 I2
3C13 I2
3C20 B9
3C21 B9
3C22 B12
3C23 B12
3C25-1 G12
3C25-2 G12
3C25-3 H11
3C25-4 H12
3C26-1 G12
3C26-2 G11
3C26-3 G11
3C26-4 H12
3C27-1 H11
3C27-2 H11
3C27-3 H9
3C27-4 I8
3C28-1 H12
3C28-2 H11
3C28-3 H11
3C28-4 H12
3C30-1 H11
3C30-2 H11
3C30-3 I8
3C30-4 I9
3C31 H12
3C32 H12
7C00-8 A6
7C01 F3
7C02 F9
FC05 B11
FC06 B9
IC04 C2
N
N
1
4
3
2
O
5
6
9
8
7
10
11
12
13
O
1X01
REF EMC HOLE
CHN
SETNAME
2
CLASS_NO
2008-11-21
DDR2 PNX5100
P
8204 000 8928
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
9
DATE
16
130
C
17
A2
1
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_518_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 104
SSB: PNX5100 - Video-In
1
4
3
2
1
2
5
3
6
8
7
4
6
5
10
9
8
7
12
11
13
9
A
PNX5100 : VIDEO-IN
A
A
B
RES
100R
3C14
RX51002A+
3C14 B2
3C15 B2
3C16 B2
3C17 C2
3C18 C2
3C19 D2
3C24 D2
3C29 D2
3C33 E2
3C34 E2
3C35 E2
3C36 F2
3C50 C6
3C51 C7
7C00-5 B4
7C00-9 C7
IC54 C7
A
B
RX51002ARX51002B+
7C00-5
PNX5100E
100R
3C15
B
RX51002BRX51002CLK+
100R
3C16
AE17
AF17
AC17
AD17
RX51002CLKRX51002C+
3C17
100R
AC16
AD16
D
AE16
AF16
RX51002C-
C
AE15
AF15
100R
3C18
RX51002D+
AC15
AD15
RX51002DRX51002E+
AE20
AF20
100R
3C19
E
AC20
AD20
3C24
D
100R
RX51002ERX51001A+
AC19
AD19
RX51001ARX51001B+
3C29
F
100R
AE19
AF19
AE18
AF18
AC18
AD18
100R
3C33
RX51001BRX51001CLK+
AP
AN
C
B
Φ
LVDS_RX
BP
BN
7C00-9
PNX5100E
CLKP
CLKN
LIN1
IC54
CP
CN
D6
A4
E2
G4
3C50
+3V3
3C51
1K0
DP
DN
1K0
G3
G2
G1
F4
F3
F2
F1
E3
E1
D2
D1
C1
A2
A3
B3
B4
EP
EN
AP
AN
BP
BN
CLKP
CLKN
LIN2
CP
CN
Φ
1
2
CLK
3
4
0
1
2
3
4
5
6
7
D
8
9
10
11
12
13
14
15
D
VDI
C
16
17
18
19
20
21
22
23
D
24
25
26
27
28
29
30
31
C4
A5
B5
C5
D5
A6
B6
C6
A7
B7
C7
D7
A8
B8
C8
D8
E
D
F
DP
DN
EP
EN
RX51001CLKRX51001C+
E
1K0
3C34
E
G
3C35
1K0
RX51001CRX51001D+
1K0
G
3C36
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
RX51001DRX51001E+
H
H
RX51001E-
F
F
I
I
1
2
3
5
4
6
8
7
CHN
9
SETNAME
2
CLASS_NO
2008-11-21
VIDEO PNX5100
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8928
TV543 R2 LDIPNX
8
9
130
9
SUPERS.
DATE
C
10
A3
2
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_519_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 105
SSB: PNX5100 - Power
1
3
2
1
4
2
5
3
6
4
9
8
7
6
5
11
10
7
8
12
13
9
A
PNX5100 : POWER
Φ
7C00-11
PNX5100E
CC60
+1V2-PNX5100-TRI-PLL2
L5
K4
+1V2-PNX5100-TRI-PLL3
T5
U4
H
VDDA_1V2_LVDS_PLL
VDDA_3V3_LVDS1
VDDA_3V3_LVDS2
VSSA_LVDS1
VSSA_LVDS2
AA22
AB22
F22
E22
VDD_1V2_MCAB1
VDD_1V2_MCAB2
VDDA_1V2_1_7_MCAB
VDDA_1V2_UIP_PLL
VDDA_3V3_SYS_PLL
VSS_MCAB1
VSS_MCAB2
VDDA_1V2_DLL1
VSSA_DLL1
VDDA_1V2_DLL4
VSSA_DLL4
VDDA_1V2_XTAL
VSSA_XTAL
P22
T22
+1V2-PNX5100-DDR-PLL1
AE25
+3V3-PNX5100-DDR-PLL0
N22
R22
+1V2-PNX5100
E15
B15
D15
A15
C15
+3V3-PNX5100-LVDS-PLL
AB14
AC14
AE14
AF12
AD14
AC13
AB13
+1V2-PNX5100
+1V2-PNX5100-CLOCK
+3V3-PNX5100-CLOCK
AD13
AE12
C
+1V2-PNX5100-CLOCK
IC80
5C60
+1V2-PNX5100-CLOCK
IC86
5C66
100n
2C88
+3V3-PNX5100-CLOCK
IC89
5C69
+3V3
100n
+1V2-PNX5100-DDR-PLL1
2C58
+1V2-PNX5100
2C90
30R
100n
+3V3-PNX5100-DDR-PLL0
IC84
5C64
E
100n
2C89
30R
+1V2-PNX5100-TRI-PLL3
5C70
IC85
IC90
100n
30R
100n 2C92
+1V2-PNX5100-LVDS-PLL
2C91
+3V3
+1V2-PNX5100
2C83
10u
IC88
5C68
+1V2-PNX5100
30R
IC87
+3V3
IC83
5C63
30R
100n
+3V3-PNX5100-LVDS-IN
30R
+1V2-PNX5100-TRI-PLL2
+1V2-PNX5100
30R
100n
5C67
+3V3
IC82
5C62
30R
100n
2C57
2C84
+1V2-PNX5100-TRI-PLL1
2C87
5C61
+1V2-PNX5100
100n
IC81
2C86
30R
30R
D
+1V2-PNX5100-DLL
+1V2-PNX5100
2C85 100n
30R
2C80
+1V2-PNX5100
5C65
F
B
+1V2-PNX5100-LVDS-PLL
+3V3-PNX5100-LVDS-PLL
F
100n
VSS
VDDA_1V2_TRI_PLL3
VSSA_TRI_PLL3
+1V2-PNX5100
100n
VSS
VDD_1V2_DDRPLL1
VSS_DDRPLL1
2C94
VDD_3V3_LVDSOUT
VDDA_1V2_TRI_PLL2
VSSA_TRI_PLL2
100n
VDD_3V3_LVDSIN
VDDA_3V3_DDRPLL0
100n
VSS
VDDD_1V2_TRI_PLL2
VSSD_TRI_PLL2
VDDA_1V2_DLL0
VSSA_DLL0
100n
VDD_3V3_PER
VDDA_1V2_DDRPLL1
VSSA_DDRPLL1
VDDD_1V2_TRI_PLL3
VSSD_TRI_PLL3
M22
L22
+1V2-PNX5100-DLL
100n
VSS
U5
U3
+1V2-PNX5100
2C62-2
VDD_1V8_DDR
VSS
VDDA_1V2_TRI_PLL1
VSSA_TRI_PLL1
AD25
AD26
100n
K5
K3
VDD_1V2_DDRPLL0
VSS_DDRPLL0
2
VDD_1V2_CORE
AD3
AE1
AE2
AF1
B1
A10
A13
A17
B2
A20
C2
C25
C3
D3
D4
E4
E5
F25
H23
J25
L11
L12
L13
L14
L15
M11
M12
M13
M14
M15
M25
N11
N12
N13
N14
N15
P11
P12
P13
P14
P15
P23
R11
R12
R13
R14
R15
R23
R25
T11
T12
T13
T14
T15
V25
W23
AE26
2C62-4
A1
AA25
AB3
AB4
AB5
AC1
AC2
AC3
AC4
AD1
AD2
AD24
100n
100n
2C76
100n
2C75
100n
2C74
A
+1V2-PNX5100-DLL
2C77
+1V2-PNX5100
Φ
SUPPLY_1
VDDD_1V2_TRI_PLL1
VSSD_TRI_PLL1
4
100n
100n
2C72
2C71
D10
D13
D17
D20
+3V3
2C73
J5
J4
2C63-3
100n
5
2C78-4
4
AB20
AB6
AB7
D22
E6
E7
G5
M5
N5
V5
W5
AB15
AB17
+3V3
GE
V22
U22
VDDA_1V2_DLL7
VSSA_DLL7
3
2C66-1
1
8
100n
2C66-2
2
7
100n
2C66-3
6
3
100n
2C66-4
4
5
100n
2C67-1
1
8
100n
2C67-2
2
7
100n
2C67-3
3
6
100n
2C67-4
4
5
100n
2C68-1
1
8
100n
2C68-2
2
7
100n
2C68-3
3
6
100n
2C68-4
4
5
100n
2C69-1
1
8
100n
2C69-2
2
7
100n
2C69-3
3
6
100n
2C69-4
4
5
100n
2C70-1
1
8
100n
2C70-2
2
7
100n
2C70-3
3
6
100n
2C70-4
4
5
100n
10u
10u
2C56
2C55
2C45
F
+1V2-PNX5100-TRI-PLL1
2C82
100n
2C65
2C64
100n
100n
2C63-1
1
8
100n
2C63-2
2
7
100n
2C63-4
4
5
100n
2C81
2C62-1
1
8
100n
2C62-3
3
6
100n
5
1
8
100n
2C61-2
2
7
100n
2C61-3
3
6
100n
2C61-4
4
5
100n
2C61-1
6
7
8
2C60-1
1
100n
2C60-2
2
100n
2C60-3
3
100n
2C60-4
4
100n
2C78-1
1
8
100n
2C78-2
2
7
100n
2C78-3
3
6
100n
+3V3
D
AA5
AB16
AB8
AB9
AC9
AD9
AE9
AF9
E16
E8
E9
F5
J22
K22
P5
R5
Y5
L16
M16
N16
P16
R16
T16
+1V8-PNX5100
220u 16V
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
D
E
+1V2-PNX5100
H5
J3
2C79
7C00-10
PNX5100E
+1V2-PNX5100
C
VDDA_3V3_LVDSIN
VSSA_LVDSIN
SENSE+1V2-PNX5100
10u
10u
2C97
10u
2C96
2C95
2C59
330u 10V
B
CB
AB18
AB19
+3V3-PNX5100-LVDS-IN
FC07
+1V2-PNX5100
100n
A
SUPPLY_2
I
1
2
3
4
5
6
7
CHN
8
5C62 E6
5C63 E6
5C64 F6
5C65 F6
5C66 D8
5C67 E8
5C68 E8
5C69 E8
5C70 F8
7C00-10 A4
7C00-11 A7
CC60 A3
FC07 A2
IC80 D7
IC81 D7
IC82 E7
IC83 E7
IC84 E7
IC85 F7
IC86 D9
IC87 E9
IC88 E9
IC89 E9
IC90 F9
2C45 D1
2C55 D1
2C56 D1
2C57 D9
2C58 F9
2C59 A1
2C60-1 B1
2C60-2 B1
2C60-3 B1
2C60-4 B1
2C61-1 B2
2C61-2 B2
2C61-3 B2
2C61-4 B2
2C62-1 B2
2C62-2 D6
2C62-3 B2
2C62-4 E6
2C63-1 B3
2C63-2 B3
2C63-3 E6
2C63-4 B3
2C64 B3
2C65 B3
2C66-1 C1
2C66-2 C2
2C66-3 C2
2C66-4 C2
2C67-1 C2
2C67-2 C2
2C67-3 C2
2C67-4 C2
2C68-1 D1
2C68-2 D2
2C68-3 D2
2C68-4 D2
2C69-1 D2
2C69-2 D2
2C69-3 D2
2C69-4 D2
2C70-1 D3
2C70-2 D3
2C70-3 D3
2C70-4 D3
2C71 E2
2C72 E2
2C73 E2
2C74 E2
2C75 E2
2C76 E3
2C77 C9
2C78-1 B1
2C78-2 B1
2C78-3 B1
2C78-4 D3
2C79 D6
2C80 D6
2C81 B3
2C82 F6
2C83 F6
2C84 D8
2C85 D9
2C86 D9
2C87 D9
2C88 E9
2C89 E9
2C90 F9
2C91 F8
2C92 F9
2C94 F7
2C95 A1
2C96 A2
2C97 A2
5C60 D6
5C61 D6
A
B
C
D
E
F
G
H
I
9
SETNAME
2
CLASS_NO
2008-11-21
SUPPLY PNX5100
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8928
TV543 R2 LDIPNX
8
SUPERS.
9
130
9
DATE
C
10
A3
3
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_520_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 106
SSB: PNX5100 - Audio
1
2
4
3
1
5
2
6
3
4
9
8
7
5
6
10
7
12
11
8
13
3C41 D4
3C95-1 B5
3C95-2 B5
3C95-3 B4
3C95-4 B4
7C00-6 B3
7C00-7 C3
9
A
PNX5100 : AUDIO
B
A
A
7C00-6
PNX5100E
AC22
AD22
C
AF22
AD23
AE23
AF23
B
AE22
Φ
OSCLK
SCK
0
1
SD
2
3
OSCLK
SCK
AUDIO
OUT
IN
4
100R
BL-OSCLK
5
3
AD21
100R
3C95-1
1
3C95-3
AE21
SD0
WS
3C95-4
AF21
AC21
C
BL-SCK
8
100R
B
BL-SD0
6
3C95-2
2
WS
B
BL-WS
7
100R
D
D
C
C
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
A
7C00-7
PNX5100E
Φ
E
F
AMBI
D
E
0
1
2
3
AMBI
4
5
6
7
CLK
DE
SYNC_H
SYNC_V
AF10
AE10
AD10
AC10
AB10
AF11
AE11
AD11
D
F
AC11
AB11
AB12
AC12
3C41
AMBI-VS
100R
G
G
E
E
H
H
2
1
3
4
5
6
7
8
9
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
AUDIO PNX5100
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8928
TV543 R2 LDIPNX
8
SUPERS.
9
DATE
9
130
C
10
4
A3
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_521_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 107
SSB: PNX5100 - LVDS
2
1
4
3
6
5
7
8
10
9
11
12
14
13
15
17
16
18
19
20
A
A
1
3
2
4
5
6
7
8
2CAS
2CAT
14
+VDISP2
2CH4
2CH5
TX2E+
TX2E-
B21
A21
TX2D+
TX2D-
D21
C21
E21
E20
TX2CLK+
TX2CLK-
F
D
H
E
TX2C+
TX2C-
C20
B20
TX2B+
TX2B-
B19
A19
TX2A+
TX2A-
D19
C19
TX1E+
TX1E-
B18
A18
TX1D+
TX1D-
D18
C18
TX1CLK+
TX1CLK-
E19
E18
TX1C+
TX1C-
C17
B17
TX1B+
TX1B-
B16
A16
D16
C16
TX1A+
TX1A-
2CA4
2CA5
Φ
TX1C+
LVDS_TX
LVDS1
IREF
LVDS2
RGB_CLK
A22
BP
BN
BP
BN
LOUT1
LOUT3
CP
CN
CLKP
CLKN
CP
CN
DP
DN
DP
DN
EP
EN
EP
EN
AP
AN
AP
AN
BP
BN
BP
BN
LOUT2
LOUT4
CLKP
CLKN
B14
A14
TX4E+
TX4E-
D14
C14
TX4D+
TX4D-
2CA6
2CA7
TX1CLK+
RES
4p7
4p7
RES
2CH7
10p
TX4CLK+
TX4CLK-
2CA8
2CA9
C13
B13
TX4C+
TX4C-
TX1D+
B12
A12
TX4B+
TX4B-
TX1E-
D12
C12
TX4A+
TX4A-
B11
A11
TX3E+
TX3E-
D11
C11
TX3D+
TX3D-
E11
E10
RES
FCAB
TX1ATX1A+
TX1BTX1B+
TX1CTX1C+
RES
4p7
4p7
RES
FCA0
FCA1
FCA2
FCA3
FCA4
FCA5
FCA6
RES
2CAA
2CAB
FCA7
TX1DTX1D+
TX1ETX1E+
4p7
4p7
RES
FCA8
FCA9
FCAA
FCAC
TX2ATX2A+
TX2BTX2B+
TX2CTX2C+
TX3CLK+
TX3CLK-
FCAD
FCAE
FCAF
FCAG
FCAH
TX2A-
CP
CN
C10
CP
B10
CN
TX3C+
TX3C-
DP
DN
DP
DN
B9
A9
TX3B+
TX3B-
EP
EN
EP
EN
D9
C9
2CAC
2CAD
TX2A+
TX3A+
TX3A-
RES
4p7
4p7
RES
RES 9C31
RES 9C32
FCJ5
TX1CLKTX1CLK+
TX1E+
ICA2
9C11
RES
10p
FCAJ
TX2CLKTX2CLK+
FCAK
FCAM
TX2DTX2D+
TX2ETX2E+
FCAN
FCAP
FCAR
TX2BRES
2CAE
2CAF
TX2B+
RES
SCL-DISP
SDA-DISP
4p7
4p7
RES
3CA3
100R
RES
I
FCBP
3CA2
100R
TX3CRES
2CAY
2CAZ
TX3C+
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TXCLK+
TX1DE13
E12
ICA1
9C10
RES
2CH6
TX1CLKRES
AP
AN
CLKP
CLKN
FC10
FCJ4
TXCLK-
AP
AN
CLKP
CLKN
4p7
4p7
RES
RES
2CB0
2CB1
TX3CLK+
4p7
4p7
RES
CTRL-DISP4
CTRL-DISP3
CTRL-DISP2
CTRL-DISP1
RES
4p7
4p7
RES
TX3ATX3A+
TX3BTX3B+
TX3CTX3C+
TX3D2CB2
2CB3
TX3D+
100R
3CAC
100R
RES
3CAE
100R
FCAV
2CB4
2CB5
2CB6
2CB7
100p
100p
100p
100p
100p
100p
FC15
FC16
FCAZ
FCB1
FCB2
FCB3
FCB4
FCB5
FCB6
FCB7
FCB8
FCB9
FCBA
FCBB
FCBC
FCBD
TX4A-
TX4A+
FC14
FCB0
TX4ATX4A+
TX4BTX4B+
TX4CTX4C+
RES
4p7
4p7
RES
RES
FC13
100R
3CAD
100R
FCAY
TX3DTX3D+
TX3ETX3E+
4p7
4p7
RES
FC19
FCAW
RES
TX3E+
100R
RES 3CAB
RES
TX3CLKTX3CLK+
TX3E-
FCAS
FCAT
100R
3CA9
3CAA
FC12
ICAE
60 61
58 59
56 57
54 55
52 53
FCBE
TX4CLKTX4CLK+
FCBF
FCBG
TX4DTX4D+
TX4ETX4E+
FCBH
FCBJ
FCBK
TX4BRES
2CB8
2CB9
TX4B+
FCBR
FCBM
4p7
4p7
RES
9CA0
+VDISP1
TO DISPLAY
FC17
TX4C2CAG
2CAH
TX2C+
RES
2CBY
RES
2CBZ
RES
RES
4p7
4p7
RES
2CBA
2CBB
TX4C+
4p7
4p7
RES
J
2CAJ
2CAK
TX2CLK+
RES
4p7
4p7
RES
2CBC
2CBD
TX4CLK+
TX2D-
B
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C
D
E
1G51
F
TO DISPLAY
TX4CLK-
TX2CLK-
RES
4p7
4p7
RES
TX4DRES
2CAM
2CAN
TX2D+
G
3CA5
100R
FI-RE51S-HF
9CA1
3CA4
SDA-DISP
SCL-DISP
TX3CLK-
TX2C-
F
4p7
4p7
RES
LAMP-ON-OUT
BACKLIGHT-OUT
1G50
10p
C
7C00-4
PNX5100E
ICA9
E17
E14
FCBN
10p
E
12K
12K
3CA6
3CA7
ICAA
TXDAT+
10p
10p
RES
FI-RE41S-HF
51
50
48
49
46
47
44
45
42
43
2CBL
RES
2CBM
RES
2CBN
RES
2CBP
RES
2CBR
RES
2CBS
RES
RES
RES
10p
TX3B+
FC08
TXDAT-
TX1C-
RES
2CAV 4p7
2CAW 4p7
RES
10p
TX3B-
RES
RES
4p7
4p7
RES
+3V3
B
A
4p7
4p7
RES
2CBJ
TX1B+
+3V3
TX3A+
9CA5
9CA4
9CA3
9CA2
2CA2
2CA3
RES
2CBE
2CBF
4p7
4p7
RES
TX4D+
4p7
4p7
RES
G
TX4E-
TX2ERES
owner.
is prohibited without the written consent of the copyright
13
2CBK
TX1A+
4p7
4p7
RES
TX1B-
All rights reserved. Reproduction in whole or in parts
12
RES
RES
2CA0
2CA1
C
K
11
TX3A-
TX1A-
A
G
10
PNX5100 : LVDS
B
D
9
2CAP
2CAR
TX2E+
RES
2CBG
2CBH
4p7
4p7
RES
TX4E+
4p7
4p7
RES
L
H
H
M
N
1
2
4
3
6
5
7
8
9
10
11
12
13
1G50 E8
1G51 F14
2CA0 A5
2CA1 A5
2CA2 B5
2CA3 B5
2CA4 B5
2CA5 B5
2CA6 C5
2CA7 C5
2CA8 C5
2CA9 C5
2CAA D5
2CAB D5
2CAC E5
2CAD E5
2CAE E5
2CAF E5
2CAG F5
2CAH F5
2CAJ F5
2CAK F5
2CAM G5
2CAN G5
2CAP G5
2CAR G5
2CAS A10
2CAT A10
2CAV B10
2CAW B10
2CAY B10
2CAZ B10
2CB0 C10
2CB1 C10
2CB2 C10
2CB3 C10
2CB4 D10
2CB5 D10
2CB6 E10
2CB7 E10
2CB8 E10
2CB9 E10
2CBA F10
2CBB F10
2CBC F10
2CBD F10
2CBE G10
2CBF G10
2CBG G10
2CBH G10
2CBJ B13
2CBK B13
2CBL B13
2CBM B13
2CBN B13
2CBP B13
2CBR B13
2CBS B14
2CBY F8
2CBZ F8
2CH4 B6
2CH5 B6
2CH6 B7
2CH7 C7
3CA2 E7
3CA3 E7
3CA4 B12
3CA5 B12
3CA6 B1
3CA7 B1
3CA9 B12
3CAA B12
3CAB C12
3CAC C12
3CAD C12
3CAE C12
7C00-4 B1
9C10 B7
9C11 C7
9C31 C8
9C32 C8
9CA0 E14
9CA1 B14
9CA2 B8
9CA3 B8
9CA4 B8
9CA5 B8
FC08 B7
FC10 B7
FC12 C12
FC13 C13
FC14 C13
FC15 C13
FC16 C13
FC17 E14
FC19 B12
FCA0 C7
FCA1 C7
FCA2 C8
FCA3 C7
FCA4 C8
FCA5 C7
FCA6 D8
FCA7 D7
FCA8 D8
FCA9 D7
FCAA D8
FCAB C8
FCAC D7
FCAD D7
FCAE D7
FCAF D8
FCAG D8
FCAH D8
FCAJ E8
FCAK E8
FCAM E8
FCAN E7
FCAP E7
FCAR E7
FCAS B12
FCAT B12
FCAV C12
FCAW C12
FCAY C12
FCAZ C12
FCB0 C12
FCB1 C12
FCB2 C12
FCB3 D12
FCB4 D12
FCB5 D12
FCB6 D12
FCB7 D12
FCB8 D12
FCB9 D12
FCBA D12
FCBB D12
FCBC D12
FCBD D12
FCBE E12
FCBF E13
FCBG E12
FCBH E12
FCBJ E12
FCBK E12
FCBM E14
FCBN B8
FCBP E8
FCBR E8
FCJ4 B7
FCJ5 C7
ICA1 B8
ICA2 B8
ICA9 B1
ICAA B1
ICAE B14
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
LVDS PNX5100
P
8204 000 8928
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
130
9
C
17
5
A2
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_522_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 108
SSB: PNX5100 - Control
1
2
3
5
4
6
9
8
7
11
10
12
13
A
A
1
2
3
5
4
6
7
B
PNX5100 : CONTROL
27p
2CD1
27p
2CD0
27M
AE13
3CD0
CLK-OUT-PNX5100
3CD3
D
B
AF14
FCD0
FCD1
FCD2
FCD3
FCD4
FCD8
RESET-PNX5100
+3V3
+3V3
10K
10K
+3V3
3CD1-4
3CD1-3
10K
10K
+3V3
3CD2
10K
3CD1-2
10K
3CD1-1
3C40
C
H4
H2
H3
J1
J2
AF24
ICD8
E
Φ
CONTROL
IN
OUT
UA1
TX
RX
UA2
TX
RX
AE8
AF8
XTAL
OUT2
AC8
AD8
100R
10K
EJTAG-PNX5100-TCK
EJTAG-PNX5100-TDI
EJTAG-PNX5100-TDO
EJTAG-PNX5100-TMS
EJTAG-PNX5100-TRSTn
A
7C00-1
PNX5100E
1CD0
R1
AB21
+3V3
TCK
TDI
TDO
TMS
TRST
1
SCL
SDA
2
SCL
SDA
3CD7
100R
100R
3CD8
SCL-SSB
SDA-SSB
L2
L1
3CDA
3CD9
100R
100R
RES
SCL-AMBI-3V3
SDA-AMBI-3V3
RESET_IN
B
PNX5100-RST-OUT
G22
H22
W22
Y22
NC
VPP_ID
+3V3
D
C
8
Φ
C08 OR C16
(2Kx8)
EEPROM
0
1
2
7
WC
FCD6
SCL
ADR
3CDD
5
SDA
WC-EEPROM-PNX5100
3CDC
6
3CDB
WC-EEPROM-PNX5100
+3V3
4K7
SCL-SSB
100R
SDA-SSB
only for DEBUG
D
100R
4
D
C
F
7CD0
M24C16-WDW6
1
2
3
B
E
+3V3
F
G
RES
AD12
RESET_SYS
OBSERVE
K2
K1
9CD0
A
AF13
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
1CD0 A2
2CD0 A2
2CD1 A2
3C40 C1
3CD0 B2
3CD1-1 C2
3CD1-2 C2
3CD1-3 C2
3CD1-4 C1
3CD2 C2
3CD3 B2
3CD7 B5
3CD8 B5
3CD9 B5
3CDA B5
3CDB D7
3CDC D6
3CDD D6
7C00-1 A3
7CD0 C4
9CD0 D7
FCD0 B3
FCD1 B3
FCD2 B3
FCD3 B3
FCD4 B3
FCD6 D5
FCD8 B3
FCD9 D5
ICD8 B3
G
FCD9
H
H
2
1
3
5
4
6
7
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
CONTROL PNX5100
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8928
TV543 R2 LDIPNX
8
SUPERS.
9
130
9
DATE
C
10
A3
6
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_523_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 109
SSB: PNX5100 - PCI
1
3
2
2
1
5
4
6
3
8
7
4
5
9
6
10
12
11
7
13
3CF1 C5
3CFK-1 B5
3CFK-2 B5
3CFK-3 B5
3CFL-1 B5
3CFL-2 B5
3CFL-3 B5
3CFN B5
7C00-2 A3
IC50 C5
IC51 C5
8
A
PNX5100 : PCI
A
B
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
D
AF5
AE4
AD4
AF3
AE3
AF2
AB2
AB1
AA4
AA3
AA2
AA1
Y4
Y3
Y2
Y1
W4
U1
T4
T3
T2
T1
R4
R3
R2
P4
P3
P2
P1
N4
N3
N2
PCI-AD0
PCI-AD1
PCI-AD2
PCI-AD3
PCI-AD4
PCI-AD5
PCI-AD6
PCI-AD7
PCI-AD8
PCI-AD9
PCI-AD10
PCI-AD11
PCI-AD12
PCI-AD13
PCI-AD14
PCI-AD15
PCI-AD16
PCI-AD17
PCI-AD18
PCI-AD19
PCI-AD20
PCI-AD21
PCI-AD22
PCI-AD23
PCI-AD24
PCI-AD25
PCI-AD26
PCI-AD27
PCI-AD28
PCI-AD29
PCI-AD30
PCI-AD31
B
C
7C00-2
PNX5100E
C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Φ
0
1
CBE
2
3
PAR
FRAME
IRDY
TRDY
STOP
DEVSEL
IDSEL
PERR
SERR
REQ
REQA
REQB
GNT
GNTA
GNTB
INTA
CLK
PLL_OUT
PCI_XIO
AD
XIO
AE5
AD5
AC5
AF4
W3
U2
V1
V2
V4
V3
L4
W1
W2
AD6
AC7
AD7
AE6
AF6
AE7
M1
L3
H1
A
PCI-CBE0
PCI-CBE1
PCI-CBE2
PCI-CBE3
PCI-PAR
PCI-FRAME
PCI-IRDY
PCI-TRDY
PCI-STOP
PCI-DEVSEL
PCI-AD25
PCI-PERR
PCI-SERR
RES
RES
RES
RES
RES
RES
3CFK-1 1
3CFK-3 3
3CFK-2 2
3CFL-1 1
3CFL-3 3
3CFL-2 2
3CFN
8
6
7
8
6
7
100R
100R
100R
100R
100R
100R
10K
A
B
B
C
+3V3
PCI-CLK-PNX5100
IC50
0
1
SEL
2
3
ACK
AD25
M2
M3
M4
N1
AC6
AF7
IC51
D
C
3CF1
+3V3
10K
E
E
D
D
F
F
E
E
G
G
1
2
3
5
4
6
7
8
H
H
I
I
CHN
SETNAME
2
CLASS_NO
PCI
J
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8928
TV543 R2 LDIPNX
2008-10-10
2008-11-21
PNX5100
8
SUPERS.
9
DATE
9
130
C
10
7
A3
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_524_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 110
SSB: PNX5100 - Display-Interfacing
7
6
3
4
5
6
PNX5100 : DISPLAY-INTERFACING
10
11
7
8
FCG0
1C01
100n
7C00-3
PNX5100E
ICH4
30R
RES
ICHA
CTRL4-PNX5100
C
BACKLIGHT-PWM-ANA-SSB
LCD-PWR-ON
BACKLIGHT-PWM-ANA-DISP
5CG2
30R
3CH2
2CG2
22u
RES
2K2
100R
BOOST-CTRL
FAN-CTRL-1
FAN-CTRL-2
+VDISP1
ICGZ
ICGV
BACKLIGHT-CTRL
CTRL3-PNX5100
CTRL2-PNX5100
CTRL1-PNX5100
6CG2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Φ
GPIO
7CG8
PDTA114EU
ICGW
BOOST-CTRL
LTST-C190KGKT
C
7CH1-1
BC847BPN(COL) 6
ICH7
+3V3
3CHC
470p RES
FCG3
BCG1
ICG9
47R RES
3CGH
FCG4
BCG2
ICGA
47R RES
3CGJ
FCG5
BCG3
3CGG
CTRL2-PNX5100
3CHE
9CH0
1K0
RES
RES
CTRL-DISP2
FCG7
E
1K0
CTRL-DISP1
3CHG
BCG0
15K
RES
FCG2
47R RES
ICG8
1
3
3CHF
3CG9
10K RES
2CH0
2
BC847BPN(COL)
7CH1-2
5
12K
7CH0
BC847BW
2
1
4K7 RES
4
ICH8
2CH1
3CGF
47R RES
100R
ICG7
CTRL1-PNX5100
47R RES
3CG8
3CG6
3CGA
3CG7
IC01
47R RES
ICH5
3CHB
3
ICH6
1u0 RES
+3V3
4K7
LCD-PWR-ON
D
ICH9
3CG5
CTRL4-PNX5100
27K
100n
2CG4
RES
ICG5
VDISP-SWITCH
CTRL3-PNX5100
3CHA
+3V3
47K
47K
ICG4 3CG0-2 ICG6 3CG0-3
2
7
3
6
10K
1
3CH9
3
47K
H
+12VD
7CG2
BC847BW
2
E
B
47K
BZX384-C5V6
G
BACKLIGHT-BOOST
+3V3
1u0
D
3CH0
100R
3CH8
ICG3
ICGY
+3V3
GPIO
CTRL-DISP3
CTRL-DISP4
47R RES
+12VD
100p
100p
2CG8
100p
2CG7
2CG5
I
100p
2CG6
RESERVED
NOTE : CAN BE
CAPACITOR OR
RES
WIRE BRIDGE
F
F
RES
47R
ICGN
2
IC03
9CG7
ICGR
3
9CG8
4K7 RES
2CGD
3C39
RES
ICGM
3CGS
47K
6
2
7CG6-1
BC847BPN(COL)
1
7CG6-2
BC847BPN(COL)
5
470K RES
7CG5
BC847BW
2 RES
1
ICH2
BACKLIGHT-CONTROL-FPGA-IN
47R
G
3
470p RES
3CH4
K
L
RES
15K
RES
3CGP
2CGC
1u0
2CGB
10K
3CGN
220u 25V
2C03
H
+3V3
1u0 RES
10K
9CG9
+3V3
FCG6
9CG4
+3V3F
1K0
10K
3CH5
ICGK
4
3CGR
3C38
CTRL4-PNX5100
ICH1
BACKLIGHT-CTRL
EN
2K2
RES
1
3
ICGP
3CH3
CTRL-DISP4
4
G
470K
10K
100n
3CGT
2C04
3C42
7C03
74LVC1G125GW
IC02
5
J
owner.
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
+3V3
3C37
3CGV
+3V3
BACKLIGHT-CTRL
H
ICGH
ICH3
7CG4
PDTC114EU
BACKLIGHT-PWM-ANA-SSB
BACKLIGHT-OUT
M
I
I
1
N
2
3
4
5
6
7
8
9
11
10
12
13
ICG3 C2
ICG4 D4
ICG5 D4
ICG6 D5
ICG7 E2
ICG8 E2
ICG9 E2
ICGA E2
ICGH H12
ICGK G13
ICGM G12
ICGN G11
ICGP G11
ICGR G10
ICGV B8
ICGW C3
ICGY B12
ICGZ B8
ICH1 G9
ICH2 G9
ICH3 H9
ICH4 A8
ICH5 D10
ICH6 D11
ICH7 D11
ICH8 D12
ICH9 D13
ICHA B8
ICHB B8
1C01 A5
1C02 B5
2C03 H5
2C04 G4
2CG0 A5
2CG1 B5
2CG2 C4
2CG3 C2
2CG4 D5
2CG5 F5
2CG6 F5
2CG7 F5
2CG8 F5
2CGB H12
2CGC H12
2CGD G11
2CH0 E11
2CH1 E12
3C37 G3
3C38 G3
3C39 G3
3C42 G9
3C43 A7
3C44 B8
3CG0-2 D5
3CG0-3 D5
3CG0-4 C3
3CG1 C2
3CG5 D4
3CG6 E5
3CG7 E5
3CG8 E5
3CG9 E5
3CGA E3
3CGF E3
3CGG E3
3CGH E3
3CGJ E3
3CGN H11
3CGP H12
3CGR H13
3CGS G12
3CGT G11
3CGV G13
3CGZ B12
3CH0 B12
3CH1 B12
3CH2 C4
3CH3 G11
3CH4 H11
3CH5 G11
3CH7 C2
3CH8 D11
3CH9 D11
3CHA D13
3CHB D12
3CHC D11
3CHD D11
3CHE E11
3CHF E12
3CHG E13
5CG0 A4
5CG1 A4
5CG2 B4
5CG3 B4
6CG0 C3
6CG2 C5
7C00-3 A9
7C03 G4
7CG0 B2
7CG1 C3
7CG2 C4
7CG4 H12
7CG5 G12
7CG6-1 G13
7CG6-2 G13
7CG8 B12
7CH0 D12
7CH1-1 D13
7CH1-2 D13
9CG0 B3
9CG1 B3
9CG4 H13
9CG7 G10
9CG8 G10
9CG9 H10
9CH0 E13
BCG0 E6
BCG1 E6
BCG2 E6
BCG3 E6
BCG5 A5
BCG6 B5
FCG0 A5
FCG1 B5
FCG2 E6
FCG3 E6
FCG4 E6
FCG5 E6
FCG6 H13
FCG7 E13
FCG8 B4
IC01 E3
IC02 G3
IC03 G3
ICG1 C4
ICG2 C2
14
ICG1
5 3CG0-4 4
6CG0
F
ICHB
3C44
AE24
AF25
AF26
C24
C26
B25
B26
A26
A25
A24
B24
A23
B23
C23
B22
C22
2K2
RES
47R
3.0A T 32V
BCG6
100n
30R
47K
2CG3
3CG1
13
20
+3V3
3CH7
C
E
1C02
5CG3
FCG8
ICG2
FCG1
2CG1
9CG1
RES
9CG0
RES
7CG1
SI3441BDV
12
19
18
A
3C43
3.0A T 32V
5CG1
7CG0
SI4835DDY
RES
11
17
BACKLIGHT-OUT2
BCG5
+VDISP2
30R
+12VD
10
9
16
15
10K
RES
5CG0
D
14
13
3CH1
A
B
12
+VDISP
2CG0
B
9
8
10K
RES
2
5
3CGZ
4
3CHD
1
A
3
100R
2
1
A
B
C
D
E
F
G
H
I
J
K
L
M
14
N
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
DISPLAY INTERF PNX5100
P
8204 000 8928
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
130
9
C
17
A2
8
ROYAL PHILIPS ELECTRONICS N.V. 2008
18
19
20
18310_525_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 111
SSB: PNX5100 - Debug
1
2
3
5
4
Personal Notes:
6
A
A
3CJ0 C3
3CJ1 C3
6CJ0 C3
7CJ0 D3
FCJ0 D3
B
B
1
2
4
PNX5100 : DEBUG
C
A
C
A
RESERVED
D
D
B
B
+3V3
C
3CJ0
10K
F
E
+3V3
F
330R
E
3CJ1
C
PNX5100-RST-OUT
6CJ0
SML-310
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
3
G
G
7CJ0
PDTC114EU
D
D
FCJ0
H
H
1
I
CHN
3
2
I
4
SETNAME
2
CLASS_NO
2008-11-21
DEBUG SHEET PNX5100
J
2008-10-10
J
8204 000 8928
TV543 R2 LDIPNX
3
NAME Maelegheer Ingrid
CHECK
1
SUPERS.
9
DATE
2
130
3
9
A4
ROYAL PHILIPS ELECTRONICS N.V. 2008
C
4
5
6
10000_012_090121.eps
090121
18310_526_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 112
SSB: FPGA Backlight-LVDS I2C-Mux
2
1
1
5
4
3
2
7
6
3
4
8
5
6
7
A
13
12
11
10
9
8
9
14
10
17
12
11
RESERVED
RES
3F36
13
14
3F37
SDA-DISP
4K7
+3V3
RES
9F16
SD1
7
VSS
3F39
150p
2F26
9F22
SDA-AMBI-3V3
IFA9
SDA-BOLT-ON
3FA6
+3V3
6
FFA9
220R
FF20
RES 4K7
+3V3
B
IN
OUT
5
FF11
FF15
FF16
+3V3
30R
IF29
5F06
IF12
100R
LTST-C190KGKT
IF34
IF35
69
3F26
10K
3F28
AMBI-VS
+3V3M
+3V3M
51
1
PROG-B
FF12
J
77
100
76
75
FF06
FF14
FF13
IP|VREF
VCCO
IP
PROG_B
VCCO
2F48
10p
10p
RES 2F47
RES 2F46
2F06
10p
2F07
10p
10p
10p
2F28
FF43
3F21
BL-MISO
FF23
100R
TXDAT-
FF24
FF31
TXDAT+
FF25
IF38
IF39
13
IF01
8
20
+2V5M
+2V5M
BL-CS
TXCLK-
3F29
100R
TXCLK+
E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16 15
F
502382-1470
3F30
BL-VS
100R
7
14
19
29
37
52
59
64
72
81
87
93
6
330R
3F15-3
G
3F31
BL-HS
100R
3
330R
330R
2 3F15-2 7
1 3F15-1 8
FF44
FF42
BANK3
TCK
TDI
TDO
TMS
FF07
K
FF40
FF41
100R
IF36
IF37
GND
G
1F53
3F20
BL-MOSI
DONE
2F08
2F04
33p
100R
+3V3M
+3V3M
2
3
4
5
9
10
11
12
15 9F05-4
16 9F05-3
17 9F05-2
18 9F05-1
22
23
IO_L01P
IO_L01N
IO_L02P
IO_L02N|VREF
IO_L03P|LHCLK0
IO_L03N|LHCLK1
IO_L04P|LHCLK2
IO_L04N|LHCLK3
IO_L05P|LHCLK4
IO_L05N|LHCLK5
IO_L06P|LHCLK6
IO_L06N|LHCLK7
IO_L07P
IO_L07N
BANK1
FF54
DONE
55
73
3F19
BL-CLK
BANK2
D
10p
LTST-C190KGKT
6F85
+2V5M +2V5M
FOR
DEBUG
F
6F84
+3V3
+3V3
RES
1K0
TO
TEMPERATURE
SENSOR
10p
100K
3F27
I
+2V5M
31
45
VCCO
3F10
9F08
+3V3
C
10p
DONE
IF19
9F00
9F01
9F02
1
2
3
4
10p
3F25
100K
LTST-C190KGKT
470R
470R
470R
470R
34
42
100R
1K0 RES
1K0 RES
1M71
3F18
SCL-SET
2F42
SML-310
6F83
3F82
3F83
3F84
3F85
10K
470R
LTST-C190KGKT
10K
3F14
+3V3M
7F05
BC847BW
9F03
3F07
3F08
CCLK
100R
10p
30
IP|VREF
IO|D5
IO|M1
IO_L01P
IO_L01N
IO_L02P
IO_L02N
IO_L03P|RHCLK0
IO_L03N|RHCLK1
IO_L04P|RHCLK2
IO_L04N|RHCLK3
IO_L05P|RHCLK4
IO_L05N|RHCLK5
IO_L06P|RHCLK6
IO_L06N|RHCLK7
IO_L07P
IO_L07N
3F09
100R
2F29
6F82
6F13
3F24
53
54
57
58
60
61
62
63
65
66
67
68
70
71
MISO
IF08
IF18
FF22
3F17
SDA-SET
+3V3
2F41
IF32
IF33
BL-SCK
BL-WS
BL-SD0
BL-OSCLK
E
100R
100R
9F06
IF15
IF16
IF17
2F03
38
39
IP_L05P|RDWR_B|GCLK0
IP_L05N|M2|GCLK1
VCCO
CLK-OUT-PNX5100
IF02
2F40
IP_L04P|GCLK8
IP_L04N|GCLK9
IO
BANK0
3F22
3F23
40
41
43
44
47
48
49
50
IO_L06P|D2|GCLK2
IO_L06N|D1|GCLK3
IO_L07P|M0
IO_L07N|DIN|D0
IO_L08P|VS2
IO_L08N|VS1
IO_L09P|VS0
IO_L09N|CCLK
FF21
1735446-4
100R
4p7
82
97
+3V3M
+3V3M
SCL-SSB
SDA-SSB
FF30
+3V3
owner.
1
100R
FF01
8
+3V3M
100n
9
8
MOSI
1
2
3
4
5
6
7
1F29
HOOK1
CCLK
CSO-B
*
FF03
5
FF04
6
FF05
3F06
100R
1
3
7
FOR
DEBUG
PROG-B
D
C
100n
100R
2F01
8
5
100R
3F16-4
4
6
3F16-3
100R
3F16-1
1
+3V3M
3F01
N
1F03
CSO-B
MOSI
MISO
CCLK
6 3F00-3
100R
8 3F00-1
H
7F01
M25P20-VMN
VCC
Φ
2M
FLASH
3F03
Q
2
S
FF02
MISO
10R
33p
3
IF00
4K7 RES
2F02
5
7
RES 2F05
I
3F00-4
100n
M
4
100R
3F00-2 2
100R
FF00
3F02
CSO-B
W
I
HOLD
VSS
4
1F05
1
2
3
4
5
6
7
3
H
100R
2 3F16-2 7
FOR FACTORY USE ONLY
L
RES 2F00
All rights reserved. Reproduction in whole or in parts
88
89
92
G
is prohibited without the written consent of the copyright
3F11
4u7
2F11
1
100n
2F19
2F18
D
100n
COM
IF14
3F40
3F41
1 100R
BACKLIGHT-CONTROL-FPGA-IN
3F12
MOSI
4p7
OUT
9F04
RES
1K0
+3V3M
+3V3M
IF07
IF09
RES
2FND
IN
BL-HS
BL-VS
2
RES 10K
RES
2FNE
7F07
LD1117DT12
3
+3V3
IO_L05P|GCLK10
IO_L05N|GCLK11
IO_L06P
IO_L06N|VREF
IO_L07P
IO_L07N|HSWAP
3F13
INIT
3F79
90
91
94
95
98
99
IF13
150R
RES
BL-CS
BL-MISO
IO_L01P|CSO_B
IO_L01N|INIT_B
IO_L02P|DOUT|BUSY
IO_L02N|MOSI|CSI_B
IO_L03P|D7|GCLK12
IO_L03N|D6|GCLK13
IO_L04P|D4|GCLK14
IO_L04N|D3|GCLK15
IO_L01P
IO_L01N
IO_L02P|GCLK4
IO_L02N|GCLK5
IO_L03P|GCLK6
IO_L03N|GCLK7
IF21
SDA-SET
CSO-B
RES
3F80
100n
+1V2M
24
25
26
27
32
33
35
36
150R
78
79
83
84
85
86
BL-MOSI
BL-CLK
F
IF20
SCL-SET
100n
2F15
100n
2F13
2F12
RES 2F09
100n
RES 2F10
120R
47u 6.3V
+1V2-PNX85XX
RES 30R
VCCINT
SPARTAN-3 FPGA
FF09
100n
2F14
C
Φ
VCCAUX
2
RES
5F02
+5V
6
28
56
80
21
46
74
96
7F00
XC3S100E-4VQG100C
1u0
COM
2F21
4
10n
BP
2F17
INH
1u0
2F16
3
B
5F05
100n
1
+3V3
SCL-DISP
SDA-DISP
SCL-BOLT-ON
SDA-BOLT-ON
+1V2M
+1V2M
+1V2M
+1V2M
D
+2V5M
+2V5M
+2V5M
+2V5M
1F50
7F06
LD3985M25
FF08
9F17
9F18
9F19 RES
9F20 RES
SCL-SET
SDA-SET
SCL-SET
SDA-SET
TO
AMBILIGHT
T 1A 63V
4
10p
SDA
9FA2
I2 C
-BUS
CTRL
1
2
3
4
5
6
7
FFA8
10p
2
9F11 RES
9F12 RES
INP
FIL
220R
1M59
FFA7
3FA5
9F21
2FA7
SCL
A
IFA8
SCL-AMBI-3V3
2FA6
SD0
SCL-DISP
SCL-SET0
SCL-BOLT-ON
SCL-SET1
SDA-DISP
SDA-SET0
SDA-BOLT-ON
SDA-SET1
RES
150p
8
9F15
1
100n
100n
RES 2F35
RES 2F34
100n
100n
2F25
100n
2F24
100n
2F23
5
SC1
2F27
100n
100n
2F39
100n
2F38
100n
2F37
100n
2F36
100n
2F33
100n
RES 2F31
RES 2F30
9F09 RES
9F10 RES
SDA-SET0
SDA-SET1
SDA-SET
+2V5M
2F20
SC0
9F14
FF10
100n
2F22
9F13
VDD
+2V5
120R
RES 4K7
9FA1
SCL-SET
SCL-SET0
SCL-SET1
RES
5F03
C
+3V3M
7F08
PCA9540B
4u7
2F32
A
120R
3FAB
+3V3M
+3V3
SCL-BOLT-ON
+3V3
3FAA
FF17
3
5F04
2K2
RES
+3V3
2K2
100n
2F49
4K7
3F38
H
20
SCL-DISP
+3V3
E
19
18
+3V3
FPGA Backlight-LVDS & I2C-MUX
B
16
15
100R
1
O
2
3
5
4
6
7
1X02
EMC HOLE
8
9
10
11
12
CHN
13
6F13 E2
6F82 E6
6F83 E6
6F84 E6
6F85 F6
7F00 B8
7F01 H9
7F05 E2
7F06 B2
7F07 D2
7F08 A6
9F00 D11
9F01 E11
9F02 E11
9F03 D10
9F04 D7
9F05-1 F9
9F05-2 F9
9F05-3 F9
9F05-4 F9
9F06 D10
9F08 E10
9F09 A5
9F10 A5
9F11 A5
9F12 A5
9F13 A8
9F14 A8
9F15 A8
9F16 A8
9F17 B6
9F18 B6
9F19 B6
9F20 B6
9F21 A12
9F22 A12
9FA1 A6
9FA2 A6
FF00 I2
FF01 I1
FF02 H10
FF03 H8
FF04 I8
FF05 I8
FF06 G4
FF07 G4
FF08 B6
FF09 C3
FF10 A3
FF11 B6
FF12 F7
FF13 G5
FF14 G4
FF15 B6
FF16 B6
FF17 A3
FF20 B14
FF21 C14
FF22 C14
FF23 F14
FF24 F14
FF25 F14
FF30 G5
FF31 F14
FF40 E14
FF41 E14
FF42 E14
FF43 E14
FF44 E14
FF54 F6
FFA7 A13
FFA8 A14
FFA9 A13
IF00 H9
IF01 F10
IF02 D10
IF07 C10
IF08 D9
IF09 C10
IF12 B3
IF13 C10
IF14 D7
IF15 D10
IF16 D10
IF17 D10
IF18 D9
IF19 E9
IF20 C13
IF21 C13
IF29 B14
IF32 E7
IF33 E7
IF34 F7
IF35 F7
IF36 E10
IF37 E10
IF38 F10
IF39 F10
IFA8 A11
IFA9 A10
1F03 H5
1F05 H1
1F29 I6
1F50 B14
1F53 E14
1M59 A14
1M71 C14
2F00 I2
2F01 H9
2F02 I10
2F03 D11
2F04 C11
2F05 I4
2F06 D13
2F07 D13
2F08 E13
2F09 C2
2F10 C2
2F11 D3
2F12 C2
2F13 C3
2F14 C3
2F15 C3
2F16 C2
2F17 C3
2F18 D1
2F19 D2
2F20 B2
2F21 C3
2F22 B2
2F23 B2
2F24 B2
2F25 B3
2F26 A11
2F27 A11
2F28 E13
2F29 F13
2F30 A2
2F31 A2
2F32 A2
2F33 A2
2F34 B3
2F35 B3
2F36 A3
2F37 A3
2F38 A3
2F39 A3
2F40 F13
2F41 G13
2F42 G13
2F46 C13
2F47 C13
2F48 C14
2F49 A6
2FA6 B13
2FA7 B13
2FND F11
2FNE F11
3F00-1 I3
3F00-2 I2
3F00-3 H2
3F00-4 H2
3F01 I2
3F02 H8
3F03 H10
3F06 I8
3F07 D11
3F08 D11
3F09 D11
3F10 E11
3F11 D7
3F12 C11
3F13 C10
3F14 F7
3F15-1 G4
3F15-2 G4
3F15-3 G5
3F16-1 H4
3F16-2 H4
3F16-3 H4
3F16-4 H5
3F17 D13
3F18 D13
3F19 E13
3F20 E13
3F21 F13
3F22 E7
3F23 E7
3F24 E1
3F25 E2
3F26 F6
3F27 F2
3F28 F4
3F29 F13
3F30 G13
3F31 G13
3F36 A8
3F37 A8
3F38 A8
3F39 B8
3F40 C13
3F41 C13
3F79 F10
3F80 F10
3F82 E7
3F83 E7
3F84 E7
3F85 E7
3FA5 A12
3FA6 A12
3FAA A10
3FAB A10
5F02 C1
5F03 A2
5F04 A2
5F05 B14
5F06 B14
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
SETNAME
2
CLASS_NO
2008-11-21
FPGA Backlight-LVDS & I2C-MUX
P
8204 000 8933
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
8
2007-12-04
130
C
17
A2
1
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_527_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 113
SSB: U-Wand
1
5
4
Personal Notes:
6
A
A
B
B
1F10 B3
1R20 A3
C
5FC5 A3
5FC6 A2
5FC7 A3
5FC8 A2
5FC9 A3
FFC2 A3
FFC3 A3
FFC4 A3
1
FFHC B3
FFHD B3
FFC5 A3
FFHB B3
FFHE B3
FFHF C3
FFHG C3
FFHH C3
FFHJ C3
FFHK C3
3
2
D
FFHL C3
IFC0 A2
IFC1 A3
IFC5 A2
C
4
D
U-WAND
RES U-WAND
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
3
2
A
E
5FC6
IFC5
5FC8
RXD-MIPS2
+12V
30R
30R
1
2
3
4
5
FFC3
FFC4
5FC7
IFC1
5FC9
30R
30R
A
1R20
FFC2
5FC5
IFC0
TXD-MIPS2
FFC5
30R
E
1735446-5
F B
B
1F10
FFHB
EJTAG-TRSTN
EJTAG-DETECT
EJTAG-TDI
FFHC
FFHD
EJTAG-TDO
FFHE
EJTAG-TMS
FFHF
EJTAG-TCK
FFHG
G
C
FFHH
FFHJ
FFHK
FFHL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F
FOR FACTORY
USE ONLY
G
C
5-147279-3
+3V3
H
H
2
1
4
3
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
U-WAND
J
2008-10-10
J
8204 000 8933
TV543 R2 LDIPNX
3
NAME Maelegheer Ingrid
CHECK
1
SUPERS.
DATE
2
8
2007-12-04
130
3
2
A4
ROYAL PHILIPS ELECTRONICS N.V. 2007
C
4
5
6
10000_012_090121.eps
090121
18310_528_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 114
SSB: Temperature & Fan control
1
3
2
1
A
4
5
2
6
4
3
8
7
9
7
6
5
10
11
13
12
8
9
TEMPERATURE- & FAN-CONTROL
1K0
3F65 RES
9F51
100n
9F50
+3V3
1u0
100p
2F55
1u0
2F54
2F53
IF66
5
9F52
FAN2-DRV
TACHO2
FF53
2F58
6F50
FF52
+12V
A2
IF64
6
4
1
2
3
A1
B
1K0
SCL
100R
1F02
+VS
SDA
2
IF62
1K0
3F64 RES
1
A0
3F63 RES
IF65
OS
GND
100p
2F52
1u0
2F51
2F50
SCL-SET
3
3F61
100R
3F62
7F50
LM75ADP
IF63
7
8
FAN1-DRV
TACHO1
FF51
B
D
1K0
FF50
+12V
SDA-SET
C
7F51
+12V
VDD
3F66
IF69
SCL-SET
3F59
1K0
8
E
100R
3F67
SDA-SET
D
IF68
Φ
6
SCL
7
FAN1-OUT
2
TACHO1-INV
5
LED3
6F51
SML-310
1
3
LED2
PCA9533
+12V
+12V
LED0
LED1
SDA
100R
D
TACHO2-INV
VSS
+12V
4
F
100n
2F59
C
IF54
PDTC114EU
27K
PDTA114EU
E
10K
+3V3
100n
3F69
IF58
+3V3
22K
2F60
RES
3F55
IF57
3F68
10K
10R
IF53
10K
3F52
3F56
2F56
E
3F54
100R
TACHO1
TACHO1-INV
RES
3F70
IF67
2
IF52
4
2
G
3F53
100R
10u
1
1u0
2F57
IF51
10R
7F54
7F53
BC857BW
1
7F52
BCP53
10K
3F51
3
FAN1-DRV
3F50
IF50
+12V
+3V3
1
7F57
RES
3F58
7F56
100R
FAN-CTRL-1
F
1K0
H
IF56
RES
3
10R
FAN1-OUT
IF59
RES
3F73
RES
7F55
BCP53
IF55
9F07
FAN2-DRV
RES
3F57
4
2
TACHO2
TACHO2-INV
27K
F
PDTA114EU
10K
100n
3F72
IF60
3F71
IF61
2F61
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
3F60
FF49
SML-310
1F01
1
2
3
C
A
+3V3
1u0
B
A
I
1
2
3
4
5
6
7
CHN
8
1F01 A1
1F02 B1
2F50 B2
2F51 B2
2F52 B2
2F53 C2
2F54 C2
2F55 C2
2F56 E4
2F57 E4
2F58 B8
2F59 C8
2F60 E8
2F61 F8
3F50 E3
3F51 E2
3F52 E5
3F53 E3
3F54 E4
3F55 E5
3F56 E2
3F57 F2
3F58 F3
3F59 D2
3F60 A7
3F61 B7
3F62 B7
3F63 C8
3F64 C9
3F65 B9
3F66 D7
3F67 D7
3F68 E8
3F69 E8
3F70 E6
3F71 F8
3F72 F8
3F73 F8
6F50 B7
6F51 D2
7F50 B7
7F51 C8
7F52 D3
7F53 E4
7F54 D9
7F55 E3
7F56 F9
7F57 F6
9F07 F6
9F50 B8
9F51 B9
9F52 C9
FF49 A2
FF50 A3
FF51 B3
FF52 C3
FF53 C3
IF50 D2
IF51 E3
IF52 E3
IF53 E4
IF54 E5
IF55 F2
IF56 F3
IF57 E8
IF58 E8
IF59 E6
IF60 F8
IF61 F8
IF62 B8
IF63 B7
IF64 B9
IF65 B7
IF66 B9
IF67 E4
IF68 D7
IF69 D7
A
B
C
D
E
F
G
H
I
9
SETNAME
2
CLASS_NO
2008-11-21
TEMPERATURE- & FAN-CONTROL
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8933
TV543 R2 LDIPNX
8
8
SUPERS.
DATE
9
2007-12-04
130
C
10
3
A3
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_529_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 115
SSB: FPGA WOW - LVDS In/Out
9FG5-2
2
7
9FGB-2
2
7
3
9FG5-1
TX852B+
1
9FGB-1
8
1
2
1
8
9FGC-4
4
5
9FG6-4
4
5
9FG6-3
3
6
TX852C+
9FGC-3
3
6
4
9FGC-2
2
7
9FG6-2
7
2
3
TXF2CLK-
RX51002CLK-
9FG6-1
TX852CLK+
1
8
9FGC-1
8
1
2
9FG7-4
4
5
1
TXF2D-
RX51002D-
4
100R
TX852D-
9FGD-4
4
5
9FG7-3
3
6
TX852D+
9FGD-3
3
6
9FGD-2
2
7
9FG7-2
2
7
3
9FG7-1
TX852E+
1
8
9FGD-1
1
8
2
2
1
3
150R
3FF5
3FF8
150R
180R
RES
2F77
4p7
RES
2F79
4p7
4
10p
10p
RES
2FNA
FFL2
RX51002CLKRES
2F80
4p7
RX51002CLK+
8
180R
3FFC-4
180R
+VDISP
RES
2F78
4p7
RX51002C+
180R 7
180R
RX51002CLKRX51002CLK+
RX51002DRX51002D+
RX51002ERX51002E+
RX51002C5
180R 6
180R
RES
2FN9
150R
3FFB
3FFE
150R
150R
3FFH
3FFL
RX51002B+
8
C
D
E
42
43
44
45
46
47
48
49
51
50
FI-RE41S-HF
RES
2F81
4p7
RX51002D-
5
RES
2F82
4p7
RX51002D+
6
F
TO DISPLAY
RES
2F83
4p7
RX51002E-
7
3FFC-1
TXF2E+
RX51002E+
RES
2F76
4p7
3FFC-2
TXF2E-
RX51002E-
100R
TX852E-
RX51002B-
3FFC-3
TXF2D+
RX51002D+
180R
RX51002CRX51002C+
7
3FFA-1
TXF2CLK+
RX51002CLK+
180R
RX51002ARX51002A+
RX51002BRX51002B+
RX51002A+
RES
2F75
4p7
3FFA-2
100R
TX852CLK-
RES
2F74
4p7
6
3FFA-3
TXF2C+
RX51002C+
RX51002A-
180R 5
180R
RX51001CLKRX51001CLK+
RX51001DRX51001D+
RX51001ERX51001E+
RES
2F73
4p7
3FFA-4
TXF2C-
RX51002C-
100R
TX852C-
RX51001E+
8
3FF9-1
TXF2B+
RX51002B+
RES
2F85
4p7
3FF9-2
TXF2B-
RX51002B-
180R
3FF9-3
TXF2A+
100R
TX852B-
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
30R
4
RX51002A+
RX51001E-
5FG2 RES
9FGB-3
3
6
RES
2F72
4p7
30R
9FG5-3
3
6
TX852A+
6
3FF9-4
TXF2A-
RX51002A-
180R
RES
1F51
RX51001CRX51001C+
100n
1
100R
TX852A-
RX51001D+
3FF7-1
TXF1E+
5
9FGB-4
4
5
RX51001DRES
2F71
4p7
3FF7-2
2
B
FFL4
RX51001ARX51001A+
RX51001BRX51001B+
RES
5FG1
4
180R
100R
RES
RES
2FN8
5
RES
2F70
4p7
5
3FF7-3
3
RX51001E+
180R 8
150R
TXF1E-
3FH5
RES
2F69
4p7
150R
9FGA-4
9FG5-4
4
5
3FG8
RX51001E-
SCL-DISP
RX51001CLK+
3FFP
9FGA-3
3
6
TXF1D+
RES
2F68
4p7
RX51001CLK-
180R 7
180R
FFL3
RX51001C+
6
3FFT
4
3FG9
4
RX51001D+
RES
2F67
4p7
3FF7-4
TXF1D-
100R
RES
RX51001C-
150R
3FG3
3FG5
E
3FGE
1
3FH4
5
3FF6-1
TXF1CLK+
100R
9FGA-2
2
7
9FG4-4
TX851E+
3FGA
2
100R
9FG4-3
3
6
3FG6
TX851E-
3FGB
TXF1CLK-
RX51001D-
180R
SDA-DISP
RES
2F66
4p7
3FF6-2
5
9FGA-1
1
8
8
150R
4
RES
2F65
4p7
RX51001B+
3FFW
5
9FG4-2
2
7
3FGC
3
RX51001CLK+
180R
A
RX51001B7
3FF6-3
TXF1C+
RX51001CLK-
RX51001A+
3FE0
9FG9-4
TX851D+
1
4
RX51001C+
180R
1F51 B9
2F62 A6
2F63 A6
2F64 A6
2F65 A6
2F66 B6
2F67 B6
2F68 B6
2F69 B6
2F70 C6
2F71 C6
2F72 C6
2F73 D6
2F74 D6
2F75 D6
2F76 E6
2F77 E6
2F78 E6
2F79 E6
2F80 F6
2F81 F6
2F82 F6
2F83 F6
2F84 F6
2F85 C6
2FN8 F8
2FN9 B8
2FNA B8
3FE0 E5
3FE3 F5
3FE6 F5
3FF4-1 A5
3FF4-2 A5
3FF4-3 A5
3FF4-4 A5
3FF5 A5
3FF6-1 B5
3FF6-2 B5
3FF6-3 B5
3FF6-4 B5
3FF7-1 C5
3FF7-2 C5
3FF7-3 C5
3FF7-4 C5
3FF8 A5
3FF9-1 E5
3FF9-2 D5
3FF9-3 D5
3FF9-4 D5
3FFA-1 F5
3FFA-2 E5
3FFA-3 E5
3FFA-4 E5
3FFB B5
3FFC-1 F5
3FFC-2 F5
3FFC-3 F5
3FFC-4 F5
3FFE B5
3FFH C5
3FFL C5
3FFP D5
3FFT D5
3FFW E5
3FG1 A2
3FG2 A2
3FG3 B2
3FG4 B2
3FG5 C2
3FG6 C2
3FG8 D2
3FG9 D2
3FGA E2
3FGB F2
3FGC F2
3FGE E2
3FH4 A8
3FH5 B8
5FG1 E8
9
RES
2F64
4p7
3FF6-4
TXF1C-
100R
9FG9-3
3
6
9FG4-1
1
8
TX851D-
I
1
5
9FG9-2
2
7
180R
12
11
8
RES
2F63
4p7
180R 6
3FF4-1
TXF1B+
100R
3FG4
4
F
2
RX51001C-
180R 5
3FF4-2
TXF1B-
RX51001B-
RX51001B+
9FG9-1
1
8
9FG3-4
TX851CLK+
H
4
9FG3-3
3
6
TX851CLK-
E
3
10
7
RX51001A-
3FF4-3
TXF1A+
RX51001A+
9
8
6
RES
2F62
4p7
150R
5
9FG3-2
2
7
TX851C+
F
9FG8-4
9FG3-1
1
8
TX851C-
D
4
100R
3FG2
4
D
9FG8-3
3
6
9FG2-4
TX851B+
C
9FG8-2
2
7
9FG2-3
3
6
TX851B-
C B
TXF1A-
RX51001A-
150R
9FG2-2
2
7
B
With FPGA
3FF4-4
100R
3FG1
A
9FG8-1
1
8
7
5
No FPGA
9FG2-1
1
8
TX851A+
owner.
6
5
4
3FE3
With FPGA
TX851A-
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
3
FPGA WOW - LVDS IN/OUT
A
G
4
2
3FE6
3
1
150R
2
1
RES
2F84
4p7
RX51002E+
180R 8
5
6
7
CHN
SETNAME
8
13
5FG2 E8
9FG2-1 A2
9FG2-2 A2
9FG2-3 A2
9FG2-4 A2
9FG3-1 B2
9FG3-2 B2
9FG3-3 B2
9FG3-4 B2
9FG4-1 C2
9FG4-2 C2
9FG4-3 C2
9FG4-4 C2
9FG5-1 E2
9FG5-2 D2
9FG5-3 D2
9FG5-4 D2
9FG6-1 F2
9FG6-2 E2
9FG6-3 E2
9FG6-4 E2
9FG7-1 F2
9FG7-2 F2
9FG7-3 F2
9FG7-4 F2
9FG8-1 A3
9FG8-2 A2
9FG8-3 A3
9FG8-4 A2
9FG9-1 B3
9FG9-2 B2
9FG9-3 B3
9FG9-4 B2
9FGA-1 C3
9FGA-2 C2
9FGA-3 C3
9FGA-4 C2
9FGB-1 E2
9FGB-2 D3
9FGB-3 D2
9FGB-4 D3
9FGC-1 F2
9FGC-2 E3
9FGC-3 E2
9FGC-4 E3
9FGD-1 F2
9FGD-2 F3
9FGD-3 F2
9FGD-4 F3
FFL2 E8
FFL3 A8
FFL4 B8
A
B
C
D
E
F
G
H
I
9
2
CLASS_NO
2008-11-21
FPGA WOW - LVDS IN/OUT
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8933
TV543 R2 LDIPNX
8
SUPERS.
DATE
9
8
2007-12-04
130
C
10
A3
4
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_530_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 116
SSB: FPGA WOW - Power & Control
1
4
3
2
2
1
A
5
3
8
7
6
4
9
6
5
11
10
13
12
8
7
14
9
15
10
17
16
11
19
18
1F00 E12
2FH0 B5
2FH1 B5
2FH2 A3
2FH3 A3
2FH4 A3
2FH5 A4
2FH6 E2
2FH7 E2
2FH8 E3
2FH9 E3
2FHA A3
2FHB C3
2FHC B3
2FHD B4
2FHE B4
2FHF B4
2FHG B4
2FHH B4
2FHJ B5
2FHK B5
2FHL B2
2FHM B2
2FHN C2
2FHP C3
2FHR C3
2FHS C3
2FHT B3
2FHV C3
2FHW D3
2FHZ D3
2FJ0 D3
2FJ1 D2
2FJ2 D2
2FJ3 F11
2FJ4 F11
2FJ5 F11
2FJ6 F11
2FJ7 D12
2FJ8 C2
2FJ9 C2
2FJA C3
2FJB C3
2FJC C3
2FJD F12
2FJJ B8
2FJK B7
2FJP B3
3FH0 H2
3FH1 H2
3FH2 H2
3FH3 H3
3FH6 H3
3FH7 H3
3FH8 D9
3FH9-1 D9
3FH9-2 D9
3FH9-3 E9
3FHB-1 E10
3FHB-2 E10
3FHB-3 E10
3FHB-4 E10
3FHG C9
3FHJ C12
3FHK C12
3FHL B11
3FHM B12
5FH0 A2
5FH1 B2
5FH2 C2
5FH3 D2
5FH4 E2
6FH0 I2
6FH1 I2
6FH2 I2
6FH3 I3
6FH6 I3
6FH7 I3
6FH8 B12
7FH0 B8
7FH2 C12
9FH0 D11
CFH0 B2
CFH1 D6
FFH0 A3
FFH1 B3
FFH2 B3
FFH3 C3
FFH4 D3
FFH5 E10
FFH6 E10
FFH7 E10
FFH8 E10
FFH9 E10
FFHA E3
FFHM B9
FFHN B9
FFHP B9
FFHR C9
FFHS C9
FFHT C11
IFH4 A7
13
12
FPGA WOW - POWER & CONTROL
FFH0
IFH4
3
W
7
HOLD
100n
2FHS
2FHB
2FHR
100n
2FHV
100n
2FHP
100n
4u7
30R
2FHN
100n
nCSO
CONF-DONE
VSS
3FHJ
FFHS
C
FFH3
5FH2
FFHR
3FHG
100n
DATA0
47R
+2V5
+2V5
+2V5
+2V5
2FJ7
+2V5
9FH0
RES
100n
2FJC
100n
2FJB
100n
2FJA
4u7
2FJ9
2FJ8
30R
D
C
+2V5out-FPGA
FFH4
5FH3
+2V5
+2V5in-FPGA
+1V8-PNX5100
G
3FHB-1
1
8
100R
4 3FHB-4 5
100R
2 3FHB-2 7
TCK
TDO
5FH4
FFHA
+2V5
TMS
+2V5-PLL
1F00
FFH5
1
2
3
4
5
6
7
8
9
10
FFH6
FFH7
100R
FFH8
FFH9
FOR
DEBUG
E
RES 100p
RES 10n
2FJD
5-147279-2
RES 100p
2FJ6
6
100R
RES 100p
2FJ5
1K0
H
3FH9-4
TDI
3FHB-3
2FJ3
3
RES 100p
2FJ4
100n
100n
2FH9
100n
2FH8
2FH6
100n
2FH7
30R
E
D
1K0
1K0
3FH9-1
CFH1
+1V8-PNX85XX
1K0
3FH9-3
RES
3FH8
100n
100n
2FHW
100n
2FHZ
100n
2FJ0
4u7
2FJ1
2FJ2
30R
RES 10n
+2V5
F
7FH2
BC847BW
100K
FFHT
4
E
3FHK
RES 100K
+3V3-FPGA
DCLK
FFHM
1
FFH2
5FH1
+3V3
FFHN
6
C
6FH8
D
B
ASDO
10K
16M
FLASH
FFHP
5
3FHL
Q
Φ
3FHM
8
VCC
2
S
D
+3V3
100n
7FH0
M25P16
2FH1
2FH0
10n
2FHK
10n
2FHJ
10n
2FHH
10n
2FHF
10n
2FHG
10n
2FHE
10n
2FHD
10n
2FHC
10n
10n
2FJP
2FHL
330u 6.3V
B
RES 2FHT
4u7
4u7
+1V2-FPGA
RES 2FJJ
2FJK
FFH1
CFH0
+1V2-PNX85XX
2FHM
100u 4V
C
100n
+2V5in-FPGA
1K0
100n
2FH5
100n
2FH4
100n
2FH3
2FH2
4u7
2FHA
100n
30R
5FH0
A
+3V3
+1V2-PLL
SML-310
A
B
FOR DEBUG
F
F
CON27
J
CON26
G
G
CON23
CON22
K
CON21
owner.
CON20
470R
LTST-C190KGKT
3FH7
6FH7
470R
LTST-C190KGKT
470R
3FH6
6FH6
LTST-C190KGKT
470R
3FH3
6FH3
3FH2
6FH2
LTST-C190KGKT
470R
470R
LTST-C190KGKT
6FH0
M
3FH1
3FH0
H
6FH1
H
L
LTST-C190KGKT
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
I
I
20
A
B
C
D
E
F
G
H
I
J
K
L
M
I
N
N
1
3
2
4
6
5
7
8
10
9
12
11
13
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
FPGA WOW - POWER & CONTROL
P
8204 000 8933
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
8
SUPERS.
DATE
16
2007-12-04
130
C
17
5
A2
ROYAL PHILIPS ELECTRONICS N.V. 2007
18
19
20
18310_531_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 117
SSB: FPGA WOW - DDR
4
3
2
1
6
5
8
7
9
12
11
10
13
A
A
1
B
2
3
4
7
6
5
8
FPGA WOW - DDR
A
F
MM1-CLK+
34
560R
3FLM
560R
3FLK
10u
100n
2FL5
100n
2FLS
100n
2FLR
100n
2FL4
100n
2FL3
2FL2
560R
100p
3FLN
100n
2FLC
1u0
2FLB
2FLA
1u0
2FL9
100p
2FL7
3FLL
560R
100n
RES 120R
2FLN
MM1-DQS0
MM1-DQS1
100n
22R
22R
100n
2FLM
3FLG
3FLH
100n
2FLL
DQS10
DQS11
+2V5-DDR1
120R
5FL1
2FLJ
DQS10
DQS11
+2V5
100n
2FLK
16
51
C
IFL1
5FL0
2FLH
MM1-D0
MM1-D1
MM1-D2
MM1-D3
MM1-D4
MM1-D5
MM1-D6
MM1-D7
MM1-D8
MM1-D9
MM1-D10
MM1-D11
MM1-D12
MM1-D13
MM1-D14
MM1-D15
22u 16V
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
100n
3FL0
3FL1
3FL2
3FL3
3FL4
3FL5
3FL6
3FL7
3FL8
3FL9
3FLA
3FLB
3FLC
3FLD
3FLE
3FLF
2FLF
DQ1(0)
DQ1(1)
DQ1(2)
DQ1(3)
DQ1(4)
DQ1(5)
DQ1(6)
DQ1(7)
DQ1(8)
DQ1(9)
DQ1(10)
DQ1(11)
DQ1(12)
DQ1(13)
DQ1(14)
DQ1(15)
100n
DQ1(0)
DQ1(1)
DQ1(2)
DQ1(3)
DQ1(4)
DQ1(5)
DQ1(6)
DQ1(7)
DQ1(8)
DQ1(9)
DQ1(10)
DQ1(11)
DQ1(12)
DQ1(13)
DQ1(14)
DQ1(15)
2FLE
61
15
55
L
DQS
U
VSSQ
VSS
MM1-CKE
MM1-CS0
MM1-RAS
MM1-CAS
MM1-WE
D
3
CLK
CLK
CKE
CS
RAS
CAS
WE
B
MM1-A12
2
4
5
7
8
10
11
13
54
56
57
59
60
62
63
65
2FLD
46
45
44
24
23
22
21
VREF
VREF-FPGA1
VREF-DDR1
330u 6.3V
220R 3FLJ
MM1-CLK-
49
FFL0
FFL1
RES
100n
D
14
17
19
25
43
50
53
42
D
64
VREF-DDR1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
DM
U
52
2FL6
0
BA
1
58
C
20
47
NC
A
12
26
27
VDDQ
DDR
SDRAM
8Mx16
6
MM1-BA0
MM1-BA1
Φ
66
D
VDD
0
1
2
3
4
5
6
7
8
9
10
11
AP
48
B
29
30
31
32
35
36
37
38
39
40
28
41
+2V5-DDR1
+2V5-DDR1
+2V5-DDR1
9
1
18
EDD1216AJTA-5B-E
MM1-A0
MM1-A1
MM1-A2
MM1-A3
MM1-A4
MM1-A5
MM1-A6
MM1-A7
MM1-A8
MM1-A9
MM1-A10
MM1-A11
33
100n
100n
2FLP
+2V5-DDR1
7FL0
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
100n
2FL1
2FL0
A
E
2FL0 A1
2FL1 A1
2FL2 B3
2FL3 B4
2FL4 B4
2FL5 B5
2FL6 C1
2FL7 B6
2FL9 B6
2FLA B8
2FLB B8
2FLC B8
2FLD C6
2FLE C6
2FLF D7
2FLH C7
2FLJ C8
2FLK C8
2FLL C8
2FLM C8
2FLN C9
2FLP A1
2FLR B4
2FLS B4
3FL0 B4
3FL1 B4
3FL2 C4
3FL3 C4
3FL4 C4
3FL5 C4
3FL6 C4
3FL7 C4
3FL8 C4
3FL9 C4
3FLA C4
3FLB C4
3FLC C4
3FLD C4
3FLE C4
3FLF C4
3FLG D4
3FLH D4
3FLJ D1
3FLK B6
3FLL B6
3FLM B9
3FLN B9
5FL0 C7
5FL1 C7
7FL0 B2
FFL0 B8
FFL1 B7
IFL1 C7
9
G
B
C
D
E
F
G
E
E
H
H
1
2
3
4
5
6
7
8
9
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
FPGA WOW - DDR
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8933
TV543 R2 LDIPNX
8
SUPERS.
DATE
9
130
8
2007-12-04
C
10
A3
6
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_532_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 118
SSB: FPGA WOW - I/O Banks
1
A
3
2
2FN2 D9
2FN3 D9
2FN5 D12
2F43 E7
2FN0 D9
2FN1 D9
2FN6 D13
2FN7 D13
3F74-2 B4
3F74-3 B2
3F74-4 B5
3FN1 A1
3FN2 B1
3FN3 B1
3FNF E7
2
1
B
5
4
7
6
3FNG E7
7FN0-1 A3
7FN0-10 F11
7FN0-5 C1
7FN0-6 C5
7FN0-7 C10
7FN0-2 A6
7FN0-3 A10
7FN0-4 A13
3
4
9
8
7FN0-8 C13
7FN0-9 E4
9FN0 D4
9FN7 E4
9FN8 D5
9FN9 D7
9FN1 D4
9FN4 E4
9FN6 E4
5
11
10
9FND C9
FF18 A1
FF19 B1
9FNA D7
9FNB D7
9FNC E7
6
FF48 B1
IFN0 A2
IFN1 A4
IFN5 B9
IFN6 B11
IFN7 B11
IFN2 B8
IFN3 B8
IFN4 B9
8
7
13
12
9
15
14
IFN8 B13
IFN9 B13
IFNA B15
IFNB B15
IFNC D13
IFND E11
IFNJ D3
IFNK D4
IFNL D4
IFNF D7
IFNG D5
IFNH D3
10
16
11
18
17
20
19
A
IFNM D5
IFNN D5
12
13
15
14
B
FPGA WOW - IO-BANKS
+1V2-PLL
+2V5-PLL
+2V5-PLL
BANK1
F2
3FN1 1K0 FF18
D
3FN2
+3V3-FPGA
10K
+3V3-FPGA
FF48
nCE
nCONFIG
nSTATUS
3FN3 10K FF19
B
nCE
nCONFIG
DCLK
nSTATUS
TCK
TDI
TDO
TMS
3F74-3
3 47R 6
IO_B2|L1P
IO_B1|L1N
IO_C1|L3N
IO_C3|L4P|RESET_
CE
IO_D3|L7P
CONFIG
IO_D2|L8P
DCLK
IO_D1|L8N|DATA1|ASDO
STATUS
IO_E2|L10P|FLASH_CE_|CSO_
TCK
IO_E1|L10N
TDI
IO_G2|L20P
TDO
IO_G1|L20N
TMS
IO_H2
IO_H3|DATA0
IO_C2|VREFB1N0
IO_F3|VREFB1N1
IO_H6|VREFB1N2
IO_H1|VREFB1N3
CLK1|CLK_0N
K6
H5
H4
G5
J1
J6
J5
J2
C2
F3
H6
H1
E
IFN1
B2
B1
C1
C3
D3
D2
3F74-2
D1 4
5
E2 47R
E1
2
G2
G1
H2
H3
CLK0|CLK_0P
F1
N2
N1
L6
M3
R1
R5
ASDO
nCSO
3F74-4
7
47R
TXF1A+
TXF1A-
K2
K1
K5
L5
L2
DATA0
TXF1B+
A
7FN0-4
EP3C40F324C7N
VCCA1
BANK2
BANK3
IO_L1|L32N
IO_L4|L33P
IO_L3|L33N
IO_M2|L34P
IO_M1|L34N
IO_P2|L44P
IO_P1|L44N
IO_R2|L45P
IO_T3|L52P
IO_R3|L52N
IO_M5
IO_R4
IO_T2|RUP1
IO_T1|RDN1
CLK2|CLK_1P
CLK3|CLK_1N
IO_L6|VREFB2N0
IO_M3|VREFB2N1
IO_R1|VREFB2N2
IO_R5|VREFB2N3
IO_K2|L26P
IO_K1|L26N
IO_K5|L28P
IO_L5|L28N
IO_L2|L32P
L1
L4
L3
M2
M1
P2
P1
R2
T3
R3
M5
R4
T2
T1
U9
TXF1BTXF1C+
TXF1CTXF1CLK+
TXF1CLKTXF1D+
TXF1D-
V9
P8
P7
T6
T4
TXF1E+
TXF1E-
U1
V1
P6
U3
V3
U4
V4
IFN4
IFN5
TXF2A+
TXF2ATXF2B+
TXF2B-
IFN2
IFN3
GNDA1
P5
IFN0
VCCD_PLL1
C
7FN0-3
EP3C40F324C7N
N5
A
7FN0-2
EP3C40F324C7N
VCCA3
VCCD_PLL3
P4
F5
7FN0-1
EP3C40F324C7N
E4
+1V2-PLL
C
CLK15|CLK_6P
CLK14|CLK_6N
IO_P8|VREFB3N0
IO_P7|VREFB3N1
IO_T6|VREFB3N2
IO_T4|VREFB3N3
IO_U1|B1P
IO_V1|B1N
IO_P6|B6P
IO_U3|B16P
IO_V3|B16N
IO_U4|B17P
IO_V4|B17N
IO_U5|B18P
IO_V5|B18N
IO_R8|B21P
IO_T8|B21N
IO_P9|B23N
IO_U6|B24P
IO_V6|B24N
IO_U7|B26P
IO_V7|B26N
IO_U8|B27P
IO_V8|B27N
IO_U2|PLL1_CLKOUTP
IO_V2|PLL1_CLKOUTN
BANK4
TXF2C+
TXF2C-
U5
V5
R8
T8
P9
U6
V6
U7
V7
U8
V8
U2
V2
TXF2CLK+
TXF2CLKTXF2D+
TXF2DTXF2E+
TXF2E-
TX852CLK+
U10
TX852CLK-
V10
P13
U16
T11
V12
U11
V11
U12
U13
V13
P10
P11
TX852E+
TX852E-
IFN6
IFN7
TX852D+
TX852DIFN8
IFN9
CLK13|CLK_7P
IO_U14|B34P
IO_V14|B34N
IO_U15|B35P
IO_V15|B35N
IO_R11|B36N
IO_V16|B44N
IO_U17|B47P
IO_V17|B47N
IO_R13|B48N
IO_P12
IO_T13|RUP2
IO_T14|RDN2
IO_U18|PLL4_CLKOUTP
IO_V18|PLL4_CLKOUTN
CLK12|CLK_7N
IO_P13|VREFB4N0
IO_U16|VREFB4N1
IO_T11|VREFB4N2
IO_V12|VREFB4N3
IO_U11|B28P
IO_V11|B28N
IO_U12|B29P
IO_U13|B32P
IO_V13|B32N
IO_P10|B33P
IO_P11|B33N
U14
V14
U15
V15
R11
V16
U17
V17
R13
P12
T13
T14
U18
V18
TX852C+
TX852CTX852B+
TX852B-
D
TX852A+
TX852A-
B
E
IFNA
IFNB
E5
GNDA3
+2V5-PLL
+2V5-PLL
+1V2-PLL
H
TX851B+
TX851BTX851C+
TX851C-
K17
K18
L17
M18
IO_K17|R29P
IO_K18|R29N
IO_L17|R32P|DEV_CLR_
IO_M18|R32N|DEV_OE
K14
K13
J18
J17
J14
IFNL
IFNM
IFNN
B17
H15
H18
J13
BACKLIGHT-OUT2
CON23
CON20
F14
F15
2F43
GNDA2
E
A10
A17
D12
C12
E11
D10
C10
B11
A11
B12
A12
B13
A13
CLK8|CLK_5N
IO_A17|VREFB7N0
IO_D12|VREFB7N1
IO_C12|VREFB7N2
IO_E11|VREFB7N3
IO_D10|T27P|PADD14
IO_C10|T27N|PADD13
IO_B11|T29P|PADD12
IO_A11|T29N|PADD11
IO_B12|T31P|PADD10
IO_A12|T31N|PADD9
IO_B13|T35P|PADD8
IO_A13|T35N|PADD7
B14
A14
B15
A15
B16
A16
E12
A18
D16
C16
E14
E13
D14
C14
MM1-D4
MM1-D3
MM1-RAS
MM1-D5
MM1-D6
MM1-CAS
MM1-D0
MM1-D7
J
F
K
G
L
M
F10
F12
F6
F8
G10
G11
G12
G13
G7
G8
H12
H7
J12
J7
K12
K7
L12
L7
M11
M12
M6
M7
M8
M9
N11
N13
N7
N9
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
VREF-FPGA1
VREF-FPGA1
VREF-FPGA1
VREF-FPGA1
MM1-WE
MM1-BA0
MM1-BA1
G
IFNC
B9
A9
E9
C7
D7
E6
D5
B3
A3
E7
B4
A4
E8
MM1-A8
MM1-A12
MM1-CKE
MM1-A6
MM1-A11
MM1-D8
MM1-D15
IFND
CLK11|CLK_4P
CLK10|CLK_4N
IO_E9|VREFB8N0
IO_C7|VREFB8N1
IO_D7|VREFB8N2
IO_E6|VREFB8N3
IO_D5|T3P|DATA12
IO_B3|T4P|DATA11
IO_A3|T4N|DATA10
IO_E7|T5N|DATA9
IO_B4|T6P|DATA8
IO_A4|T7N|DATA7
IO_E8|T8P|DATA6
IO_C5|T11P|DATA5
IO_B5|T16P|DATA13
IO_A5|T16N|DATA14
IO_B6|T18P|DATA15
IO_A6|T18N|PADD19
IO_B7|T19P|DATA4
IO_A7|T19N|PADD18
IO_B8|T20P|DATA3
IO_A8|T20N|DATA2
IO_D9|T24P|PADD17
IO_C9|T24N|PADD16
IO_E10|T25P|PADD15
IO_A2|PLL3_CLKOUTP
IO_A1|PLL3_CLKOUTN
C5
B5
A5
B6
A6
B7
A7
B8
A8
D9
C9
E10
A2
A1
MM1-D9
MM1-A9
MM1-DQS1
MM1-A7
MM1-D10
MM1-D11
MM1-D12
MM1-A5
MM1-D13
MM1-DQS0
MM1-D14
MM1-A4
MM1-CLK+
MM1-CLK-
D
H
E
I
7FN0-10
EP3C40F324C7N
VCC
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
7FN0-9
EP3C40F324C7N
BANK8
IO_B14|T36P|PADD6
IO_A14|T36N|PADD5
IO_B15|T37P|PADD4
IO_A15|T38N|PADD3
IO_B16|T41P|PADD2
IO_A16|T41N|PADD1
IO_E12|T45P|PADD0
IO_A18|T48P
IO_D16|T49P
IO_C16|T49N
IO_E14|RUP4
IO_E13|RDN4
IO_D14|PLL2_CLKOUTP
IO_C14|PLL2_CLKOUTN
1n0
CLK9|CLK_5P
1n0
1n0
1n0
VREF-FPGA1
VREF-FPGA1
CON26
VREF-FPGA1
SDA-AMBI-3V3
9FNA RES
VREF-FPGA1
CON22
9FNB RES
BACKLIGHT-OUT
MM1-A2
RES BACKLIGHT-CONTROL-FPGA-IN MM1-A3
9FNC 3FNF
MM1-A0
SDA-SSB
MM1-A1
100R
3FNG
SCL-SSB
CON21
MM1-A10
100R
MM1-D1
MM1-D2
MM1-CS0
B10
1n0
9FN9
RES
CON27
SCL-AMBI-3V3
1n0
B18
C17
C18
G14
H13
H14
D17
D18
H16
E17
E18
G17
G18
H17
2FN7
CONF-DONE
IFNK
MSEL0
MSEL1
MSEL2
MSEL3
IO_B18|R4N|PADD20
IO_C17|R5P|PADD21
CLK5|CLK_2N
IO_C18|R5N|PADD22
IO_G14|R7N|PADD23
CONF_DONE
IO_H13|R8P|RDY
IO_H14|R8N|AVD_
MSEL0
IO_D17|R12P|OE_
MSEL1
IO_D18|R12N|WE_
MSEL2
IO_H16|R23N
MSEL3
IO_E17|R24P|CLKUSR
IO_E18|R24N|CEO_
IO_B17|VREFB6N0 IO_G17|R27P|CRC_ERROR
IO_H15|VREFB6N1 IO_G18|R27N|INIT_DONE
IO_H18|VREFB6N2
IO_H17|R28P
IO_J13|VREFB6N3
CLK4|CLK_2P
2FN5
F18
P14
GNDA4
9FN8
IFNF
F17
2FN6
IO_L18|VREFB5N0
IO_N16|VREFB5N1
IO_R17|VREFB5N2
IO_R18|VREFB5N3
IFNG
CLK-OUT2-PNX5100
CLK-OUT-PNX5100
1n0
CLK7|CLK_3N
IFNH
IFNJ
TX851A+
TX851ATX851D+
TX851DTX851E+
TX851E-
L16
M17
L14
L15
L13
M14
P17
P18
T17
N15
T18
T16
R16
2FN3
L18
N16
R17
R18
IO_L16|R33P
IO_M17|R33N
IO_L14|R36P
IO_L15|R36N
IO_L13|R38P
IO_M14|R38N
IO_P17|R42P
IO_P18|R42N
IO_T17|R54N
IO_N15|R55P
IO_T18
IO_T16|RUP3
IO_R16|RDN3
7FN0-8
EP3C40F324C7N
BANK7
2FN2
TX851B+
CLK6|CLK_3P
9FN1
N18
9FN7
N17
TX851CLK-
9FN0 RES
D
TX851CLK+
7FN0-7
EP3C40F324C7N
VCCA2
BANK6
+3V3-FPGA
9FN4
G
VCCD_PLL2
2FN0
BANK5
E15
7FN0-6
EP3C40F324C7N
VCCA4
9FN6
VCCD_PLL4
9FND
RES
CLK-OUT2-PNX5100
N14
P15
7FN0-5
EP3C40F324C7N
2FN1
+1V2-PLL
I
F
C
C
1n0
F
VCCINT
VCCIO2
+2V5out-FPGA
+2V5out-FPGA
+2V5out-FPGA
R10
R12
R14
VCCIO4
VCCINT
+2V5in-FPGA
+2V5in-FPGA
+2V5in-FPGA
K15
M15
R15
VCCIO5
+2V5in-FPGA
+2V5in-FPGA
+2V5in-FPGA
F16
G15
J15
VCCINT
VCCIO6
+3V3-FPGA
+3V3-FPGA
+3V3-FPGA
D11
D13
D15
VCCIO7
+2V5-DDR1
+2V5-DDR1
+2V5-DDR1
D4
D6
D8
VCCIO8
C4
C6
C8
C11
C13
C15
E3
E16
F7
F9
F11
F13
G3
G6
G9
G16
H8
H9
H10
H11
J3
J8
J9
J10
J11
J16
+2V5out-FPGA
+2V5out-FPGA
+2V5out-FPGA
R6
R7
R9
VCCINT
H
+3V3-FPGA
+3V3-FPGA
+3V3-FPGA
K4
M4
N4
VCCIO3
VCCINT
GND
F4
G4
J4
VCCIO1
GND
GND
GND
GND
GND
GND
GND
GND
J
K3
K8
K9
K10
K11
K16
L8
L9
L10
L11
M10
M13
M16
N3
N6
N8
N10
N12
P3
P16
T5
T7
T9
T10
T12
T15
F
K
G
L
+2V5-DDR1
+2V5-DDR1
+2V5-DDR1
M
H
N
N
2
1
3
4
5
6
7
8
9
10
11
12
14
13
15
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
FPGA WOW - IO-BANKS
P
8204 000 8933
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
8
SUPERS.
DATE
16
2007-12-06
130
C
17
7
A2
ROYAL PHILIPS ELECTRONICS N.V. 2007
18
19
20
18310_533_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 119
SSB: CI: PCMCIA Connector
2
1
1P00-A B1
1P00-B B5
2P15 A8
2P16 C8
2P40 A2
3P09 A2
3
3P10-1 A6
3P10-2 A6
3P10-4 A6
3P11 C7
3P12 A6
3P13-1 A6
4
3P13-2 A6
3P13-3 A6
3P20 D2
3P24 D6
3P25 E6
3P26-1 E6
6
5
3P26-2 E6
3P26-3 E6
3P26-4 E6
3P27-1 E6
3P27-2 E6
3P27-3 E6
3P27-4 E6
3P80-1 B9
3P80-2 B9
3P82-1 D9
3P82-2 D9
3P82-3 D9
3P84-1 E8
3P84-2 E8
3P84-3 E8
3P82-4 D9
3P83-3 D9
3P83-4 D9
10
3
9
2
8
1
7
3P80-3 B9
3P80-4 B9
3P81 B9
3P84-4 E8
3P85-1 E8
3P85-2 E8
3P85-3 E8
3P85-4 E8
3P86 E8
5
12
11
4
7P16 C8
FP04 A2
FP05 D6
3P87 E8
3P88 E8
7P15 A8
IP00 A6
IP01 A6
IP02 A6
IP03 A6
IP04 A6
IP05 A6
13
6
IP08 D2
IP09 C9
IP18 D2
A
A
1
2
5
4
3
6
7
10
9
8
+3V3 PCMCIA-VCC-VPP
4
10K
3P10-2
7
2
10K
8 3P10-1 1
10K
RES 3P12
B
E
C
F
D
CABLE CARD INTERFACE
22u
PCMCIA-D3
PCMCIA-D4
PCMCIA-D5
PCMCIA-D6
PCMCIA-D7
CA-CE1
PCMCIA-A10
CA-OE
PCMCIA-A11
PCMCIA-A9
PCMCIA-A8
PCMCIA-A13
PCMCIA-A14
CA-WE
IRQ-CA
PCMCIA-VCC-VPP
CA-MIVAL
CA-MICLK
PCMCIA-A12
PCMCIA-A7
PCMCIA-A6
PCMCIA-A5
PCMCIA-A4
PCMCIA-A3
PCMCIA-A2
PCMCIA-A1
PCMCIA-A0
PCMCIA-D0
PCMCIA-D1
PCMCIA-D2
3P20
IP18
PCMCIA-VCC-VPP
IP08
10K
A
IRQ-CA
3EN1
3EN2
G3
18
MDO3
2
2
3
4
5
6
7
8
9
3P80-4
47R
3
3P80-2
47R 1
3P81
47R
4
2
CA-MDO3
3P80-3
47R
3P80-1
47R
CA-MDO4
CA-MDO6
CA-MDO5
CA-MDO7
D
B
+3V3
E
3P11
CA-RST
3EN1
3EN2
G3
100K
C
7P16
74LVC245A
1
19
IP09
MOCLK_VS2
18
MDO0
MDO2
MDO1
MOVAL
MOSTRT
17
16
15
14
13
12
11
2
1
2
G
3P24
3P25
3
2
H
C
19
1
17
16
15
14
13
12
11
MDO4
MDO6
MDO5
MDO7
7P15
74LVC245A
1
3
4
5
6
7
8
9
4
2
4
3P82-4
47R
3
3P82-2
47R 1
3P83-4
47R 3
F
CA-MOCLK_VS2
3P82-3
47R
3P82-1
47R
3P83-3
47R
CA-MDO0
CA-MDO2
CA-MDO1
CA-MOVAL
CA-MOSTRT
D
10
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
2P40
ROW_A
1P00-A
GND1
1
D3
2
D4
3
D5
4
D6
5
D7
6
CE1
7
A10
8
OE
9
A11
10
A9
11
A8
12
A13
13
A14
14
WE|P
15
RDY|BSY
16
VCC1
17
VPP1
18
A16
19
A15
20
A12
21
A7
22
A6
23
A5
24
A4
25
A3
26
A2
27
A1
28
A0
29
D0
30
D1
31
D2
32
WP|IOIS16
33
GND2
34
69 70
MOCLK_VS2
IP02
100n
+T 0R4
C
+3V3
2P15
PCMCIA-VCC-VPP
+5V
CA-WAIT
IP03
10K
CA-CD1
8 3P13-1 1
10K
IP04
CA-CD2
6 3P13-3 3
10K
IP05
CA-VS1
3P13-2
7
2
10K
ROW_B
1P00-B
GND3
35
CD1
CA-CD1
36
D11
MDO3
37
D12
MDO4
38
D13
MDO5
39
D14
MDO6
40
D15
MDO7
41
CE2
CA-CE2
42
VS1
CA-VS1
43
IORD
CA-IORD
44
IOWR
CA-IOWR
45
A17
CA-MISTRT
46
A18
CA-MDI0
47
A19
CA-MDI1
48
A20
CA-MDI2
49
A21
CA-MDI3
50
VCC2
51
PCMCIA-VCC-VPP
VPP2
52
A22
CA-MDI4
53
A23
CA-MDI5
54
A24
CA-MDI6
55
A25
CA-MDI7
56
VS2
MOCLK_VS2
57
RESET
CA-RST
58
WAIT
CA-WAIT
59
INPACK
CA-INPACK
60
REG
CA-REG
61
BVD2|SPKR
MOVAL
62
BVD1|STSCHG
MOSTRT
63
D8
MDO0
64
D9
MDO1
65
D10
MDO2
66
CD2
CA-CD2
67
GND4
68
FP05
71 72
FP04
B
CA-INPACK
100n
3P09
IP01
2P16
A
D
IP00
3P10-4
20
5
10
B
20
CI : PCMCIA CONNECTOR
1
E
4
4
3
2
1
G
MOSTRT
10K
MOVAL
3P26-310K
MDO0
10K
3P26-2
MDO1
10K
3P26-1
MDO2
10K
3P26-4
MDO3
10K
3P27-4
MDO4
10K
3P27-3
RESERVED
5
MDO3
MDO4
MDO5
MDO6
MDO7
MDO1
MDO2
MDO0
MOVAL
MOSTRT
8
6
8
3P84-4
47R 6
3P84-1
47R 7
3P88
47R 7
3P85-3
47R 5
3P85-1
47R
MDO5
10K
3P27-2
MDO6
10K
3P27-1
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
CA-MDO1
CA-MDO2
CA-MDO0
CA-MOVAL
CA-MOSTRT
3P84-3
47R
3P84-2
47R
3P85-2
47R
3P85-4
47R
3P86
47R
3P87
47R
MOCLK_VS2
H
E
CA-MOCLK_VS2
MDO7
10K
I
1
2
3
5
4
I
7
6
CHN
1X06
EMC HOLE
1X05
REF EMC HOLE
9
8
10
SETNAME
2
CLASS_NO
2008-11-21
UFD2K8
J
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8934
DIGI i/O TV543 R2 LDIPNX
1
8
SUPERS.
DATE
9
2
130
8
2007-10-18
C
10
3
A3
1
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
4
12
5
6
13
18310_534_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 120
SSB: Audio In HDMI
1
2
3
4
5
6
9
8
7
10
11
13
12
A
A
1
3
2
4
5
6
1P0A B2
1P0B D2
1P9A B3
1P9B D3
2P06 B2
2P07 B3
2P08 B4
2P09 D2
2P10 D3
2P11 D4
3P05 B3
3P06 B4
3P07 D3
3P08 D4
6P01 B3
6P02 D3
FP01 D2
FP02 B2
FP24 D2
IP06 B4
IP07 D4
7
AUDIO IN HDMI
B
A
A
100n
RES
2P07
6P01
FP02
B
IP06
3P05
AUDIO-IN4-L
C
100p
100K
1n0
1P9A
2P06
1P0A 1
D
RES
2P08
1K0
RES
3P06
YKB11-3004
2
V_NOM
B
D
+12V
C
C
E
2P10
100n
AUDIO-IN4-R
F
D
100p
100K
1P9B
1P0B 1
RES
2P11
1K0
FP24
RES
3P08
D
IP07
3P07
1n0
F
FP01
V_NOM
YKB11-3004
2
BZX384-C
6P02
E
2P09
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
BZX384-C
+12V
B
G
G
E
E
H
H
2
1
3
4
5
7
6
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
UFD2K8
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8934
DIGI I/O TV543 R2 LDIPNX
8
8
SUPERS.
DATE
9
2007-10-18
130
C
10
2
A3
ROYAL PHILIPS ELECTRONICS N.V. 2005
11
12
13
18310_535_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 121
SSB: USB Connector
Personal Notes:
3
2
1
4
6
5
A
A
1P07 C4
1P10 C2
2P17 A1
B
2P31 A1
3P16 A2
3P17 A2
2P24 B2
2P27 A1
2P30 A1
1
5P07 A2
9P21 C3
9P22 C3
2
FP27 C3
FP28 C3
FP29 C3
IP13 C2
IP19 C2
FP2A C3
FP45 B1
IP12 A2
3
B
4
C
USB CONNECTOR
C
+5V
3P56
100R
RES
100R
100R
3P55
3P21
100R
3P23
3P19
A
100R
3P18
180R
RES
180R
RES
3P17
RES
3P16
180R
+5V
D
A
D
0R4
3P59
+T
22u
220u 16V
2P31
2P30
330u 10V
2P17
2P27
220u 16V
+3V3
IP12
5P07
FP45
3P62
USB-OC
47u 6.3V
2P24
B
E
B
100K
E
56K
3P60
220R
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
3P59 A2
3P60 B2
3P62 B2
3P23 A4
3P55 A4
3P56 A4
3P18 A2
3P19 A3
3P21 A3
USB
CONNECTOR
F
F
1P07
FP27
FP28
FP29
FP2A
USB20-DM
USB20-DP
C
5
1P10
1
2
3
4
5
G
6
1
2
3
4
C
292303-4
IP13
9P21
9P22
G
IP19
6
7
502382-0570
1
2
3
4
H
H
I
I
CH N
SETNAME
2
CLASS_NO
2008-11-21
DIGI I/O UFD2K8
J
2008-10-10
J
8204 000 8934
TV 543 R2 LDIPNX
3
NAME Maelegheer Ingrid
CHECK
1
SUPERS.
DATE
2
8
2007-10-18
130
3
A4
3
ROYAL PHILIPS ELECTRONICS N.V. 2007
C
4
5
10000_012_090121.eps
090121
6
18310_536_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 122
SSB: HDMI
3
2
7
6
3
4
8
5
9
6
10u
Replacing the TDA 9996
Requires reprogramming
5P11
FP13
AIN-5V
BP1D
CRX1CRX0+
BP1E
BP1F
FP07
CRX-DDC-SCL
CRX-DDC-SDA
FP08
FP09
FP0A
CRX-DDC-SCL
CRX-DDC-SDA
CIN-5V
CRX-HOTPLUG
20
FP0C
3P68
FP06
47K
CRXCPCEC-HDMI
3P67
CRX0CRXC+
BP1G
BP1H
3P75
PCEC-HDMI
IP5U
IP5V
IP5Y
9P0J
CEC-HDMI
100R
DC1R019WBER220
CIN-5V
BC847BW
7P32
WC-EEPROM-PNX5100
I
I
N
DRX1DRX0+
BP5R
DRX0DRXC+
BP5P
BP5S
FP0T
FP0U
DRX-DDC-SCL
DRX-DDC-SDA
3P38
63
62
66
65
69
68
72
71
DRXC+
DRXCDRX0+
DRX0DRX1+
DRX1DRX2+
DRX2-
81
80
84
83
87
86
90
89
+
+
+
+
+
+
+
+
-
DRX-DDC-SCL
DRX-DDC-SDA
100n
100n
2P55
100n
2P54
100n
2P53
100n
2P52
100n
2P51
100n
2P50
100n
2P35
100n
55
IP17
2P45
D2
RXA DDC
C
D0
2P56
10
12
11
9
5V
CLK
DAT
HPD
D1
D2
RXC DDC
C
D0
RXC
D2
C
CDEC
D0
RXD
3P34
AIN-5V
100n
+5V
BIN-5V
BRX-DDC-SCL
BRX-DDC-SDA
BRX-HOTPLUG
2P58
5V
CLK
DAT
HPD
CIN-5V
100n
CRX-DDC-SCL
CRX-DDC-SDA
CRX-HOTPLUG
G
2P59
100n
77
79
78
76
DDC
STBY
57
DIN-5V
DRX-DDC-SCL
DRX-DDC-SDA
DRX-HOTPLUG
6P03
IP10
44
54
BAT54 COL
IP11
FP22
27
TEST
D2
F
ARX-DDC-SCL
ARX-DDC-SDA
ARX-HOTPLUG
59
61
60
58
CEC
D1
12K 1%
2P57
5V
CLK
RXD DDC
DAT
HPD
D1
100n
29
31
30
28
5V
CLK
RXB DDC
DAT
HPD
RXB
REF-3V3
3P14
74
R12K
DDC-SCL
DDC-SDA
FP44
48
PD
RXA
D1
FP03
5
6
CLK
DAT
1K8
4
D0
H
25
NC
VSS
IP26
DRXCPCEC-HDMI
FP0R
FP0S
CRXC+
CRXCCRX0+
CRX0CRX1+
CRX1CRX2+
CRX2-
+
+
+
+
-
DDC
C
PCEC-HDMI
5P15
FP43
IP60
+5V
3P47
4R7
30R
FP23
2P33
BP5N
BP5M
33
32
36
35
39
38
42
41
+
+
+
+
-
1
7
18
26
37
43
56
67
73
85
92
98
BP5L
DRX2DRX1+
BRXC+
BRXCBRX0+
BRX0BRX1+
BRX1BRX2+
BRX2-
MODE
DIN-5V
3P53
BP5K
+5V-EDID
+3V3
I
3P66
DIN-5V
47K
DIN-5V
DRX-HOTPLUG
20
23 22
BP1W
DRX2+
14
13
17
16
20
19
23
22
22K
BP5J
3P65
1P05
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FP17 21
M
+3V3-STANDBY
HDMI CONNECTOR SIDE
H
47K
L
H
22K
IP5Z
BC847BW
7P12
WRITE-PROT
ARXC+
ARXCARX0+
ARX0ARX1+
ARX1ARX2+
ARX2-
OUT
E
+5V
3P36
BP1C
23 22
25 24
26
BP1V
CIN-5V
CRX2CRX1+
INT
HP_CTRL
HDMIB-RXC+
HDMIB-RXCHDMIB-RX0+
HDMIB-RX0HDMIB-RX1+
HDMIB-RX1HDMIB-RX2+
HDMIB-RX2-
100n
G
K
G
CRX2+
47K
J
47
BP1A
owner.
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
F
F
53
1K0
HDMI CONNECTOR 1
I
FP21
2
3
99
100
96
97
93
94
1K8
3P43
+
+
D0
+
D1
+
D2
C
100n
+3V3
SCL
I2C
SDA
0
SEL
1
2P32
100R
XTAL
OUT
100n
SDA-SSB
BP1B
100n
2P43
3P77
IN
VDDS_3V3
52
50
49
Φ
VDDH_3V3
2P28
E
1P02
2P05
2P34
2P37
100n
3P76
SCL-SSB
BIN-5V
51
100R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FP1619
21
2P36
2P38
100n
9P33
REF-3V3
FP26
7P02
TDA9996
VDDO_3V3
FP0J
15
21
34
40
64
70
82
88
BRX-HOTPLUG
20
DC1R019WBER220
HE
C
D
46
BIN-5V
+3V3
30R
FP25
VDDC_3V3
FP0G
FP0H
BRX-DDC-SCL
BRX-DDC-SDA
95
BRX-DDC-SCL
BRX-DDC-SDA
24
75
FP0E
FP0F
2P39
100n
BRXCPCEC-HDMI
2P41
100n
BP5H
5P08
BIN-5V
100n
BRX0BRXC+
2P42
100n
BP5G
30R
+1V8-PNX85XX
3P63
BP5E
BRX1BRX0+
BP5F
23 22
25 24
26
BP1U
BRX2BRX1+
FP39
FP41
8
45
91
G
BP5C
BP5D
RES
5P14
47K
D
BRX2+
BP5B
3P64
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FP0P 21
BP5A
2P46
30R
30R
1V8-HDMI
47K
F
HDMI CONNECTOR 2
1P03
B
FP40
5P12
+3V3
100n
20
2P44
ARX-HOTPLUG
22u
AIN-5V
of its I2C address from
0xC0 to 0xCE
FP20
30R
+3V3
100n
ARX-DDC-SCL
ARX-DDC-SDA
FP15
VDDO_1V8
ARX-DDC-SCL
ARX-DDC-SDA
47K
ARXCPCEC-HDMI
FP11
FP12
2P49
ARX0ARXC+
1
BP1R
BP1S
A
I2C Address = 0xCE
AIN-5V
FP0W
DC1R019JB1E400
1
2
4
3
5
6
7
8
9
10
11
13
12
FP0S I1
FP0T I2
FP0U I2
FP0W I1
FP10 B1
FP11 B1
FP12 B1
FP13 B1
FP14 B2
FP15 B1
FP16 G1
FP17 I1
FP20 B11
FP21 E9
FP22 H12
FP23 I10
FP25 D8
FP26 D12
FP39 C12
FP40 C11
FP41 C10
FP42 A6
FP43 H12
FP44 F13
IP10 G12
IP11 H12
IP17 F13
IP26 H5
IP5U G6
IP5V G7
IP5Y G6
IP5Z H6
IP60 H13
1P02 E1
1P03 C1
1P04 A1
1P05 H1
2P03 C6
2P05 C10
2P28 H13
2P32 H13
2P33 I12
2P34 D12
2P35 D12
2P36 D10
2P37 D10
2P38 D9
2P39 D9
2P41 D9
2P42 D9
2P43 D12
2P44 C10
2P45 C11
2P46 B10
2P47 C10
2P48 A5
2P49 A6
2P50 D12
2P51 D12
2P52 D13
2P53 D13
2P54 D13
2P55 D13
2P56 F12
2P57 F12
2P58 G12
2P59 G12
3P14 F13
3P34 E14
3P36 F14
3P38 H6
3P43 E9
3P47 H14
3P53 H5
3P58 B4
3P61 B4
3P63 D4
3P64 D4
3P65 I4
3P66 I4
3P67 F3
3P68 G3
3P75 G5
3P76 E9
3P77 E9
5P08 C12
5P11 B10
5P12 C10
5P13 C10
5P14 C10
5P15 H13
6P03 G13
7P01 A6
7P02 D10
7P12 H5
7P32 G6
9P0J G7
9P33 E9
BP1A F2
BP1B F1
BP1C F2
BP1D F1
BP1E F2
BP1F F1
BP1G F2
BP1H F2
BP1J A2
BP1K A2
BP1L A2
BP1M A2
BP1N A2
BP1P A2
BP1R B2
BP1S B2
BP1T B1
BP1U E1
BP1V G1
BP1W I1
BP5A C2
BP5B C2
BP5C C2
BP5D C2
BP5E D2
BP5F D2
BP5G D2
BP5H D2
BP5J H2
BP5K H2
BP5L H2
BP5M H2
BP5N I2
BP5P I2
BP5R I2
BP5S I2
FP03 F14
FP06 F1
FP07 F1
FP08 G1
FP09 G1
FP0A G1
FP0C G1
FP0E D1
FP0F D1
FP0G D2
FP0H D2
FP0J E1
FP0P D1
FP0R I1
14
Remark for service:
5P13
C
13
20
19
18
FP42 1V8-HDMI
2
OUT
+3V3
ARX1ARX0+
100n
BP1N
DC1R019WBER220
E
C
17
12
COM
2P48
ARX2ARX1+
BP1P
23 22
25 24
26
BP1T
BP1L
BP1M
FP14
11
3P58
BP1K
IN
+3V3
2P03
B
ARX2+
220u 16V
B
D
3
BP1J
3P61
C
10
9
16
15
RES
47K
A
8
14
13
7P01
LD1117DT18
HDMI CONNECTOR 3
1P04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FP10 21
12
11
7
HDMI
B
10
VDDH_1V8
1
A
5
4
22u 6.3V
2P47
2
VDDC_1V8
1
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
O
CHN
1X07
EMC HOLE
SETNAME
2
CLASS_NO
2008-11-21
UFD2K8
P
8204 000 8934
DIGI IO TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
8
SUPERS.
DATE
16
2007-10-18
130
C
17
4
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_537_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 123
SSB: HDMI Switch
1
2
2
1
A
5
4
3
3
6
4
5
10
9
8
7
6
7
11
8
13
12
1M96 D1
1P06 A1
2P04 A5
2P12 A5
2P23 E6
2P60 B1
3P15 C5
3P22 B5
3P28 B5
3P29 B6
3P30 B5
3P31 B5
3P32 C6
3P33 C4
3P35 C3
5P06 A5
6P06 D6
7P07 B4
7P17 C5
9P19 A6
9P20 A6
9P29-3 D2
9P29-4 D2
9P30-1 E2
9P30-2 E2
9P30-3 E2
9P30-4 E2
9P31-1 E2
9P31-2 E2
9P31-3 E2
9P31-4 E2
9P32-1 D1
9P32-2 D1
9P32-4 D1
BP50 A1
BP51 A2
BP52 A1
BP53 A2
BP54 A1
BP55 A1
BP56 B2
BP57 B1
BP5Z B1
FP00 B1
FP0B A4
FP30 B1
FP31 B1
FP32 B1
FP33 B1
FP34 B1
FP35 B5
FP36 D1
FP37 D2
FP38 D2
IP14 A6
IP15 A6
IP16 B5
IP20 C4
IP23 C5
IP28 B4
IP68 C6
9
HDMI SWITCH
D
BP55
120R
+5V-DDC
HDMIA-RX0HDMIA-RXC+
HDMIA-RXCPCEC-HDMI
FP33
HDMI 4
FP34
1
2
3
0
1
2
WC
ADR
SDA
3P33
ERX-HOTPLUG
6
5
F
G
E
H
22R
3P30
WRITE-PROT
IP23
3P32
7P17
BC847BW
IP68
HOT-PLUG-A
C
10K
3P15
3P35
D
3P31
IP20
EIN-5V
1M96
B
22R
1K0
22R
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
FP35
7
47K
IP16
SCL
DC1R019WBER220
HDMI CONNECTOR 4
E
EDID0
10K
Φ
(256x8)
EEPROM
EDID NVM
47K
EIN-5V
ERX-HOTPLUG
3P29
100n
7P07
M24C02-WDW6
3P28
IP28
ERX-DDC-SCL
ERX-DDC-SDA
FP32
23 22
25 24
26
BP5Z
HDMIA-RX1HDMIA-RX0+
A
DDCA-SDA
IP15
BP56
FP30
FP31
2P60
20
9P19
5P06
FP0B
3P22
BP57
ERX-DDC-SDA
DDCA-SCL
100n
BP54
HDMIA-RX2HDMIA-RX1+
2P12
BP53
9P20
100n
BP52
ERX-DDC-SCL
10K
B
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
BP51
HDMIA-RX2+
4
A
IP14
BP50
2P04
1P06
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FP00 19
21
8
B
RES
FP36
5
7
9P32-4
9P32-2
4
2
ERX-HOTPLUG
D
EIN-5V
FP37
9P29-4
9P29-3
5
6
4
3
6P06
ERX-DDC-SDA
ERX-DDC-SCL
EIN-5V
+5V-EDID
FP38
BAT54
8
9P32-1
1
PCEC-HDMI
1
2
3
4
1
2
3
4
9P30-1
9P30-2
9P30-3
9P30-4
9P31-1
9P31-2
9P31-3
9P31-4
8
7
6
5
8
7
6
5
2P23
HDMIA-RXCHDMIA-RXC+
HDMIA-RX0HDMIA-RX0+
HDMIA-RX1HDMIA-RX1+
HDMIA-RX2HDMIA-RX2+
100n
+5V-DDC
E
A
B
C
D
E
F
G
23 22
25 24
27 26
29 28
31 30
H
FI-RE21S-HF-R1500
1
2
4
3
5
6
7
8
9
I
I
CHN
SETNAME
2
CLASS_NO
2008-11-21
UFD2K8
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8934
DIGI I/O TV543 R2 LDIPNX
8
SUPERS.
DATE
9
130
8
2007-10-18
C
10
A3
5
ROYAL PHILIPS ELECTRONICS N.V. 2006
11
12
13
18310_538_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 124
SSB: PNX8543: Flash
2
1
4
3
6
5
9
8
7
10
11
13
12
14
17
16
15
19
18
20
A
A
1
2
3
5
4
6
7
9
8
11
10
12
13
PNX 8543 : FLASH
B
A
A
C
B
B
D
1M97 C12
2P13 C6
2P14 C7
3P37 C1
3P39-1 C3
3P39-2 C3
3P39-3 C3
3P39-4 D3
3P40-1 D3
3P40-2 D3
3P40-3 D3
3P40-4 D3
3P42 E3
3P44 D3
3P48-1 E3
3P48-2 E3
3P48-3 F3
3P48-4 F3
3P57 C11
5P09 B1
7P10 C5
IP24 E5
IP27 D5
IP29 B5
IP30 E4
B
C
D
IP29
+3V3-NAND
C
3P37
+3V3-NAND
Φ
XIO-SEL-NAND
PCI-AD24
PCI-AD25
PCI-AD26
PCI-AD27
PCI-AD28
PCI-AD29
PCI-AD30
PCI-AD31
F
3P39-1
3P39-2
3P39-3
3P39-4
3P40-1
3P40-2
3P40-3
3P40-4
1
2
3
4
1
2
3
4
8
7 100R
6 100R
5 100R
8 100R
7 100R
6 100R
5 100R
NAND-AD(0)
NAND-AD(1)
NAND-AD(2)
NAND-AD(3)
NAND-AD(4)
NAND-AD(5)
NAND-AD(6)
NAND-AD(7)
29
30
31
32
41
42
43
44
NAND-AD(0)
NAND-AD(1)
NAND-AD(2)
NAND-AD(3)
NAND-AD(4)
NAND-AD(5)
NAND-AD(6)
NAND-AD(7)
0
1
2
3
IO
4
5
6
7
NC
100R
D
3P44
XIO-ACK
+3V3-NAND
2K2
G
3P42
WP-NANDFLASH
+3V3-NAND
10K
NAND-CLE
NAND-ALE
XIO-SEL-NAND
IP27
NAND-REn
NAND-WEn
WP-NANDFLASH
XIO-ACK
16
17
9
8
18
19
7
IP24
IP30
E
CLE
ALE
CE
RE
WE
WP
R
B
PCI-AD0
PCI-AD1
PCI-CBE1
PCI-CBE2
3P48-1
3P48-2
3P48-3
3P48-4
1
2
3
4
8
7
6
5
100R
100R
100R
100n
1M97
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48
TSO-BIT-CLK
TSO-BIT-VALID
TSO-SYNC
TSINO-DATA0
TSINO-DATA1
TSINO-DATA2
TSINO-DATA3
TSINO-DATA4
TSINO-DATA5
TSINO-DATA6
TSINO-DATA7
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
3P57
10K
I2C-SCL
I2C-SDA
RESET-BOLT-ON
F
D
G
22 23
24 25
26 27
28 29
FI-RE21S-VF-R1300
E
36
VSS
13
H
VCC
[FLASH]
1G
10K
E
37
12
7P10
NAND01GW3B2BN6F
E
100n
2P13
+3V3-NAND
30R
2P14
5P09
+3V3
NAND-CLE
NAND-ALE
NAND-WEn
NAND-REn
100R
I
I
F
J
J
G
G
K
K
owner.
is prohibited without the written consent of the copyright
F
All rights reserved. Reproduction in whole or in parts
H
L
L
H
H
M
M
I
I
N
N
1
2
3
4
5
7
6
8
11
10
9
13
12
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
UFD 2K8
P
8204 000 8934
DIGI I/O TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
8
SUPERS.
DATE
16
2007-10-18
130
C
17
6
A2
ROYAL PHILIPS ELECTRONICS N.V. 2007
18
19
20
18310_539_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 125
SSB: Ethernet
1
2
4
3
5
7
6
9
8
10
12
11
13
14
15
16
17
19
18
20
A
A
1
2
3
4
5
6
7
8
ETHERNET
4
5
3
3N0N-3
22R
33R
3 3N0L-3 6
4 3N0N-4 5
22R
33R
1 3N0L-1 8
IN0P 3N0N-2
1 3N0N-1 8
7
2
33R
F
K
G
121
120
119
118
116
115
113
112
110
109
108
106
105
104
102
101
88
87
86
83
82
81
79
78
74
73
72
71
70
68
67
66
CMD/ BE
132
133
134
135
138
139
140
141
0
CFGDIS
0
EEDO
MD<0:7>
7
142
143
144
1
2
3
7
10
11
12
14
15
22
23
24
25
LEDACT
LED10LNK
LED100LNK
EEDI
EECLK
MA5
0
1
RXD
2
3
RXER
RXDV
0
1
TXD
2
3
AD<0:31>
DATA
100n
2
100R
100R
3N0T-2
7
8 3N0T-1 1
100R
5
128
IN0K
3N0W
E
1K0
RES
IN0W
3N0J
IN0Y
270R
6N00
IN0Z
BAS316
6N01
BAS316
FN0A
3N0K
IN10
FN0B
220R
F
50
RESERVED
127
E
F
G
H
I
J
K
G
L
C1
VSS
7N04-2
DP83816AVNG
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
220R
2N0V
34
36
37
42
43
+3V3-ET-ANA
84
85
124
125
126
H
1
114
136
103
90
77
57
65
55
52
51
49
44
38
35
32
26
20
16
8
IN0U
+3V3
100n
2N0N
2N1C
10u 6.3V
IN0N
19
5N07
M
D
31
L
H
C
+3V3-ET-DIG
220R
41
B
IN0L
5N06
+3V3
MA<0:15>
100n
I
PCI-AD0
PCI-AD1
PCI-AD2
PCI-AD3
PCI-AD4
PCI-AD5
PCI-AD6
PCI-AD7
PCI-AD8
PCI-AD9
PCI-AD10
PCI-AD11
PCI-AD12
PCI-AD13
PCI-AD14
PCI-AD15
PCI-AD16
PCI-AD17
PCI-AD18
PCI-AD19
PCI-AD20
PCI-AD21
PCI-AD22
PCI-AD23
PCI-AD24
PCI-AD25
PCI-AD26
PCI-AD27
PCI-AD28
PCI-AD29
PCI-AD30
PCI-AD31
100R
131
MWR
EESEL
0
1
2
3
100n
REGE
1
E
111
100
89
75
2N0Z
48
1u0
PCI-CBE0
PCI-CBE1
PCI-CBE2
PCI-CBE3
100n
+3V3-ET-ANA
2N0Y
2N0M FN0C
10K
H
129
130
100n
MRD
2N10
MCS
RST
D
2N11
REQ
IP0J
RESET-ETHERNET
13
30
TXE
100n
58
DEVSEL
31
2N12
62
RXOE
2N14 100n
64
RESET-ETHERNET
TXCLK
IDSEL
6
2N16 100n
PCI-REQ-ETH
STOP
NX5032GB
25M
4
2N15 100n
3N0Y
+3V3-ET-DIG
95
RXCLK
2N17 100n
PCI-DEVSEL
5
MDIO
GNT
1M0
1N02
2
D
76
100R
MDC
C
3N0V
100n
3N0G
PCI-AD23
SERR
FRAME
96
PCI-STOP
G
CRS
IN0M
100n
2N0P
63
PERR
29
4u7 6.3V
91
PCI-GNT-ETH
28
2N0Q
PCI-FRAME
40
COL
IN0T
470R
1N00 A11
1N02 C8
2N0K D8
2N0L D8
2N0M D3
2N0N H4
2N0P G10
2N0Q G10
2N0R A9
2N0S C8
2N0T B10
2N0U B9
2N0V H10
2N0W H10
2N0Y G12
2N0Z G13
2N10 G12
2N11 G12
2N12 G12
2N13 G11
2N14 G12
2N15 G11
2N16 G11
2N17 G11
2N1C H3
3N0F C7
3N0G D3
3N0H C7
3N0J E8
3N0K F8
3N0L-1 A8
3N0L-2 A9
3N0L-3 A8
3N0L-4 A8
3N0N-1 A9
3N0N-2 A9
3N0N-3 A9
3N0N-4 A9
3N0T-1 B9
3N0T-2 B9
3N0T-3 C9
3N0T-4 C9
3N0V C8
3N0W E8
3N0Y D1
5N06 G10
5N07 H10
6N00 F8
6N01 F8
7N04-1 B3
7N04-2 H7
BN0A A10
BN0B B10
BN0C B10
BN0D B10
FN05 A10
FN06 A10
FN07 B10
FN08 B11
FN09 C11
FN0A E9
FN0B F9
FN0C D3
FN15 B10
IN0K E7
IN0L G10
IN0M C7
IN0N H3
IN0P A9
IN0T C8
IN0U H10
IN0V C8
IN0W E7
IN0Y F7
IN0Z F7
IN10 F8
IP0H B10
IP0J D1
2
98
TRDY
100n
3N0F
18
VREF
IRDY
FN09
17
X1
X2
PAR
2N0S
IN0V
4u7
2N0W
PCI-SERR
45
3N0T-4
97
PCICLK
46
1840420-1
4
PCI-PERR
TPRDM
B
53
3 3N0T-3 6
93
13 14
ETHERNET CONNECTOR
22p
92
PCI-TRDY
TPRDP
INTA
IP0H
1
2
3
4
5
6
7
8
2N0K
PCI-IRDY
3VAUX
100n
54
TPTDP
TPTDM
2N0L
99
MacPhyter II
10/100 Mb/s
10K
F
60
PCI-PAR
FN08
2N0T
100n
3N0H
C
PCI-CLK-ETHERNET
1N00
BN0A
BN0B
BN0C
BN0D
2N0U
AUXVDD
PWRGOOD
61
IRQ-PCI
+3V3-ET-ANA
PCIVDD
PMEM
CLKRUN
122
E
22R
FN15
22p
59
7 3N0L-2 2
137
33
56
27
9
21
117
94
107
80
69
47
39
2N0R
33R
A
FN07
IAUXVDD
123
owner.
13
FN05
FN06
7N04-1
DP83816AVNG
B
is prohibited without the written consent of the copyright
12
6
+3V3-ET-ANA
D
All rights reserved. Reproduction in whole or in parts
11
2N13 100n
A
3N0L-4
22R
J
10
+3V3-ET-DIG
B
C
9
M
N
N
1
2
3
4
6
5
7
8
9
10
11
12
13
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
UFD 2K8
P
8204 000 8934
DIGI I/O TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
8
2007-10-18
130
C
17
7
A2
ROYAL PHILIPS ELECTRONICS N.V. 2007
18
19
20
18310_540_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 126
SSB: Buffering
1
2
3
1
4
2
3
6
5
4
8
7
5
9
6
11
10
7
8
13
12
9
2N30 D3
2N31 B5
2N32 D5
2N33 B3
2P18 E9
2P19 E9
2P20 D7
2P21 C8
2P22 C8
2P25 D8
2P26 E9
2P61 C7
2P62 C8
3N30 D1
3N31 B4
3N32 D4
3N33 E4
3N34 D2
3P46 C7
3P49 D6
3P50 D8
3P51 D8
3P52 E8
3P54 E8
5P10 C9
7N10 D2
7N11 B5
7N12 D5
7N13 B2
7P11 D9
7P13 D7
FP18 D7
FP19 D8
IN20 B4
IN21 D4
IN22 D2
IN30 D2
IN32 E4
IN34 B2
IN35 B2
IP31 D8
IP32 D8
10
A
BUFFERING
A
A
B
+3V3
10K
3N31
100n
17
16
15
14
13
12
11
PCMCIA-A6
PCMCIA-A5
PCMCIA-A4
PCMCIA-A3
PCMCIA-A2
PCMCIA-A1
PCMCIA-A0
+12V
E
C
7P11
PHD38N02LT
IP31
+3V3
E
19
PCI-AD14
2
PCI-AD13
PCI-AD12
PCI-AD11
PCI-AD10
PCI-AD9
PCI-AD8
3
4
5
6
7
8
9
3N33
F
1u0
RES
1u0
RES
R
10K RES
1
2
18
PCMCIA-A14
17
16
15
14
13
12
11
PCMCIA-A13
PCMCIA-A12
PCMCIA-A11
PCMCIA-A10
PCMCIA-A9
PCMCIA-A8
E
G
IN32
10
10K
F
H
F
1
I
2
3
E
1
K
3P52
2P19
CA-ADDEN
FP19
2
3EN1
3EN2
G3
D
D
IP32
22u 16V
2P18
CA-WE
CA-OE
CA-CE2
CA-CE1
CA-REG
CA-IORD
CA-IOWR
+5V-TUN
2P26
17
16
15
14
13
12
11
220p
2P25
10K
3N32
1
2
1K0
C
1K0
3
4
5
6
7
8
9
PCI-AD18
3P51
1K0
3P54
PCI-CBE1
PCI-CBE2
PCI-AD16
PCI-AD17
PCI-AD19
PCI-AD22
PCI-AD23
18
7N12
74LVC245A
1
3P50
A
2
IN21
FP18
B
3
CA-WAIT
7P13
TS2431
3EN1
3EN2
G3
10
G
19
22n
20
IN30
CA-ADDEN
100n
20
1
2P20
100n
74LVC245A
7N10
IN22
F
2N30
10K
D
10K
3N34
3N30
2N32
10K
3P49
3
1
+3V3
H
5P10
1
2
30R RES
3
4
5
6
7
8
9
PCMCIA-A7
2
PCI-AD6
PCI-AD5
PCI-AD4
PCI-AD3
PCI-AD2
PCI-AD1
PCI-AD0
+5V5-TUN
18
10
2
1u0
19
PCI-AD7
1u0
CA-ADDEN
2P22
PCI-AD25
PCI-AD27
PCI-AD28
PCI-AD29
PCI-AD30
PCI-AD31
PCI-AD24
2P21
PCI-AD26
17
16
15
14
13
12
11
2P62
18
220u 25V
1
2
100n
3EN1
3EN2
G3
2P61
3
4
5
6
7
8
9
10
C
2
PCMCIA-D1
PCMCIA-D3
PCMCIA-D4
PCMCIA-D5
PCMCIA-D6
PCMCIA-D7
PCMCIA-D0
7N11
74LVC245A
1
220u 25V
D
PCMCIA-D2
IN20
3EN1
3EN2
G3
2K2
19
2N31
3P46
IN35
CA-DATAEN
B
20
CA-DATADIR
20
7N13
74LVC245A
1
IN34
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C B
2N33
+3V3
A
4
5
6
7
8
C HN
9
10
I
SETNAME
2
CLASS_NO
2008-11-21
UFD 2K8
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8934
DIGI I/O TV543 R2 LDIPNX
8
SUPERS.
DATE
9
8
2007-10-18
130
C
10
8
A3
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_541_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 127
SSB: Analogue Externals A
1
2
3
1
4
6
5
3
2
8
7
5
4
10
9
6
12
11
7
8
13
9
15
14
10
17
16
12
11
18
13
19
14
A
ANALOGUE EXTERNALS A
100p
IE23
2E90
2E87
1n0
2E88
CDS4C12GTA
12V
1009
6E07
CDS4C12GTA
12V
1015
2E91
100p
2E04
100K
3E22
1n0
2E82
1025
6E14
CDS4C12GTA
12V
100p
RES 2E31
CDS4C12GTA
12V
100p
2E15
1E12
75R
RES
3E28
6E23
10
11
330p
12V
1001
11
FE80
2E18
8K2
10
12
13
12
IE16
17
RES
FE78
IE17
100p
6E26
75R
19
19
FE84
20
21
20
F
FE85
FE79
MTJ-505H-01 NI LF
21
1E16
G
100p
2E12
1E19
AV4-PR
6E28
9E26
9E27
75R
AV1-R
CDS4C12GTA
12V
MTJ-505H-01 NI LF
RES
3E54
CDS4C12GTA
12V
6E35
100p
2E19
75R
RES
3E55
9E19
AV5-PR
J
G
RES
9E20
AV1-BLK-BO
+3V3
+5V
100n
2E24
IE48
3
3E68
1E22
H
75R
10K
6E29
3E61
IE09
1
7E09
BC847BW
2
12V
3E43
AV1-BLK
10K
1E26
IE06
CDS4C12GTA
3E69
1
7E14
BC847BW
2
CDS4C12GTA
12V
IE51
CVBS-OUT-SC1
75R
IE92
390R
3EB7
H
4K7
3
AV2-BLK
7E05
BC847BW
3E44
2E13
4K7
3E73
IE91
100R
6E36
3EB6
100n
2E74
+3V3
* EU
100n 16V
K
L
9E25
AV4-Y
FE83
9E18
AV3-PR
owner.
4
3
6
5
8
7
10
9
100p
2E44
75R
1E25
1E23
6E30
1E24
CDS4C12GTA
12V
68R
2
1
O
68R
6E31
3EB8
N
I
3E45
CVBS-OUT-SC1
3E52
12V
IE93
7E04
BC847BW
12V
RES
3E59
6E32
1E27
100R
CDS4C12GTA
IE94
CDS4C12GTA
12V
6E37
100p
2E41
75R
RES
3E62
9E10
AV2-Y_CVBS
RES
2E73
3EB9
I
100n
+5V
CDS4C12GTA
AV1-CVBS
M
390R
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
FE77
9E33
F
18
9E24
AV1-G
17
2E14
16
18
I
E
16
15
1E18
FE76
CDS4C12GTA
12V
1E13
CDS4C12GTA
12V
6E34
100p
75R
7
9E17
AV5-Y
2E17
CVBS-TER-OUT
FE67
15
FE82
14
9E16
RES
3E38
AV3-Y
VSS VEE
8
14
FE81
13
3
5
9
4
RES
3E51
H
E
D
8
3E31
3K3
FE66
FE75
9
CDS4C12GTA
IE96
IE18
3E32
Y_CVBS-MON-OUT-SC
8
AV1-STATUS
FE65
7
* EU
9
12V
6E02
1028
3K3
3E17
2E33
8K2
9E23
AV4-PB
7
6
FE74
6E22
FE64
3E16
CDS4C12GTA
13
12
11
5
FE73
9E22
AV1-B
6
IE05
AV2-STATUS
3
4
5
FE63
C
2
FE72
CDS4C12GTA
12V
75R
RES 3E02
1027
6E24
100p
2E16
10K
+3V3
1
2
10
FE71
4
6
15
1E01
1
3
* EU
VDD
330p
100n
16
7E02
74HC4053PW
1
2
4X1
4X2
(AV1)
FE70
2
FE68
9E15
AV5-PB
2E75
3E06
IE97
2
G4
RES
1E02
9E12
AV3-PB
1
MDX
RES
(AV2)
IE14
REGIMBEAU_CVBS-SWITCH
F
SCART2
1
7E15
PDTC114EU
+5v
100K
RES 3E34
100n
2E77
8K2
3E99
3
IE98
SCART1
1K0
1K0
C
B
3E19
3E14
+5v
1E31
100p
100p
RES
AV1-AUDIO-L
IE21
AUDIO-IN2-L
* EU
14
1E00
100K
2E01
2E06
2E10
2E70
100K
RES
1024
6E12
CDS4C12GTA
12V
100p
2E32
100K
RES
A-PLOP
RES
3E30
470R
D
G
6E01
2E51
1n0
3E15
AP-SCART-OUT-L
FE62
3E64
470R
6E09
AP-SCART-OUT-L
1n0
4
BC847BS(COL)
1n0
6K8
B
IE04
CDS4C12GTA
12V
5
RES
1n0
IEC3
3EB0
1K0
RES
3E27
RES
3E07
AV1-AUDIO-R
1023
6E08
AP-SCART-OUT-R
CDS4C12GTA
12V
7E01-2 3
100p
RES
2E30
1u0 16V
FEA1
3E18
150R
100K
C
1K0
AUDIO-CL-R
IE22
FE61
3E11
2EA5
100K
IE20
AUDIO-IN2-R
IEC2
3EA8
D
A
1
BC847BS(COL)
E
1n0
1n0
RES
6E03
6K8
RES
CDS4C12GTA
12V
2
470R
3E12
RES
IEC1
3EA9
3E37
AP-SCART-OUT-R
1022
6E10
CDS4C12GTA
12V
100p
2E29
AP-SCART-OUT-L
100K
RES
FEA0
7E01-1 6
3E24
1u0 16V
2E50
470R
AUDIO-CL-L
150R
A
2EA4
3E21
B
FE60
3E63
AP-SCART-OUT-R
IEC0
3EA7
12
11
CHN
1X04
EMC HOLE
20
1001 E11
1009 B12
1015 C12
1022 A7
1023 B7
1024 B7
1025 C7
1027 D6
1028 E6
1E00 A12
1E01 C14
1E02 C8
1E12 D12
1E13 E7
1E16 F7
1E18 F12
1E19 G12
1E22 H13
1E23 I11
1E24 I7
1E25 I11
1E26 H7
1E27 I7
1E31 B12
2E01 A11
2E04 C11
2E06 B11
2E10 B11
2E12 G12
2E13 G6
2E14 F12
2E15 D12
2E16 D5
2E17 E6
2E18 E12
2E19 F6
2E24 H11
2E29 A5
2E30 B5
2E31 C5
2E32 B5
2E33 E5
2E41 I6
2E44 I12
2E50 A7
2E51 A7
2E70 B7
2E73 I2
2E74 G2
2E75 D1
2E77 C2
2E82 C7
2E87 A13
2E88 A12
2E90 B12
2E91 C12
2EA4 A3
2EA5 A3
3E02 D6
3E06 D4
3E07 A11
3E11 A6
3E12 A11
3E14 C6
3E15 B11
3E16 D6
3E17 E5
3E18 B5
3E19 C11
3E21 B5
3E22 C11
3E24 A5
3E27 B11
3E28 D11
3E30 B11
3E31 D11
3E32 E11
3E34 C5
3E37 A11
3E38 F11
3E43 H12
3E44 H11
3E45 I10
3E51 E5
3E52 I5
3E54 G11
3E55 F5
3E59 I11
3E61 H6
3E62 I6
3E63 A6
3E64 B6
3E68 H12
3E69 H6
3E73 G5
3E99 C2
3EA7 A3
3EA8 A3
3EA9 A2
3EB0 B2
3EB6 H1
3EB7 H2
3EB8 I2
3EB9 I1
6E01 A12
6E02 E6
6E03 B12
6E07 B12
6E08 B6
6E09 C12
6E10 A6
6E12 B6
6E14 C6
6E22 E12
6E23 D11
6E24 D6
6E26 F12
6E28 G12
6E29 H12
6E30 I11
6E31 I6
6E32 I11
6E34 E6
6E35 F6
6E36 H7
6E37 I6
7E01-1 A2
7E01-2 B2
7E02 D2
7E04 I1
7E05 H1
7E09 H11
7E14 H5
7E15 C3
9E10 I3
9E12 C5
9E15 D5
9E16 E5
9E17 E5
9E18 F5
9E19 F5
9E20 G10
9E22 D10
9E23 D10
9E24 E10
9E25 F10
9E26 G10
9E27 G10
9E33 F2
FE60 A7
FE61 A7
FE62 B7
FE63 D7
FE64 D7
FE65 E7
FE66 E7
FE67 E7
FE68 C7
FE70 C13
FE71 C13
FE72 C13
FE73 D13
FE74 D13
FE75 D13
FE76 E7
FE77 F7
FE78 F7
FE79 F7
FE80 D13
FE81 E13
FE82 E13
FE83 F13
FE84 F13
FE85 F13
FEA0 A3
FEA1 B3
IE04 D1
IE05 D5
IE06 H6
IE09 H11
IE14 C5
IE16 E5
IE17 F5
IE18 D10
IE20 A5
IE21 C5
IE22 A11
IE23 C11
IE48 H11
IE51 H5
IE91 H1
IE92 H2
IE93 I2
IE94 I1
IE96 E2
IE97 D3
IE98 C2
IEC0 A3
IEC1 A2
IEC2 A3
IEC3 B2
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
13
O
SETNAME
2
CLASS_NO
2008-11-21
ANA + SIDE I/O
P
8204 000 8930
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
4
2008-01-18
130
C
17
1
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_542_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 128
SSB: Analogue Externals B
1
2
5
4
3
2
1
7
6
3
4
8
6
5
9
11
10
7
14
13
10
12
8
9
15
16
11
18
14
17
13
12
19
20
V-SYNC-VGA
H-SYNC-VGA
B-VGA
6E05
100p
75R
RES
3E03
1241
75R
RES
3E01
1240
75R
RES
3E05
1016
BAT54
12V
CDS4C12GTA
2E65
6E53
CDS4C12GTA
12V
100p
FE52
+5V
6E54
A
B
1
2
3
0
1
2
7
WC
BAS321
4K7
6E17
47K
3E70
3E71
FEB2
9E29
WRITE-PROT
1
6
SCL
ADR
3E72
5
SDA
9E37
RES
4
100R
C
FE39
BAS321
6E16
100R
BAS321
3E65
CLK-SCL
FE26
IE32
(256×8)
EEPROM
4K7
6E13
BAS321
3E47
4u7
Φ
4K7
3E89
47p
2E64
4K7
3E35
6E11
7E18
M24C02-WDW6
6E15
FE38
12V
CDS4C12GTA
1242
47p
2E46
4K7
3E46
C
6E04
1012
E
12V
CDS4C12GTA
100R
100n
2E99
3E42
120R
4K7
FE16
3E90
D
FE19
8
FE13
IE10
5E05
+5VDCOUT
2E26
17
100R
EDID NVM VGA
3E82
B
FE55
100n
C
FE58
IE19
2ECF
VGA
CONNECTOR
2E11
16
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
100p
1E05
A
2EB4
1226-02B-15S-FAE-02
B
6E18
12V
CDS4C12GTA
R-VGA
ANALOGUE EXTERNALS B
G-VGA
A
FEB3
F
DATA-SDA
D
D
H
3E29
CDS4C12GTA
12V
V_NOM
3E60
2E49
100K
RES
FE40
E
IE27
CVBS-MON-OUT-CINCH
IE08
100p
5
3E53
RES
IE35
3E56
A-PLOP
2E28
100K
F
FE53
3E48
MSP-305H-BBB-732-03 NI
6
470R
3
RES
RES
4
7E10-2
BC847BS(COL)
5 1E04-1
RED
F
IE15
5E06
1E07
CON_JACK
FE59
+12V
+5V
4
BC847BPN(COL)
7E06-2
IE07
1
1
2
2E72
100p
RES
100K
3E98
100n
3EA1
100K
3EA2
1K0
IE61
1u0
I
3EA5
22K
3EB2
RES
3EA6
330R
470R
560R
3EB4
*AP
9E07
CVBS-MON-OUT-CINCH
RES
2E79
Y_CVBS-MON-OUT
4
3
AUDIO-IN3-R
1K0
12V
6E06
CDS4C12GTA
FE43
O
IE31
3E97
1250
1n0
2E93
1E10 1
1u0
2
3EB1
330R
7E16
BC847BW
2
IE13
9E28
IE38
3EB5
9E21
N
2E78
6
7E06-1
BC847BPN(COL)
1
3
10K
2E71
100p
RES
100K
3
RES
Y_CVBS-MON-OUT-SC
FE50
IE70
5
IE60
1K0
I
YKB11-3001V
2
H
IE89
100n
2E76
AUDIO-IN3-L
3E95
CDS4C12GTA
12V
6E38
1255
1E03-1 5
WHITE
1n0
2E92
M
IE29
3E96
33R
AV2-Y_CVBS
3EA3
220R
9E06
FE49
6E46
IE90
5E02
100n
27K
RES 2EB3
IE01
RES 3ED3
47R
*AP
MSP-305H-BBB-523-03 NI
6
1011
2E08
3E20
100n
IE02
+5V
1u0
9E01
7E03
BC847BW
2EB1
4K7
2E67
H
4K7
IE24
7 3E04-2 2
3E13
IE25
3 3E04-3 6
2E05
SPDIF-OUT
100n
3E92
100p
75R
RES
CDS4C12GTA
12V
AV4-PB
2E81
L
6E51
1246
owner.
1E03-3 1
BLUE
IE03
9E02
180R
10p
*EU
FE51
MSP-305H-BBB-523-03 NI
2
G
+3V3
AV1-Y_CVBS
2E52
K
1
YKB11-3004
FE41
100n
2E07
*AP
9E11
1 3E04-1 8
3E36
100p
2E68
AV4-PR
12p
IE26
9E00
4K7
FE42
RES 75R
CDS4C12GTA
12V
6E52
1235
1E03-2 3
RED
G
*EU
FE48
MSP-305H-BBB-523-03 NI
4
2E22
30R
J
2
CDS4C12GTA
12V
IE33
3E50
150R
1014
1u0
CDS4C12GTA
12V
V_NOM
IE34
2E34
AUDIO-OUT-R
1n0
AV4-Y
6E48
9E04
2E95
75R
RES 3E10
2E27
100p
*EU
6K8
All rights reserved. Reproduction in whole or in parts
RES
68R
6E40
12V
CDS4C12GTA
1013
V_NOM
1E04-3 1
GREEN
is prohibited without the written consent of the copyright
100p
1
7E10-1
BC847BS(COL)
3 1E04-2
WHITE
*AP
FE54
MSP-305H-BBB-732-03 NI
2
I
2
6K8
E
RES
IE62
3E58
MSP-305H-BBB-732-03 NI
4
1n0
6
A-PLOP
FE69
3E33
470R
150R
1026
IE68
3E25
1u0
6E47
IE57
2E21
AUDIO-OUT-L
2E96
G
5
6
7
8
10
9
11
12
CHN
13
1011 G12
1012 C4
1013 F3
1014 F11
1016 A4
1026 E11
1235 G3
1240 A5
1241 A6
1242 C5
1246 H3
1250 I3
1255 I3
1E03-1 I3
1E03-2 G3
1E03-3 H3
1E04-1 F11
1E04-2 E11
1E04-3 E3
1E05 A2
1E07 F14
1E10 I3
2E05 G8
2E07 G8
2E08 H11
2E11 A5
2E21 D8
2E22 G12
2E26 C10
2E27 F4
2E28 F9
2E34 F8
2E46 C5
2E49 E9
2E52 G8
2E64 C6
2E65 A6
2E67 H5
2E68 G5
2E71 I5
2E72 I5
2E76 I11
2E78 H14
2E79 I14
2E81 H12
2E92 I3
2E93 I3
2E95 F10
2E96 E10
2E99 C9
2EB1 H12
2EB3 H14
2EB4 A4
2ECF B3
3E01 B6
3E03 B7
3E04-1 G8
3E04-2 G8
3E04-3 H8
3E05 A4
3E10 F4
3E13 H9
3E20 H10
3E25 D9
3E29 E5
3E33 D10
3E35 C6
3E36 G4
3E42 B7
3E46 C5
3E47 C11
3E48 F10
3E50 F9
3E53 F10
3E56 F8
3E58 E8
3E60 E10
3E65 C12
3E70 B13
3E71 B13
3E72 C13
3E82 B7
3E89 C7
3E90 B8
3E92 H4
3E95 I5
3E96 I4
3E97 I4
3E98 I5
3EA1 H14
3EA2 H13
3EA3 H13
3EA5 I14
3EA6 I13
3EB1 I13
3EB2 I13
3EB4 I11
3EB5 I12
3ED3 H14
5E02 H12
5E05 B10
5E06 F12
6E04 C4
6E05 A7
6E06 I4
6E11 C6
6E13 C10
6E15 C11
6E16 C13
6E17 B14
6E18 A4
6E38 I4
6E40 F4
6E46 G13
6E47 E10
6E48 F10
6E51 H4
6E52 G4
6E53 A5
6E54 A3
7E03 H9
7E06-1 I13
7E06-2 I13
7E10-1 E9
7E10-2 F9
7E16 I11
7E18 B12
9E00 G5
9E01 H5
9E02 H5
9E04 F5
9E06 H9
9E07 I8
9E11 G5
9E21 I12
9E28 I8
9E29 C14
9E37 C14
FE13 B4
FE16 B6
FE19 B9
FE26 C10
FE38 C4
FE39 C12
FE40 E11
FE41 G14
FE42 G3
FE43 I3
FE48 G4
FE49 I3
FE50 I3
FE51 G4
FE52 A6
FE53 F10
FE54 E3
FE55 A5
FE58 A4
FE59 F13
FE69 D10
FEB2 C13
FEB3 D13
IE01 H10
IE02 H9
IE03 G5
IE07 I12
IE08 F5
IE10 B12
IE13 I9
IE15 F11
IE19 A2
IE24 G8
IE25 G8
IE26 G5
IE27 E5
IE29 I5
IE31 I5
IE32 C13
IE33 F9
IE34 F8
IE35 F9
IE38 I12
IE57 D8
IE60 I14
IE61 I14
IE62 E9
IE68 D9
IE70 H13
IE89 H13
IE90 H13
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
SETNAME
2
CLASS_NO
2008-11-21
ANA + SIDE I/O
P
8204 000 8930
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
SUPERS.
DATE
16
4
2008-01-18
130
C
17
2
A2
ROYAL PHILIPS ELECTRONICS N.V. 2005
18
19
20
18310_543_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 129
SSB: Analogue Externals C
1
2
3
1
4
5
2
A
5
10
9
6
7
8
13
12
9
B
1E14
75R
100p
FE87
FE88
FE86
B
FE89
AUDIO-IN5-R
BE21
AUDIO-HDPH-L-AP
2
1005
V_NOM
CVBS
1M36
FE98
AUDIO-HDPH-R-AP
1E11-1 1
YELLOW
1
2
3
4
5
6
7
8
9
10
11
IE58
D
BE23
FE22
3E81
C
100p
2E97
100K
3E76
1n0
TO SIDE I/O
C
B11B-PH-K
5E00
FE90
RES
RES
30R
100p
2E57
E
2E42
6E21
1004
V_NOM
5
6
1E11-2 4
WHITE
CDS4C12GTA
12V
1K0
LEFT
AUDIO-IN5-L
AUDIO-IN5-R
100R
100p
2E56
75R
RES
3E75
FRONT-C
AUDIO-IN5-L
100R
3EC0
100p
2E55
100p
RES
3E74
12V
2E53
FE21
FRONT-Y_CVBS
3EC1
FRONT-Y_CVBS
12V
BE22
MDC-013V1-B
CDS4C12GTA
1
100p
FE20
1006
V_NOM
3
FRONT-C
9E14
2E54
C
A
9E13
Y/CVBS
6E41
4
5
RESERVED
BE20
FE56
2E36
SVHS IN
CDS4C12GTA
6E20
100p
1007
2E35
V_NOM
2
RIGHT
8
9
7
RES
RES
D
100p
2E58
30R
100u 4V
2E45
100p
2E98
100K
1n0
2E37
1K0
100u 4V
CDS4C12GTA
12V
2E80
IE72
3E78
E
E
FOR ITV
5
4
2
FE24
LEFT
FE18 9E34
RIGHT
FOR ITV
2
8
3E26-2
IE67
33R
1n0
1K0
2E40
6E44
1010
V_NOM
BE27
1n0
7
33R
3E26-3
3
6
FE25
CDS4C12GTA
12V
3E80
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1K0
2E39
F
3E26-1
33R
CDS4C12GTA
12V
3E79
H
1
6E45
3
7 BE28
8
1
MSJ-035-10A B AG PPO
IE66
RC-OUT
1000
V_NOM
HEADPHONE
1E15
V_NOM
RC-IN
1002
G
6E43
F
FE23
3E77
BE24
BE25
FE17
V_NOM
1E11-3
RED
1003
D
5E01
FE91
9E32
owner.
11
ANALOGUE EXTERNALS C
B
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
8
7
4
3
A
C
6
F
4 3E26-4 5
33R
I
1
2
3
4
5
6
7
CHN
8
1000 F3
1002 E2
1003 D3
1004 C2
1005 B2
1006 B3
1007 A3
1010 F4
1E11-1 C1
1E11-2 C2
1E11-3 D2
1E14 B1
1E15 E2
1M36 B8
2E35 A3
2E36 B3
2E37 D3
2E39 F4
2E40 F5
2E42 C3
2E45 D5
2E53 A7
2E54 A7
2E55 B7
2E56 B8
2E57 D8
2E58 D8
2E80 D5
2E97 C4
2E98 D4
3E26-1 E5
3E26-2 F5
3E26-3 F5
3E26-4 F5
3E74 A4
3E75 B4
3E76 C4
3E77 D4
3E78 D4
3E79 F3
3E80 F4
3E81 C4
3EC0 B8
3EC1 A8
5E00 C8
5E01 D8
6E20 A3
6E21 C3
6E41 B3
6E43 D3
6E44 F4
6E45 F3
9E13 A8
9E14 A8
9E32 F2
9E34 F3
BE20 A3
BE21 B2
BE22 B2
BE23 C3
BE24 D2
BE25 D2
BE26 F3
BE27 F4
BE28 F2
FE17 D2
FE18 F2
FE20 B2
FE21 B2
FE22 C3
FE23 D3
FE24 F3
FE25 F5
FE56 A2
FE86 B7
FE87 B7
FE88 B7
FE89 B8
FE90 C8
FE91 D7
FE98 B8
IE58 C4
IE66 E5
IE67 F5
IE72 D5
A
B
C
D
E
F
G
H
I
9
SETNAME
2
CLASS_NO
2008-11-21
ANA + SIDE I/O
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8930
TV543 R2 LDIPNX
8
SUPERS.
DATE
9
130
4
2008-01-18
C
10
A3
3
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_544_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 130
SSB: Analogue Externals D
4
3
6
5
ANALOGUE EXTERNAL D
9E31
100n
2
X1
7
7E19-2
74HC4066
4
3ECN
1
1
5
7
100R
1
6
9
7E19-4
74HC4066
11
1
3ECM
+3V3-STANDBY
7EA1
ADG734BRU
10
7
9E09
V+
IEA3
BO-B
2EA3
4u7
IEA4
AV1-B
2EAP
4u7
IEA5 BEB6
9
BO-G
2EAQ
4u7
IEA6
8
AV1-G
2EA6
4u7
IEA7
7
T1
T2
R1
IN
R2
OUT
R1
R2
14
7
BEB1
FE93
BEB2 FE94
12
9
6
FE44
5
1
2
3
4
BEB0
5
UP
4
1
2
3
MIPS
USE ONLY
3
3ECQ-3
3ECQ-1
8
FE14
100R
47K
47K
3EAC
3EAB
47K
IE99
3EC9
2EB6
AV1-CVBS
47K
4u7
D
AV1-PB
2EAC
1u0
IEB1
1
2EAD
1u0
IEB0
7EA3
74HC4053PW
IEC5
MDX
2
G4
13
12
11
33K
3ECQ-2
BO-AUDIO-L
3
AV1-AUDIO-L
1
3ECS-3
33K
100n
VDD
14
AUDIO-IN1-R
1
2
10
15
AUDIO-IN1-L
3
5
9
4
1
2
4X1
4X2
7
SERVICE
CONNECTOR
4 3ECS-4 5
UART
E
2EAB
FE57
1008
1029
FE97
6
IEC6
2EAE
1u0
IEB5
8
IEC7
2EAF
1u0
IEB4
F
VEE VSS
33K
3ECS-1
100R
AV1-CVBS
100p
2E25
100p
2E38
MHP-SWITCH
+3V3
3E88
MHP-SWITCH
10K
AV1-AUDIO-R
9EA4
IEC8
AUDIO-IN1-R
AV1-AUDIO-L
9EA5
IEC9
AUDIO-IN1-L
G
FOR MHP BOLT-ON
3E57
100R
100R
FE34
BOLT-ON-IO
3E87
BOLT-ON-IO
STANDBY
3E39
100p
2E20
100p
2E09
100p
2E03
M
+3V3
10K
CVBS-TER-OUT
RES
10K
I
FE29
SCL 1
BOLT-ON-IO
RXD-UP
TXD-UP
AV1-BLK
IED0SPDIF-IN1
FEA8
3ECE
FEB1
3EAY
3EAZ
FEA9
FEB0
H
68R
IED1
IED2
1K0
1K0
BO-AUDIO-L
BO-AUDIO-R
FEB5
BO-CVBS
FEB6
FEB7
FEB8
BO-R
BO-G
BO-B
15 16
SCL-SSB
FE27
2
SDA 3 4
3E85
100R
100R
100R
100R
9E30
BM14B-SRSS-TBT
1HP0
3ECF
3ECG
3ECH
I
100p
3E86
100R
FEA5
FEA6
FEA7
100p
RES 2EAN
FEB4
100R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RES 2EAM
3E83
SCL-BOLT-ON
SDA-BOLT-ON
RC-UP
1n0
3E84
1n0
2EAL
100R
2EAK
3E23
22p
5E03
IE12 FE33 30R
IE11
+3V3-STANDBY
1R12
RXD-UP
TXD-UP
100p
RES 2ECD
100R
100p
RES 2ECC
3E09
FE35
RES 2ECB
FE36
B10P-PH-K-S
N
15
FE37
1
2
3
4
5
6
7
8
9
10
H
AV1-Y_CVBS
47K
GND VSS
33K
1E06
AV1-AUDIO-L
AV1-AUDIO-R
3E00
IE95
10 11
1R08
L
3E67
FE30
17
7
FE10
4u7
3EB3
18
BO-CVBS
IEA8
IEC4
1
AV1-B
AV1-G
AV1-R
AV1-BLK-BO
FE11
FE31
6E27
6E25
FE12
K
owner.
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
TO ITV BOLT - ON MODULE
BZX384-C5V1
100R
BZX384-C5V1
3E41
FE15
6
33K
2
3
F
G
NC
BEB5
C
2ECE
+3V3
DEBUG
7 3ECS-2 2
IE76
S4B
47K
19
6
FE96
FE32
S2B
9E40
3E91
RXD
D4
FOR
BO-AUDIO-R
100R
J
S4A
D2
IE78
AV1-PR
AV1-AUDIO-R
1
2
3
4
5
6
7
8
9
S2A
3EAT
20
BEB4
B3B-PH-SM4-TBT(LF)
1R07
IN4
AV1-Y
47K
SHIFTED
1E51
BEB3
FE45
LEVEL
1E50
FE92
9E41
I
IN2
13
14
16
OUT
IE84
IE75
10
S3B
8
T1
IN
T2
9E05
TXD
BEB7
S1B
12
3ED1
B4B-PH-SM4-TBT(LF)
E
FEC0
3EAA
100n 2E61
47K
2E60
15
RXD-UP
4
D3
11
100n
RXD-MIPS
H
BEB8
6
2
C2+
13
8
IE82
TXD-MIPS
6
C2-
11
10
9E03
47K
4u7
D1
33K
FEB9
TXD-UP
47K
2EA2
3
S3A
33K
G
RS232
V-
5
3EC5
AV1-R
S1A
TXD
VCC
C1-
4
100n
47K
IEA2
MHP-SWITCH
33K
2E63
3EC4
4u7
4 3ECQ-4 5
D
C1+
3
3EC3
2EA1
3EC8
1
100n
47K
BO-R
3EC6
2E62
2
16
Φ
GND
F
BEB9
RXD
9E36
TXD-MIPS
47K
3ED2
9E35
100n
SWITCH
IN1
IN3
1
RXD-MIPS
FE99
PMEG1020EA
B
10u
Φ
SPDT
+3V3
7E17
ST3232C
2EAA
VDD
TXD-MIPS
6E50
DEBUG / RS232 INTERFACE
A
+5V
IEA1
RES
RES
RES
9E08
PMEG1020EA
3E40
AV1-Y_CVBS
+3V3-STANDBY
+3V3
C
AV1-PR
9EA7
RES
6E19
E
9EA3
AV1-CVBS
X1
7E20
PDTC114EU
100R
10K
UART-SWITCH
1008 F5
1029 F5
1E06 F6
1E50 D6
1E51 E6
1HP0 I1
1R07 F1
1R08 H1
1R12 H9
2E03 I1
2E09 I2
2E20 I2
2E25 G2
2E38 G2
2E60 D3
2E61 D4
2E62 D2
2E63 D2
2EA1 C8
2EA2 C8
2EA3 C8
2EA6 D8
2EA9 B11
2EAA B11
2EAB E11
2EAC E9
2EAD E9
2EAE F9
2EAF G9
2EAK I10
2EAL I10
2EAM I11
2EAN I11
2EAP C8
2EAQ D8
2EB6 D12
2ECB I9
2ECC I9
2ECD I9
2ECE C12
2ECH A5
3E00 G3
3E08 C2
3E09 H2
3E23 H2
3E39 I5
3E40 C2
3E41 F2
3E57 H3
3E67 G2
3E83 H3
3E84 H3
3E85 I2
3E86 H3
3E87 H5
3E88 G14
3E91 F2
3E93 I2
3EAA D9
3EAB D9
3EAC D9
3EAT C12
3EAV C8
3EAY H10
3EAZ H10
3EB3 C12
3EC2 C9
3EC3 C9
3EC4 C9
3EC5 C9
3EC6 D8
3EC7 D8
3EC8 D9
3EC9 D12
3ECE H11
3ECF H10
3ECG H10
3ECH H10
3ECK A1
3ECL A2
3ECM B3
3ECN B1
3ECP B1
3ECQ-1 E8
3ECQ-2 F9
3ECQ-3 E9
3ECQ-4 E9
3ECS-1 G8
3ECS-2 G9
3ECS-3 F8
3ECS-4 F9
3ED1 D12
3ED2 C8
5E03 H1
5EA1 B10
6E19 C3
6E25 F3
6E27 F4
6E50 C3
7E17 D2
7E19-1 A3
7E19-2 A4
7E19-3 B5
7E19-4 B5
7E20 C3
7EA1 B10
7EA3 E11
9E03 D2
9E05 E1
9E08 C3
9E09 C4
9E30 H11
2EA9
1
12
IE81
3E08
AV1-R
TXD-UP
10K
FE47
AV1-Y
3EC2
FE95
UART-SWITCHn
20
14
X1
7
D
AV1-PB
9EA2
FOR MHP BOLT-ON
RXD-MIPS
7E19-3
74HC4066
8
1
3ECP
TXD
19
X1
100R
B
3
9EA1
AV1-G
47K
UART-SWITCHn
13
AV1-B
30R
1
RXD-UP
47K
C
12
18
+3V3-STANDBY
2ECH
5EA1
13
IE79
1
100R
17
16
15
11
16
3ECL
10
9
14
100R
UART-SWITCH
8
14
14
7E19-1
74HC4066
1
3ECK
RXD
14
A
7
13
12
HOTEL TV
14
B
11
10
9
5
2
8
7
6
47K
1
A
5
4
3EAV
3
2
3EC7
1
SDA-SSB
5
FE28
1
100R
3E93
2
3
4
5
6
7
8
9
10
11
13
12
9E31 A6
9E35 C6
9E36 C6
9E40 F3
9E41 E3
9EA1 A11
9EA2 A11
9EA3 A11
9EA4 G11
9EA5 G11
9EA7 A11
BEB0 E5
BEB1 D5
BEB2 E5
BEB3 E5
BEB4 D10
BEB5 D10
BEB6 C10
BEB7 C10
BEB8 C10
BEB9 C10
FE10 G2
FE11 G1
FE12 F1
FE14 G2
FE15 G1
FE27 I2
FE28 I1
FE29 I2
FE30 G2
FE31 G2
FE32 G1
FE33 H1
FE34 H2
FE35 H2
FE36 H1
FE37 H1
FE44 E5
FE45 E5
FE47 C1
FE57 F5
FE92 D5
FE93 E5
FE94 E5
FE95 B1
FE96 F4
FE97 F4
FE99 C3
FEA5 H10
FEA6 H10
FEA7 H10
FEA8 H10
FEA9 H10
FEB0 H10
FEB1 H9
FEB4 H2
FEB5 I10
FEB6 I10
FEB7 I10
FEB8 I10
FEB9 D1
FEC0 E1
IE11 H1
IE12 H1
IE75 F1
IE76 F1
IE78 C12
IE79 A4
IE81 C2
IE82 E2
IE84 E2
IE95 C12
IE99 D12
IEA1 B10
IEA2 C10
IEA3 C10
IEA4 C10
IEA5 C10
IEA6 C10
IEA7 D10
IEA8 E11
IEB0 E10
IEB1 E10
IEB4 G10
IEB5 F10
IEC4 E9
IEC5 E9
IEC6 F9
IEC7 G9
IEC8 G12
IEC9 G12
IED0 H12
IED1 H11
IED2 H11
A
B
C
D
E
F
G
H
I
J
K
L
M
N
14
O
O
CHN
SETNAME
2
CLASS_NO
2008-11-21
ANA + SIDE I/O
P
8204 000 8930
TV543 R2 LDIPNX
2008-10-10
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
3
15
4
SUPERS.
DATE
16
2008-01-18
130
C
17
4
A2
ROYAL PHILIPS ELECTRONICS N.V. 2007
18
19
20
18310_545_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 131
SSB: Mini PCI Connector
2
3
5
4
6
7
MINI PCI CONNECTOR
+3V3-mPCI
B
D
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
C
E
C
F
D
G
E
H
13
9
5A01
FA37
+5V-mPCI
2A50
100n
100n
2A09
100n
2A08
100n
2A07
100n
2A06
100n
2A05
100n
2A04
100n
2A03
2A02
30R
ROW_B
ROW_A
1A01-A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
8
+5V
1u0
330u 6.3V
2A01
RES 2A00
A
12
RES
+3V3
B
11
IA28
5A00
30R
10
9
100n
1
8
7
100n
2A52
A
6
5
4
3
1u0
2
2A51
1
A
1A01-B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
IA29
IRQB-mPCI
+3V3-mPCI
9A00
RES
IRQ-PCI
PCI-CLK-MINI
PCI-REQ-MINI
+3V3-mPCI
PCI-AD31
PCI-AD29
PCI-AD27
PCI-AD25
PCI-CBE3
PCI-AD23
PCI-AD21
PCI-AD19
PCI-AD17
PCI-CBE2
PCI-IRDY
IA30
+3V3-mPCI
PCI-CLKRUN
PCI-SERR
3A01
PCI-CLKRUN
10K
PCI-PERR
PCI-CBE1
PCI-AD14
PCI-AD12
PCI-AD10
PCI-AD8
PCI-AD7
+3V3-mPCI
PCI-AD5
PCI-AD3
+5V-mPCI
PCI-AD1
FA30
FA31
FA32
FA33
126
+5V-mPCI
IA27
9A01
IRQ-PCI
IRQA-mPCI
IA26
RESET-mPCI
9A02
RESET-mPCI
RESET-ETHERNET
B
+3V3-mPCI
PCI-GNT-MINI
IA20
PME
3A02
PME
+3V3-mPCI
10K
PCI-AD30
+3V3-mPCI
PCI-AD28
PCI-AD26
PCI-AD24
IDSEL
PCI-AD22
PCI-AD20
PCI-PAR
PCI-AD18
PCI-AD16
C
PCI-FRAME
PCI-TRDY
PCI-STOP
+3V3-mPCI
PCI-DEVSEL
PCI-AD15
PCI-AD13
PCI-AD11
IA21
3A04
PCI-AD9
PCI-CBE0
IA22
100R RES
IA23
3A03 RES
PCI-AD12
+3V3-mPCI
PCI-AD6
PCI-AD4
PCI-AD2
PCI-AD0
IDSEL
3A05
PCI-AD13
PCI-AD11
A
1A01-A A1
1A01-B A6
2A00 A3
2A01 A3
2A02 A3
2A03 A3
2A04 A4
2A05 A4
2A06 A4
2A07 A4
2A08 A5
2A09 A5
2A50 A7
2A51 A7
2A52 A8
3A00 E9
3A01 C4
3A02 B9
3A03 D9
3A04 D9
3A05 D9
3A06 E9
5A00 A2
5A01 A7
9A00 B3
9A01 B7
9A02 B9
FA30 E1
FA31 E2
FA32 E1
FA33 E1
FA34 E6
FA35 E6
FA36 E6
FA37 A8
IA20 B9
IA21 D9
IA22 D9
IA23 D9
IA24 E9
IA25 E9
IA26 B7
IA27 B7
IA28 A3
IA29 B2
IA30 C4
B
C
D
E
F
100R
D
100R
IA24
G
3A00
M66EN
M66EN
10K
FA34
FA35
E
FA36
MPCIACT
3A06
MPCIACT
IA25
H
+3V3-mPCI
10K
125
1734065-3
1734065-3
1
I
2
3
5
4
6
1X09
REF EMC HOLE
7
CHN
8
9
I
SETNAME
2
CLASS_NO
2008-11-21
MINI PCI
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8935
TV543 R2 LDIPNX
8
SUPERS.
DATE
9
2
2007-10-16
130
C
10
1
A3
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_546_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 132
SSB: DDR Supply
1
2
3
1
A
5
4
2
6
3
8
7
4
5
9
6
7
DDR SUPPLY
12
+3V3F
3A12
1K0
2A19
2A21
1u0
IA04
B
1K0
3A17
1K0
1u0
2A26
2A25
1
1n0
2A20
10K
IA01
3A10
IA05
FA01
330p
A
3A13
22R
2
3
A
2
2
IA03
3
3
8
IA02
1
3A11
C
470R
K
3A09
FA04
R
7A07
TS2431
7A01
PHD38N02LT
7A00-1
LM833
4
1
+V-LM833
100n
3A08
+2V5-REF
RES 470R
2K2
3A27
2K2
3A26
+12V
A
3A14
IA10
+V-LM833
+12V
2A27
1u0
2A14
1u0
2A13
3A15
4K7
3A07
3A21
+12V
22K
D
B
+2V5
1K0
RES 22u 6.3V
IA06
RES
C
RES
3A23
1K0
1K0 1%
RES
NC
1
3A22
IA07
3A25
RES
3A24
2K2 1%
4
NC
2
5
D
A
F
RES
7A03
TS431AILT
REF
K
3
22n
330p
RES
FA06
2A16
RES
2A15
RES
22K
4K7
3A20
C
100n
2A22
+3V3F
RES
D
+V-LM833
1n0
IA11
1u0
SS24
6A01
1K0
E
3A18
FA03
+1V8-PNX85XX
1K0
2AC0
22u 6.3V
5AC4
5AC2 30R
30R
1
2
3
RES
2A30
+3V3-STANDBY
FAC0
IAC3
1u0
10R
30R
IA12
2A23
H
1M01
IAC2
IAC4
IA13
2A24
5AC1
3AC0
KEYBOARD
3A16
E
22R
IA09
330p
2A12
2A11
4
RES 100n
FA02
1u0
2A29
3A19
7
6
G
2A28
7A00-2
LM833
1u0
5
IA08
8
7A02
PHD38N02LT
2A10
owner.
10R
E
100p
1
I
2
3
4
5
6
7
CHN
13
1M01 E3
2A10 E3
2A11 E5
2A12 E5
2A13 B6
2A14 B6
2A15 C4
2A16 C4
2A19 A5
2A20 A4
2A21 B5
2A22 C1
2A23 E6
2A24 E6
2A25 A7
2A26 A7
2A27 B7
2A28 D7
2A29 D7
2A30 E7
2AC0 E1
3A07 C1
3A08 A3
3A09 A3
3A10 B3
3A11 A3
3A12 A4
3A13 A6
3A14 B5
3A15 B5
3A16 E5
3A17 B5
3A18 E6
3A19 D6
3A20 C3
3A21 C3
3A22 C4
3A23 C5
3A24 D4
3A25 D4
3A26 A1
3A27 A1
3AC0 E1
5AC1 E2
5AC2 E2
5AC4 E3
6A01 E7
7A00-1 A5
7A00-2 D5
7A01 A6
7A02 D7
7A03 D3
7A07 A1
FA01 A6
FA02 E6
FA03 E6
FA04 A1
FA06 C4
FAC0 E3
IA01 B3
IA02 A4
IA03 A5
IA04 B5
IA05 A6
IA06 B5
IA07 D4
IA08 D3
IA09 E5
IA10 C1
IA11 E5
IA12 E7
8
+2V5-REF
B
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
11
10
IA13 E6
IAC2 E3
IAC3 E3
IAC4 E1
A
B
C
D
E
F
G
H
8
I
SETNAME
2
CLASS_NO
2008-11-21
MINI PCI
J
2008-10-10
3
NAME Maelegheer Ingrid
CHECK
1
2
3
4
5
7
6
J
8204 000 8935
TV543 R2 LDIPNX
8
SUPERS.
DATE
9
130
2
2008-01-18
C
10
A3
2
ROYAL PHILIPS ELECTRONICS N.V. 2008
11
12
13
18310_547_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 133
SSB: Audio
1
2
4
3
1
2
A
6
5
3
4
5
6
7
8
7D03-1
BC847BS(COL)
+AUDIO-POWER
4R7
GND-AUDIO
A
GND-AUDIO
A
2D19
220n
25V 220u
2D08
2D31
220R
5D08
220u 25V
2D07
25V 220u
220R
220u 25V
2D20
5D07
GND-AUDIO
ID27
ID28
1
2D26
2D22
220n
3D14-1
220n
8
7
3D14-2
15K
3
2
15K
3D14-4
15K
4
B
B
ID36
-AUDIO-R
2D24
ID19
7D10-1
TPA3120D2PWP
1
3
10
12
19
20
47n
L
R
AVCC
6
D
ID16
+AUDIO-L
2D23
ID18
47n
18
17
GND-AUDIO
2D16
1u0
3D06-2
22u
ID05
220R
ID07
5D04
VCLAMP
BYPASS
MUTE
SD
RIGHT-SPEAKER
LEFT-SPEAKER
C
220R
25V 220u
2D15
220n
25V 220u
PGND
AGND
3
ID38
L
R
GND_HS
2D27
2D21
220n
6
8
3D10-1
220n
D
1
ID33
100K
3D10-2
15K
CD10
2
4
8
7
5
7
100K
3D06-1
2D09
3D10-3
15K
1
ID31
5D05
25V 220u ID08
2D11
3
D
21
BSL
ID06
25V 220u
2D12
5D01
ID09
5
2
22
L
3D10-4
15K
100K 4
22u
4
5
ID37
2
4K7
OUT
0
GAIN
1
5D02
ID10
220n
15
R
15K
3D06-4 FD07
LEFT-SPEAKER
1
AUDIO-MUTE
A-STBY
16
BSR
2D10
ID32
25
7D03-2
BC847BS(COL)
ID30
L
8
9
E
11
7
4
2
IN
13
14
A-STBY
ID29
1u0
2D17
3D17
5
Φ
CLASS-D
AUDIO AMP
R
2D18
PVCC
23
24
C
GND-AUDIO
GND-AUDIO
37
36
35
34
GND-AUDIO
LEFT-SPEAKER
GND-AUDIO
3D11-4
4
3D03
100R
2D01
3
1
2
3
1735
GND-AUDIO
1735446-3
220R
2D25
FD02
GND-A
2D13
1K5
1
2
3
4
1735446-4
2
7
1K5
8
3D11-2
3D11-1
GND-AUDIO
1
1D54
V_NOM
F
V_NOM
1D53
GND-AUDIO
GND-AUDIO
FD05
FD06
5D09
F
2n2
RIGHT-SPEAKER
1D52
GND-AUDIO
V_NOM
GND-A
V_NOM
10n
H
E
1D38
LEFT-SPEAKER
10n
1D51
E
5
VIA
2n2
VIA
V_NOM
VIA
2D14
VIA
VIA
1D50
GND-AUDIO
26
27
28
29
1K5
GND-AUDIO
6
10u
GND-AUDIO
1K5
100K
7D10-2
TPA3120D2PWP
3D11-3
RIGHT-SPEAKER
2D02
6 3D06-3 3
40
39
38
F
30
31
32
33
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
6
5
220n
3D14-3
15K
ID12
2D05
22K
10u 35V
ID11
220n
3D16
2D06
2
2D30
B
G
1735 E9
1D38 E6
1D50 E9
1D51 F8
1D52 F9
1D53 F5
1D54 F6
2D01 E2
2D02 D2
2D05 A4
2D06 A5
2D07 A5
2D08 A7
2D09 C7
2D10 C7
2D11 C8
2D12 C8
2D13 F9
2D14 E9
2D15 C8
2D16 C4
2D17 C4
2D18 B8
2D19 A7
2D20 A5
2D21 D8
2D22 B8
2D23 C4
2D24 B4
2D25 F8
2D26 B8
2D27 D8
2D30 A5
2D31 A6
3D03 E2
3D06-1 D2
3D06-2 D2
3D06-3 D2
3D06-4 D2
3D09 A3
3D10-1 D8
3D10-2 D8
3D10-3 D7
3D10-4 D7
3D11-1 F7
3D11-2 F8
3D11-3 E8
3D11-4 E7
3D14-1 B8
3D14-2 B8
3D14-3 B8
3D14-4 B7
3D16 A4
3D17 C4
5D01 C7
5D02 C7
5D04 C9
5D05 C9
5D07 A6
5D08 A6
5D09 F8
7D03-1 A4
7D03-2 C2
7D10-1 B6
7D10-2 D3
CD10 D5
FD02 F9
FD05 E9
FD06 F9
FD07 D2
FD14 A5
ID05 C8
ID06 C8
ID07 C8
ID08 C8
ID09 C7
9
FD14
1
6
3D09
RIGHT-SPEAKER
I
1
3
2
4
5
6
7
CHN
8
13
12
11
AUDIO
+AUDIO-POWER
C
10
9
8
7
ID10 C7
ID11 A4
ID12 A4
ID16 C4
ID18 C5
ID19 B5
ID27 A6
ID28 B6
ID29 C5
ID30 C5
ID31 C6
ID32 C6
ID33 D2
ID36 B4
ID37 C4
ID38 D4
A
B
C
D
E
F
G
H
I
9
SETNAME
2
CLASS_NO
2008-11-21
CLASS D
J
2008-10-10
3
NAME Randal De Keyzer
CHECK
1
2
3
4
5
7
6
J
8204 000 8931
TV543 R2 LDIPNX
8
1
SUPERS.
DATE
9
2007-10-12
130
C
10
1
A3
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_548_090303.eps
090303
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 134
SSB: SRP List Explanation
Personal Notes:
Example
Net Name
Diagram
+12-15V
AP1 (4x)
+12-15V
AP4 (4x)
+12-15V
AP5 (12x)
+12-15V
AP6 (4x)
+12-15V
AP7 (8x)
+12V
AP1 (4x)
+12V_NF
AP1 (2x)
+12VAL
AP1 (2x)
+25VLP
AP1 (4x)
+25VLP
AP2 (1x)
+3V3-STANDBY
AP5 (3x)
+400V-F
AP1 (2x)
+400V-F
AP2 (2x)
+400V-F
AP3 (2x)
+5V2
AP1 (6x)
+5V2
AP2 (1x)
+5V2-NF
AP1 (1x)
+5V2-NF
AP2 (1x)
+5V-SW
AP1 (6x)
+5V-SW
AP2 (1x)
+8V6
AP1 (3x)
+AUX
AP1 (2x)
+AUX
AP2 (1x)
+DC-F
AP1 (2x)
+DC-F
AP3 (2x)
+SUB-SPEAKER
AP5 (1x)
+SUB-SPEAKER
AP6 (2x)
-12-15V
AP1 (4x)
-12-15V
AP4 (6x)
-12-15V
AP5 (14x)
-12-15V
AP6 (6x)
-12-15V
AP7 (8x)
AL-OFF
AP1 (2x)
AUDIO-L
AP4 (1x)
AUDIO-L
AP5 (1x)
AUDIO-PROT
AP5 (3x)
AUDIO-R
AP4 (1x)
AUDIO-R
AP5 (1x)
AUDIO-SW
AP5 (1x)
AUDIO-SW
AP7 (1x)
BOOST
AP1 (2x)
CPROT
AP4 (2x)
CPROT
AP5 (1x)
CPROT-SW
AP5 (1x)
CPROT-SW
AP6 (2x)
-DC-F
AP1 (2x)
-DC-F
AP3 (2x)
DC-PROT
AP1 (1x)
DC-PROT
AP5 (2x)
DIM-CONTROL
AP1 (2x)
FEEDBACK+SW
AP6 (2x)
FEEDBACK-L
AP4 (2x)
FEEDBACK-R
AP4 (2x)
FEEDBACK-SW
AP6 (2x)
GND-AL
AP1 (2x)
GNDHA
AP1 (40x)
GNDHA
AP2 (20x)
GNDHA
AP3 (2x)
GNDHOT
AP3 (2x)
GND-L
AP1 (2x)
GND-L
AP4 (4x)
GND-L
AP5 (34x)
GND-LL
AP4 (7x)
GND-LL
AP5 (1x)
GND-LR
AP4 (7x)
GND-LR
AP5 (1x)
GND-LSW
AP5 (1x)
GND-LSW
AP6 (15x)
GND-S
AP1 (11x)
GND-SA
AP4 (8x)
AP5 (2x)
GND-SA
GND-SA
AP6 (8x)
GND-SA
AP7 (6x)
GNDscrew
AP3 (2x)
GNDscrew
AP5 (2x)
GND-SSB
AP5 (3x)
GND-SSP
AP1 (51x)
GND-SSP
AP2 (15x)
IN+SW
AP6 (2x)
IN-L
AP4 (2x)
IN-R
AP4 (2x)
IN-SW
AP6 (2x)
INV-MUTE
AP4 (1x)
INV-MUTE
AP5 (1x)
INV-MUTE
AP6 (1x)
LEFT-SPEAKER
AP4 (1x)
LEFT-SPEAKER
AP5 (1x)
MUTE
AP4 (2x)
MUTE
AP5 (1x)
MUTE
AP6 (2x)
ON-OFF
AP1 (3x)
OUT
AP6 (1x)
OUT
AP7 (2x)
OUTN
AP6 (1x)
OUTN
AP7 (1x)
POWER-GOOD
AP1 (2x)
POWER-OK-PLATFORM AP1 (2x)
RIGHT-SPEAKER
AP4 (1x)
RIGHT-SPEAKER
AP5 (1x)
SOUND-ENABLE
AP5 (3x)
STANDBY
AP1 (5x)
STANDBY
AP2 (1x)
-SUB-SPEAKER
AP5 (1x)
-SUB-SPEAKER
AP6 (2x)
V-CLAMP
AP1 (1x)
V-CLAMP
AP3 (2x)
1.1.
Introduction
SRP (Service Reference Protocol) is a software tool that creates a list with all references to signal lines. The list contains
references to the signals within all schematics of a PWB. It replaces the text references currently printed next to the signal
names in the schematics. These printed references are created manually and are therefore not guaranteed to be 100%
correct. In addition, in the current crowded schematics there is often none or very little place for these references.
Some of the PWB schematics will use SRP while others will still use the manual references. Either there will be an SRP
reference list for a schematic, or there will be printed references in the schematic.
1.2.
Non-SRP Schematics
There are several different signals available in a schematic:
1.2.1.
Power Supply Lines
All power supply lines are available in the supply line overview (see chapter 6). In the schematics (see chapter 7) is not
indicated where supplies are coming from or going to.
It is however indicated if a supply is incoming (created elsewhere), or outgoing (created or adapted in the current schematic).
+5V
Outgoing
1.2.2.
+5V
Incoming
Normal Signals
For normal signals, a schematic reference (e.g. B14b) is placed next to the signals.
B14b
1.2.3.
signal_name
Grounds
For normal and special grounds (e.g. GNDHOT or GND3V3 etc.), nothing is indicated.
1.3.
SRP Schematics
SRP is a tool, which automatically creates a list with signal references, indicating on which schematic the signals are used.
A reference is created for all signals indicated with an SRP symbol, these symbols are:
+5V
name
name
+5V
Power supply line.
name
Stand alone signal or switching line (used as less as possible).
name
Signal line into a wire tree.
name
name
Switching line into a wire tree.
name
Bi-directional line (e.g. SDA) into a wire tree.
name
Signal line into a wire tree, its direction depends on the circuit (e.g. ingoing for PDP, outgoing for LCD sets).
Remarks:
•
When there is a black dot on the "signal direction arrow" it is an SRP symbol, so there will be a reference to the signal
name in the SRP list.
•
All references to normal grounds (Ground symbols without additional text) are not listed in the reference list, this to keep
it concise.
•
Signals that are not used in multiple schematics, but only once or several times in the same schematic, are included
in the SRP reference list, but only with one reference.
Additional Tip:
When using the PDF service manual file, you can very easily search for signal names and follow the signal over all the
schematics. In Adobe PDF reader:
•
Select the signal name you want to search for, with the "Select text" tool.
•
Copy and paste the signal name in the "Search PDF" tool.
•
Search for all occurrences of the signal name.
•
Now you can quickly jump between the different occurrences and follow the signal over all schematics. It is advised to
"zoom in" to e.g. 150% to see clearly, which text is selected. Then you can zoom out, to get an overview of the complete
schematic.
PS. It is recommended to use at least Adobe PDF (reader) version 6.x, due to better search possibilities in this version.
10000_031_090121.eps
090121
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 135
SSB: SRP List Part 1
Netname
Schematic
B01B
B01C
B02B
B06B
B06C
B07B
B07H
B08B
B09B
B01B
B05H
B01A
B01B
B01A
B01C
B02B
B02B
B06E
B06G
B06A
B06E
B06G
B01C
B04A
B05C
B05C
B05C
B05C
B05C
B05C
B05C
B05C
B01A
B02B
B04A
B04P
B06A
B06E
B01A
B01B
B04P
B05A
B05C
B06E
B04G
B04P
B06E
B07D
B09B
B06A
B06E
B06F
B09B
B06F
B06G
B06E
B06G
B06A
B06E
B06G
B06E
B06G
B09B
B01B
B02A
B01A
B01B
B02B
B04A
B04L
B04M
B04N
B04P
B05C
B05E
B05F
B05G
B05H
B05I
B06A
B06B
B06C
B06E
B07A
B07C
B07D
B07F
B07G
B07H
B08A
B08B
B08D
B09A
B02A
B02B
B02B
B02B
B07G
B07G
B01A
B05H
B09B
B06E
B06G
B06A
B09A
B07F
B04A
B04B
B04E
B04F
B04N
B04P
B05C
B05C
B05C
B05C
B01B
B04A
B04P
B07D
+12V
+12V
+12V
+12V
+12V
+12V
+12V
+12V
+12V
+12VD
+12VD
+12VF
+12VF
+12VF1
+12VF2
+1V2
+1V2A
+1V2-FPGA
+1V2-FPGA
+1V2M
+1V2-PLL
+1V2-PLL
+1V2-PNX5100
+1V2-PNX5100
+1V2-PNX5100
+1V2-PNX5100-CLOCK
+1V2-PNX5100-DDR-PLL1
+1V2-PNX5100-DLL
+1V2-PNX5100-LVDS-PLL
+1V2-PNX5100-TRI-PLL1
+1V2-PNX5100-TRI-PLL2
+1V2-PNX5100-TRI-PLL3
+1V2-PNX85XX
+1V2-PNX85XX
+1V2-PNX85XX
+1V2-PNX85XX
+1V2-PNX85XX
+1V2-PNX85XX
+1V2-STANDBY
+1V2-STANDBY
+1V2-STANDBY
+1V8-PNX5100
+1V8-PNX5100
+1V8-PNX5100
+1V8-PNX85XX
+1V8-PNX85XX
+1V8-PNX85XX
+1V8-PNX85XX
+1V8-PNX85XX
+2V5
+2V5
+2V5
+2V5
+2V5-DDR1
+2V5-DDR1
+2V5in-FPGA
+2V5in-FPGA
+2V5M
+2V5out-FPGA
+2V5out-FPGA
+2V5-PLL
+2V5-PLL
+2V5-REF
+33VTUN
+33VTUN
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3A
+3V3A
+3V3D
+3V3E
+3V3-ET-ANA
+3V3-ET-DIG
+3V3F
+3V3F
+3V3F
+3V3-FPGA
+3V3-FPGA
+3V3M
+3V3-mPCI
+3V3-NAND
+3V3-PER
+3V3-PER
+3V3-PER
+3V3-PER
+3V3-PER
+3V3-PER
+3V3-PNX5100-CLOCK
+3V3-PNX5100-DDR-PLL0
+3V3-PNX5100-LVDS-IN
+3V3-PNX5100-LVDS-PLL
+3V3-STANDBY
+3V3-STANDBY
+3V3-STANDBY
+3V3-STANDBY
B08D
B09B
B01B
B01C
B04A
B04L
B06A
B07C
B07D
B08A
B08B
B08D
B09A
B01C
B07H
B07E
B07D
B07E
B09A
B02A
B02B
B07H
B02B
B02A
B04I
B10
B01B
B04I
B04M
B10
B05H
B06D
B05E
B05H
B05E
B05H
B09B
B02A
B07D
B04I (1×)
B04L (1×)
B04I (1×)
B04L (1×)
B04L (1×)
B04M (1×)
B04L (1×)
B04M (1×)
B04I (1×)
B04L (1×)
B04I (1×)
B04L (1×)
B04I (1×)
B04L (3×)
B04I (1×)
B04L (3×)
B07D (4×)
B04A (2×)
B05D (1×)
B02B (2×)
B02A (2×)
B02B (1×)
B04M (1×)
B08A (1×)
B08B (2×)
B08A (3×)
B08A (3×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (3×)
B07D (3×)
B07D (2×)
B06E (1×)
B06G (1×)
B04M (1×)
B10 (2×)
B04I (1×)
B08A (1×)
B04I (1×)
B08A (1×)
B04M (1×)
B08C (1×)
B04M (1×)
B08C (1×)
B04L (1×)
B08D (2×)
B04L (1×)
B08D (2×)
B04L (1×)
B08A (1×)
B04L (1×)
B08A (1×)
B04L (1×)
B08B (1×)
B04L (1×)
B08B (1×)
B04L (1×)
B07B (1×)
B04L (1×)
B07B (1×)
B04L (1×)
B08C (2×)
B04L (1×)
B08C (2×)
B04A (2×)
B10 (1×)
B04I (1×)
B08B (1×)
B04I (1×)
B08B (1×)
B04I (1×)
B10 (1×)
B04I (7×)
B04M (2×)
B08A (1×)
B08D (3×)
B08A (1×)
B08D (3×)
+3V3-STANDBY
+3V3-STANDBY
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V5-TUN
+5V5-TUN
+5V-DDC
+5V-EDID
+5V-EDID
+5V-mPCI
+5V-TUN
+5V-TUN
+5V-TUN
+5V-TUN-CVBS
+5V-TUN-PIN
+AUDIO-L
+AUDIO-L
+AUDIO-POWER
+AUDIO-POWER
+AUDIO-POWER
+AUDIO-POWER
+VDISP
+VDISP
+VDISP1
+VDISP1
+VDISP2
+VDISP2
+V-LM833
+VTUN
1V8-HDMI
ADAC(1)
ADAC(1)
ADAC(2)
ADAC(2)
ADAC(3)
ADAC(3)
ADAC(4)
ADAC(4)
ADAC(5)
ADAC(5)
ADAC(6)
ADAC(6)
ADAC(7)
ADAC(7)
ADAC(8)
ADAC(8)
AIN-5V
ALE
AMBI-VS
ANTENNA-CTRL
ANTENNA-SUPPLY
ANTENNA-SUPPLY
A-PLOP
A-PLOP
A-PLOP
AP-SCART-OUT-L
AP-SCART-OUT-R
ARX0ARX0+
ARX1ARX1+
ARX2ARX2+
ARXCARXC+
ARX-DDC-SCL
ARX-DDC-SDA
ARX-HOTPLUG
ASDO
ASDO
A-STBY
A-STBY
AUDIO-CL-L
AUDIO-CL-L
AUDIO-CL-R
AUDIO-CL-R
AUDIO-HDPH-L-AP
AUDIO-HDPH-L-AP
AUDIO-HDPH-R-AP
AUDIO-HDPH-R-AP
AUDIO-IN1-L
AUDIO-IN1-L
AUDIO-IN1-R
AUDIO-IN1-R
AUDIO-IN2-L
AUDIO-IN2-L
AUDIO-IN2-R
AUDIO-IN2-R
AUDIO-IN3-L
AUDIO-IN3-L
AUDIO-IN3-R
AUDIO-IN3-R
AUDIO-IN4-L
AUDIO-IN4-L
AUDIO-IN4-R
AUDIO-IN4-R
AUDIO-IN5-L
AUDIO-IN5-L
AUDIO-IN5-R
AUDIO-IN5-R
AUDIO-MUTE
AUDIO-MUTE
AUDIO-OUT-L
AUDIO-OUT-L
AUDIO-OUT-R
AUDIO-OUT-R
-AUDIO-R
-AUDIO-R
AUDIO-VDD
AUDIO-VDD
AV1-AUDIO-L
AV1-AUDIO-L
AV1-AUDIO-R
AV1-AUDIO-R
B08A (1×)
B08D (3×)
B04A (1×)
B08A (1×)
B08D (1×)
B08A (1×)
B08D (1×)
B08A (1×)
B08D (3×)
B08A (1×)
B08D (3×)
B04K (1×)
B08D (2×)
B04K (1×)
B08D (2×)
B08A (1×)
B08D (3×)
B04A (1×)
B08A (1×)
B04K (1×)
B08D (2×)
B04K (1×)
B08B (1×)
B08D (2×)
B04A (1×)
B08A (1×)
B04A (1×)
B08A (1×)
B04K (1×)
B08A (1×)
B08B (1×)
B04K (1×)
B08A (1×)
B04K (1×)
B08A (1×)
B04K (1×)
B08A (1×)
B04K (1×)
B08A (1×)
B08B (1×)
B04K (1×)
B08A (1×)
B08B (1×)
B04K (2×)
B08A (1×)
B08B (1×)
B04K (1×)
B08A (1×)
B04K (1×)
B08A (1×)
B04K (2×)
B08A (1×)
B01B (1×)
B05H (1×)
B05H (1×)
B06A (1×)
B06G (1×)
B05H (3×)
B01B (1×)
B05E (1×)
B05H (1×)
B06G (1×)
B05H (1×)
B06G (1×)
B01B (1×)
B05H (1×)
B05H (2×)
B02A (3×)
B02A (3×)
B07D (4×)
B06A (2×)
B06A (2×)
B06A (2×)
B06A (2×)
B06A (2×)
B05D (1×)
B06A (1×)
B05D (1×)
B06A (1×)
B05D (1×)
B06A (1×)
B06A (2×)
B05D (1×)
B06A (1×)
B08D (2×)
B08D (2×)
B08D (2×)
B08D (2×)
B08D (2×)
B04A (2×)
B04N (1×)
B08D (3×)
B04A (2×)
B04N (1×)
B05H (3×)
B04E (2×)
B08D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (3×)
B07D (3×)
B07D (2×)
B04K (1×)
B08B (1×)
B04N (1×)
B07H (3×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B04N (1×)
B07H (1×)
B04N (1×)
AV1-B
AV1-B
AV1-BLK
AV1-BLK
AV1-BLK
AV1-BLK-BO
AV1-BLK-BO
AV1-CVBS
AV1-CVBS
AV1-G
AV1-G
AV1-PB
AV1-PB
AV1-PR
AV1-PR
AV1-R
AV1-R
AV1-STATUS
AV1-STATUS
AV1-Y
AV1-Y
AV1-Y_CVBS
AV1-Y_CVBS
AV1-Y_CVBS
AV2-BLK
AV2-BLK
AV2-STATUS
AV2-STATUS
AV2-Y_CVBS
AV2-Y_CVBS
AV2-Y_CVBS
AV3-PB
AV3-PB
AV3-PR
AV3-PR
AV3-Y
AV3-Y
AV4-PB
AV4-PB
AV4-PB
AV4-PR
AV4-PR
AV4-PR
AV4-Y
AV4-Y
AV4-Y
AV5-PB
AV5-PB
AV5-PR
AV5-PR
AV5-Y
AV5-Y
BACKLIGHT-BOOST
BACKLIGHT-BOOST
BACKLIGHT-CONTROL-FPGA-IN
BACKLIGHT-CONTROL-FPGA-IN
BACKLIGHT-CONTROL-FPGA-IN
BACKLIGHT-CTRL
BACKLIGHT-OUT
BACKLIGHT-OUT
BACKLIGHT-OUT
BACKLIGHT-OUT
BACKLIGHT-OUT2
BACKLIGHT-OUT2
BACKLIGHT-PWM-ANA-DISP
BACKLIGHT-PWM-ANA-DISP
BACKLIGHT-PWM-ANA-SSB
B-IF-_N-IFB-IF+_N-IF+
BIN-5V
BL-CLK
BL-CS
BL-HS
BL-MISO
BL-MOSI
BL-OSCLK
BL-OSCLK
BL-SCK
BL-SCK
BL-SD0
BL-SD0
BL-VS
BL-WS
BL-WS
BO-AUDIO-L
BO-AUDIO-R
BO-B
BO-CVBS
BO-G
BOLT-ON-IO
BOLT-ON-IO
BOLT-ON-IO
BOLT-ON-TS-ENn
BOLT-ON-TS-ENn
BOOST-CTRL
BOOTMODE
BO-R
BRX0BRX0+
BRX1BRX1+
BRX2BRX2+
BRXCBRXC+
BRX-DDC-SCL
BRX-DDC-SDA
BRX-HOTPLUG
B-VGA
B-VGA
CA-ADDEN
CA-ADDEN
CA-CD1
CA-CD1
CA-CD2
CA-CD2
CA-CE1
CA-CE1
CA-CE2
CA-CE2
CA-DATADIR
CA-DATADIR
CA-DATAEN
B07H (1×)
B07A (2×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (1×)
B07A (1×)
B04N (2×)
B07A (2×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B04N (1×)
B07A (2×)
B04N (1×)
B07A (2×)
B07A (2×)
B07H (1×)
B07A (1×)
B07H (1×)
B06A (3×)
B04A (2×)
B07D (1×)
B07D (4×)
B06G (2×)
B05F (1×)
B06A (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (3×)
B07D (3×)
B07D (2×)
B06A (4×)
B05H (2×)
B05H (2×)
B05H (2×)
B05H (3×)
B05E (1×)
B05H (1×)
B05E (1×)
B05H (1×)
B05E (1×)
B05H (1×)
B05E (1×)
B05H (2×)
B02B (1×)
B04K (1×)
B08B (2×)
B08A (2×)
B02B (1×)
B08A (1×)
B08D (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B04H (1×)
B07E (1×)
B04H (1×)
B07E (1×)
CA-DATAEN
CA-INPACK
CA-IORD
CA-IORD
CA-IOWR
CA-IOWR
CA-MDI0
CA-MDI0
CA-MDI1
CA-MDI1
CA-MDI2
CA-MDI2
CA-MDI3
CA-MDI3
CA-MDI4
CA-MDI4
CA-MDI5
CA-MDI5
CA-MDI6
CA-MDI6
CA-MDI7
CA-MDI7
CA-MDO0
CA-MDO0
CA-MDO1
CA-MDO1
CA-MDO2
CA-MDO2
CA-MDO3
CA-MDO3
CA-MDO4
CA-MDO4
CA-MDO5
CA-MDO5
CA-MDO6
CA-MDO6
CA-MDO7
CA-MDO7
CA-MICLK
CA-MICLK
CA-MISTRT
CA-MISTRT
CA-MIVAL
CA-MIVAL
CA-MOCLK_VS2
CA-MOCLK_VS2
CA-MOSTRT
CA-MOSTRT
CA-MOVAL
CA-MOVAL
CA-OE
CA-OE
CA-REG
CA-REG
CA-RST
CA-RST
CA-VS1
CA-VS1
CA-WAIT
CA-WAIT
CA-WE
CA-WE
CCLK
CEC-HDMI
CEC-HDMI
CIN-5V
CLK-OUT2-PNX5100
CLK-OUT-PNX5100
CLK-OUT-PNX5100
CLK-OUT-PNX5100
CON20
CON20
CON21
CON21
CON22
CON22
CON23
CON23
CON26
CON26
CON27
CON27
CONF-DONE
CONF-DONE
CRX0CRX0+
CRX1CRX1+
CRX2CRX2+
CRXCCRXC+
CRX-DDC-SCL
CRX-DDC-SDA
CRX-HOTPLUG
CSO-B
CTRL1-PNX5100
CTRL2-PNX5100
CTRL3-PNX5100
CTRL4-PNX5100
CTRL-DISP1
CTRL-DISP1
CTRL-DISP2
CTRL-DISP2
CTRL-DISP3
CTRL-DISP3
CTRL-DISP4
CTRL-DISP4
CVBS4
CVBS4
CVBS-MON-OUT-CINCH
CVBS-OUT-SC1
CVBS-TER-OUT
CVBS-TER-OUT
CVBS-TER-OUT
DATA0
DATA0
DCLK
DCLK
DDCA-SCL
DDCA-SCL
DDCA-SDA
DDCA-SDA
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (3×)
B04G (2×)
B04G (3×)
B04G (3×)
B04G (4×)
B04G (4×)
B04G (3×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (2×)
B04G (3×)
B04G (3×)
B04G (2×)
B04G (3×)
B04G (3×)
B04A (3×)
B01B (1×)
B04A (1×)
B04A (3×)
B07D (4×)
B06A (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B06F (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (2×)
B07D (3×)
B07D (3×)
B07D (2×)
B04A (2×)
B07E (4×)
B04A (2×)
B06B (1×)
B05F (1×)
B05F (1×)
B05F (1×)
B05F (1×)
B05F (1×)
B04E (2×)
B06B (1×)
B04E (2×)
B06B (1×)
B04E (2×)
DDC-SCL
DDC-SCL
DDC-SDA
DDC-SDA
DDR2-A0
DDR2-A1
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-BA0
DDR2-BA1
DDR2-BA2
DDR2-CAS
DDR2-CKE
DDR2-CLK_N
DDR2-CLK_P
DDR2-CS
DDR2-D0
DDR2-D1
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D2
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23
DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D3
DDR2-D30
DDR2-D31
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3
DDR2-DQS0_N
DDR2-DQS0_P
DDR2-DQS1_N
DDR2-DQS1_P
DDR2-DQS2_N
DDR2-DQS2_P
DDR2-DQS3_N
DDR2-DQS3_P
DDR2-ODT
DDR2-RAS
DDR2-VREF-CTRL
DDR2-VREF-DDR
DDR2-WE
DETECT1
DETECT-12V
DETECT-12V
DETECT2
DIN-5V
DONE
DQ1(0)
DQ1(1)
DQ1(10)
DQ1(11)
DQ1(12)
DQ1(13)
DQ1(14)
DQ1(15)
DQ1(2)
DQ1(3)
DQ1(4)
DQ1(5)
DQ1(6)
DQ1(7)
DQ1(8)
DQ1(9)
DQS10
DQS11
DRX0DRX0+
DRX1DRX1+
DRX2DRX2+
DRXCDRXC+
DRX-DDC-SCL
DRX-DDC-SDA
DRX-HOTPLUG
EA
EIN-5V
EJTAG-DETECT
EJTAG-DETECT
EJTAG-PNX5100-TCK
EJTAG-PNX5100-TDI
EJTAG-PNX5100-TDO
EJTAG-PNX5100-TMS
EJTAG-PNX5100-TRSTn
EJTAG-TCK
EJTAG-TCK
EJTAG-TDI
EJTAG-TDI
EJTAG-TDO
B06B (1×)
B04E (2×)
B06B (1×)
B04E (2×)
B06B (1×)
B01B (1×)
B04A (2×)
B01A (1×)
B01B (1×)
B01C (1×)
B07E (3×)
B07E (3×)
B07E (3×)
B06C (2×)
B06C (2×)
B06C (2×)
B05H (1×)
B06C (1×)
B05H (1×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B04N (4×)
B02B (1×)
B04N (3×)
B02B (1×)
B04N (3×)
B04K (1×)
B08C (2×)
B04K (1×)
B08C (2×)
B10 (2×)
B01B (1×)
B10 (16×)
B01A (15×)
B01C (15×)
B04K (1×)
B08B (1×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07E (2×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B07D (1×)
B04H (1×)
B04H (1×)
B07E (1×)
B04K (1×)
B08B (1×)
B04N (1×)
B07F (1×)
B04N (1×)
B07F (1×)
B09A (2×)
B02A (1×)
B02B (1×)
B02A (1×)
B02B (1×)
B02A (2×)
B02B (1×)
B04K (1×)
B02B (1×)
B04K (1×)
B09A (1×)
B09A (1×)
B04E (2×)
B04N (1×)
B07A (2×)
B04E (2×)
B07G (1×)
B09A (2×)
B01B (1×)
B04A (2×)
B09B (1×)
B04A (3×)
B01B (1×)
B04A (1×)
B05E (1×)
B05H (2×)
B01B (2×)
B04A (2×)
B01B (2×)
EJTAG-TDO
EJTAG-TMS
EJTAG-TMS
EJTAG-TRSTN
EJTAG-TRSTN
ENABLE-3V3
ENABLE-3V3
ENABLE-3V3-5V
ENABLE-3V3-5V
ENABLE-3V3-5V
ERX-DDC-SCL
ERX-DDC-SDA
ERX-HOTPLUG
FAN1-DRV
FAN1-OUT
FAN2-DRV
FAN-CTRL-1
FAN-CTRL-1
FAN-CTRL-2
FE-CLK
FE-CLK
FE-DATA0
FE-DATA0
FE-DATA1
FE-DATA1
FE-DATA2
FE-DATA2
FE-DATA3
FE-DATA3
FE-DATA4
FE-DATA4
FE-DATA5
FE-DATA5
FE-DATA6
FE-DATA6
FE-DATA7
FE-DATA7
FE-ERR
FE-SOP
FE-SOP
FE-VALID
FE-VALID
FRONT-C
FRONT-C
FRONT-Y_CVBS
FRONT-Y_CVBS
GND-A
GND-AUDIO
GND-AUDIO
GND-SIG
GND-SIG1
G-VGA
G-VGA
HDMIA-RX0HDMIA-RX0HDMIA-RX0+
HDMIA-RX0+
HDMIA-RX1HDMIA-RX1HDMIA-RX1+
HDMIA-RX1+
HDMIA-RX2HDMIA-RX2HDMIA-RX2+
HDMIA-RX2+
HDMIA-RXCHDMIA-RXCHDMIA-RXC+
HDMIA-RXC+
HDMIB-RX0HDMIB-RX0HDMIB-RX0+
HDMIB-RX0+
HDMIB-RX1HDMIB-RX1HDMIB-RX1+
HDMIB-RX1+
HDMIB-RX2HDMIB-RX2HDMIB-RX2+
HDMIB-RX2+
HDMIB-RXCHDMIB-RXCHDMIB-RXC+
HDMIB-RXC+
HOT-PLUG
HOT-PLUG-A
HOT-PLUG-A
H-SYNC-VGA
H-SYNC-VGA
I2C-SCL
I2C-SCL
I2C-SDA
I2C-SDA
IDSEL
IFIFIF+
IF+
IF-AGC
IF-AGC
IF-N
IF-P
IF-P
IRQA-mPCI
IRQB-mPCI
IRQ-CA
IRQ-CA
IRQ-CA
IRQ-PCI
IRQ-PCI
IRQ-PCI
KEYBOARD
KEYBOARD
KEYBOARD
LAMP-ON
LAMP-ON-OUT
LAMP-ON-OUT
LAMP-ON-OUT
LCD-PWR-ON
LED1
LED1
LED2
B04A (2×)
B10 (3×)
B01B (2×)
B04A (1×)
B09A (2×)
B07A (4×)
B07A (4×)
B07A (4×)
B07A (4×)
B07A (4×)
B07A (4×)
B07A (4×)
B07A (4×)
B04A (2×)
B08D (3×)
B06A (3×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
B06F (1×)
B06G (1×)
LED2
LEFT-SPEAKER
LIGHT-SENSOR
LIGHT-SENSOR
M66EN
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
MHP-SWITCH
MHP-SWITCH
MISO
MM1-A0
MM1-A0
MM1-A1
MM1-A1
MM1-A10
MM1-A10
MM1-A11
MM1-A11
MM1-A12
MM1-A12
MM1-A2
MM1-A2
MM1-A3
MM1-A3
MM1-A4
MM1-A4
MM1-A5
MM1-A5
MM1-A6
MM1-A6
MM1-A7
MM1-A7
MM1-A8
MM1-A8
MM1-A9
MM1-A9
MM1-BA0
MM1-BA0
MM1-BA1
MM1-BA1
MM1-CAS
MM1-CAS
MM1-CKE
MM1-CKE
MM1-CLKMM1-CLKMM1-CLK+
MM1-CLK+
MM1-CS0
MM1-CS0
MM1-D0
MM1-D0
MM1-D1
MM1-D1
MM1-D10
MM1-D10
MM1-D11
MM1-D11
MM1-D12
MM1-D12
MM1-D13
MM1-D13
MM1-D14
MM1-D14
MM1-D15
MM1-D15
MM1-D2
MM1-D2
MM1-D3
MM1-D3
MM1-D4
MM1-D4
MM1-D5
MM1-D5
MM1-D6
MM1-D6
MM1-D7
MM1-D7
MM1-D8
MM1-D8
MM1-D9
MM1-D9
MM1-DQS0
MM1-DQS0
MM1-DQS1
MM1-DQS1
MM1-RAS
MM1-RAS
18310_700_090309.eps
090309
3104 313 6343.2
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 136
SSB: SRP List Part 2
Netname
Schematic
B06F (1×)
B06G (1×)
B07A (4×)
B06A (3×)
B07A (4×)
B07A (4×)
B09A (2×)
B06G (1×)
B06G (1×)
B06G (1×)
B06G (1×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B07F (2×)
B06G (2×)
B06G (2×)
B06E (1×)
B06G (1×)
B06G (2×)
B07D (6×)
B07E (2×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (2×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (2×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (2×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (2×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (2×)
B07H (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
MM1-WE
MM1-WE
MOCLK_VS2
MOSI
MOSTRT
MOVAL
MPCIACT
MSEL0
MSEL1
MSEL2
MSEL3
NAND-AD(0)
NAND-AD(1)
NAND-AD(2)
NAND-AD(3)
NAND-AD(4)
NAND-AD(5)
NAND-AD(6)
NAND-AD(7)
NAND-ALE
NAND-CLE
NAND-REn
NAND-WEn
nCE
nCONFIG
nCSO
nCSO
nSTATUS
PCEC-HDMI
PCEC-HDMI
PCI-AD0
PCI-AD0
PCI-AD0
PCI-AD0
PCI-AD0
PCI-AD0
PCI-AD1
PCI-AD1
PCI-AD1
PCI-AD1
PCI-AD1
PCI-AD1
PCI-AD10
PCI-AD10
PCI-AD10
PCI-AD10
PCI-AD10
PCI-AD11
PCI-AD11
PCI-AD11
PCI-AD11
PCI-AD11
PCI-AD12
PCI-AD12
PCI-AD12
PCI-AD12
PCI-AD12
PCI-AD13
PCI-AD13
PCI-AD13
PCI-AD13
PCI-AD13
PCI-AD14
PCI-AD14
PCI-AD14
PCI-AD14
PCI-AD14
PCI-AD15
PCI-AD15
PCI-AD15
PCI-AD15
PCI-AD16
PCI-AD16
PCI-AD16
PCI-AD16
PCI-AD16
PCI-AD17
PCI-AD17
PCI-AD17
PCI-AD17
PCI-AD17
PCI-AD18
PCI-AD18
PCI-AD18
PCI-AD18
PCI-AD18
PCI-AD19
PCI-AD19
PCI-AD19
PCI-AD19
PCI-AD19
PCI-AD2
PCI-AD2
PCI-AD2
PCI-AD2
PCI-AD2
PCI-AD20
PCI-AD20
PCI-AD20
PCI-AD20
PCI-AD21
PCI-AD21
PCI-AD21
PCI-AD21
PCI-AD22
PCI-AD22
PCI-AD22
PCI-AD22
PCI-AD22
PCI-AD23
PCI-AD23
PCI-AD23
PCI-AD23
PCI-AD23
PCI-AD24
PCI-AD24
PCI-AD24
PCI-AD24
PCI-AD24
PCI-AD24
PCI-AD25
B05G (2×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07F (1×)
B07G (1×)
B07H (1×)
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B07G (1×)
B04F (2×)
B09A (1×)
B04E (1×)
B04F (3×)
B04F (2×)
B05G (1×)
B04F (3×)
B09A (2×)
B04F (2×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B04F (2×)
B04F (1×)
B07G (1×)
B04F (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07G (1×)
PCI-AD25
PCI-AD25
PCI-AD25
PCI-AD25
PCI-AD25
PCI-AD26
PCI-AD26
PCI-AD26
PCI-AD26
PCI-AD26
PCI-AD26
PCI-AD27
PCI-AD27
PCI-AD27
PCI-AD27
PCI-AD27
PCI-AD27
PCI-AD28
PCI-AD28
PCI-AD28
PCI-AD28
PCI-AD28
PCI-AD28
PCI-AD29
PCI-AD29
PCI-AD29
PCI-AD29
PCI-AD29
PCI-AD29
PCI-AD3
PCI-AD3
PCI-AD3
PCI-AD3
PCI-AD3
PCI-AD30
PCI-AD30
PCI-AD30
PCI-AD30
PCI-AD30
PCI-AD30
PCI-AD31
PCI-AD31
PCI-AD31
PCI-AD31
PCI-AD31
PCI-AD31
PCI-AD4
PCI-AD4
PCI-AD4
PCI-AD4
PCI-AD4
PCI-AD5
PCI-AD5
PCI-AD5
PCI-AD5
PCI-AD5
PCI-AD6
PCI-AD6
PCI-AD6
PCI-AD6
PCI-AD6
PCI-AD7
PCI-AD7
PCI-AD7
PCI-AD7
PCI-AD7
PCI-AD8
PCI-AD8
PCI-AD8
PCI-AD8
PCI-AD8
PCI-AD9
PCI-AD9
PCI-AD9
PCI-AD9
PCI-AD9
PCI-CBE0
PCI-CBE0
PCI-CBE0
PCI-CBE0
PCI-CBE1
PCI-CBE1
PCI-CBE1
PCI-CBE1
PCI-CBE1
PCI-CBE1
PCI-CBE2
PCI-CBE2
PCI-CBE2
PCI-CBE2
PCI-CBE2
PCI-CBE2
PCI-CBE3
PCI-CBE3
PCI-CBE3
PCI-CBE3
PCI-CLK-ETHERNET
PCI-CLK-ETHERNET
PCI-CLK-MINI
PCI-CLK-MINI
PCI-CLK-OUT
PCI-CLK-OUT
PCI-CLK-PNX5100
PCI-CLK-PNX5100
PCI-CLK-PNX8535
PCI-CLKRUN
PCI-DEVSEL
PCI-DEVSEL
PCI-DEVSEL
PCI-DEVSEL
PCI-FRAME
PCI-FRAME
PCI-FRAME
PCI-FRAME
PCI-GNT
PCI-GNT-B
PCI-GNT-ETH
PCI-GNT-ETH
PCI-GNT-MINI
PCI-GNT-MINI
PCI-IRDY
PCI-IRDY
PCI-IRDY
B09A (1×)
B04F (1×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B04F (2×)
B04F (1×)
B07G (1×)
B04F (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07G (1×)
B09A (1×)
B04F (2×)
B05G (1×)
B07G (1×)
B09A (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (1×)
B07H (1×)
B07A (5×)
B02A (2×)
B02B (1×)
B02A (1×)
B02B (1×)
B09A (2×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (3×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
PCI-IRDY
PCI-PAR
PCI-PAR
PCI-PAR
PCI-PAR
PCI-PERR
PCI-PERR
PCI-PERR
PCI-PERR
PCI-REQ
PCI-REQ-B
PCI-REQ-ETH
PCI-REQ-ETH
PCI-REQ-MINI
PCI-REQ-MINI
PCI-SERR
PCI-SERR
PCI-SERR
PCI-SERR
PCI-STOP
PCI-STOP
PCI-STOP
PCI-STOP
PCI-TRDY
PCI-TRDY
PCI-TRDY
PCI-TRDY
PCMCIA-A0
PCMCIA-A0
PCMCIA-A1
PCMCIA-A1
PCMCIA-A10
PCMCIA-A10
PCMCIA-A11
PCMCIA-A11
PCMCIA-A12
PCMCIA-A12
PCMCIA-A13
PCMCIA-A13
PCMCIA-A14
PCMCIA-A14
PCMCIA-A2
PCMCIA-A2
PCMCIA-A3
PCMCIA-A3
PCMCIA-A4
PCMCIA-A4
PCMCIA-A5
PCMCIA-A5
PCMCIA-A6
PCMCIA-A6
PCMCIA-A7
PCMCIA-A7
PCMCIA-A8
PCMCIA-A8
PCMCIA-A9
PCMCIA-A9
PCMCIA-D0
PCMCIA-D0
PCMCIA-D1
PCMCIA-D1
PCMCIA-D2
PCMCIA-D2
PCMCIA-D3
PCMCIA-D3
PCMCIA-D4
PCMCIA-D4
PCMCIA-D5
PCMCIA-D5
PCMCIA-D6
PCMCIA-D6
PCMCIA-D7
PCMCIA-D7
PCMCIA-VCC-VPP
PDN
PDN
PDP
PDP
PME
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
PNX5100-DDR2-A2
PNX5100-DDR2-A3
PNX5100-DDR2-A4
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A8
PNX5100-DDR2-A9
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
PNX5100-DDR2-CAS
PNX5100-DDR2-CKE
PNX5100-DDR2-CLK_N
PNX5100-DDR2-CLK_P
PNX5100-DDR2-CS
PNX5100-DDR2-D0
PNX5100-DDR2-D1
PNX5100-DDR2-D10
PNX5100-DDR2-D11
PNX5100-DDR2-D12
PNX5100-DDR2-D13
PNX5100-DDR2-D14
PNX5100-DDR2-D15
PNX5100-DDR2-D16
PNX5100-DDR2-D17
PNX5100-DDR2-D18
PNX5100-DDR2-D19
PNX5100-DDR2-D2
PNX5100-DDR2-D20
PNX5100-DDR2-D21
PNX5100-DDR2-D22
PNX5100-DDR2-D23
PNX5100-DDR2-D24
PNX5100-DDR2-D25
PNX5100-DDR2-D26
PNX5100-DDR2-D27
PNX5100-DDR2-D28
PNX5100-DDR2-D29
PNX5100-DDR2-D3
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (2×)
B05A (3×)
B05A (3×)
B05A (2×)
B05A (3×)
B05A (3×)
B05F (1×)
B05I (1×)
B01B (1×)
B04A (2×)
B06A (2×)
B04A (2×)
B01B (1×)
B04A (2×)
B04A (1×)
B08C (1×)
B04A (1×)
B08C (1×)
B04A (4×)
B08D (1×)
B07D (2×)
B04A (2×)
B08A (1×)
B04A (2×)
B04M (2×)
B04N (1×)
B07F (1×)
B04A (2×)
B07G (2×)
B09A (1×)
B09A (2×)
B04A (3×)
B04A (2×)
B05F (1×)
B04A (2×)
B02B (1×)
B04A (2×)
B04B (1×)
B04E (1×)
B02A (4×)
B02B (1×)
B10 (3×)
B04H (1×)
B04P (2×)
B04K (1×)
B08B (1×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B05B (1×)
B06D (3×)
B08D (3×)
B04E (2×)
B08D (3×)
B04E (2×)
B06B (1×)
B04A (2×)
B08D (4×)
B04E (2×)
B04E (3×)
B04E (2×)
PNX5100-DDR2-D30
PNX5100-DDR2-D31
PNX5100-DDR2-D4
PNX5100-DDR2-D5
PNX5100-DDR2-D6
PNX5100-DDR2-D7
PNX5100-DDR2-D8
PNX5100-DDR2-D9
PNX5100-DDR2-DQM0
PNX5100-DDR2-DQM1
PNX5100-DDR2-DQM2
PNX5100-DDR2-DQM3
PNX5100-DDR2-DQS0_N
PNX5100-DDR2-DQS0_P
PNX5100-DDR2-DQS1_N
PNX5100-DDR2-DQS1_P
PNX5100-DDR2-DQS2_N
PNX5100-DDR2-DQS2_P
PNX5100-DDR2-DQS3_N
PNX5100-DDR2-DQS3_P
PNX5100-DDR2-ODT
PNX5100-DDR2-RAS
PNX5100-DDR2-VREF-CTRL
PNX5100-DDR2-VREF-DDR
PNX5100-DDR2-WE
PNX5100-RST-OUT
PNX5100-RST-OUT
POWER-OK
POWER-OK
PROG-B
PSEN
RC
RC
RC-IN
RC-IN
RC-OUT
RC-OUT
RC-UP
RC-UP
REF-3V3
REGIMBEAU_CVBS-SWITCH
REGIMBEAU_CVBS-SWITCH
RESET-AUDIO
RESET-AUDIO
RESET-BOLT-ON
RESET-BOLT-ON
RESET-ETHERNET
RESET-ETHERNET
RESET-ETHERNET
RESET-mPCI
RESET-NVM
RESET-PNX5100
RESET-PNX5100
RESET-STBY
RESET-SYSTEM
RESET-SYSTEM
RESET-SYSTEM
RESET-SYSTEM
RF-AGC
RF-AGC
RIGHT-SPEAKER
RREF-PNX85XX
RREF-PNX85XX
R-VGA
R-VGA
RX51001ARX51001ARX51001A+
RX51001A+
RX51001BRX51001BRX51001B+
RX51001B+
RX51001CRX51001CRX51001C+
RX51001C+
RX51001CLKRX51001CLKRX51001CLK+
RX51001CLK+
RX51001DRX51001DRX51001D+
RX51001D+
RX51001ERX51001ERX51001E+
RX51001E+
RX51002ARX51002ARX51002A+
RX51002A+
RX51002BRX51002BRX51002B+
RX51002B+
RX51002CRX51002CRX51002C+
RX51002C+
RX51002CLKRX51002CLKRX51002CLK+
RX51002CLK+
RX51002DRX51002DRX51002D+
RX51002D+
RX51002ERX51002ERX51002E+
RX51002E+
RXD
RXD-MIPS
RXD-MIPS
RXD-MIPS2
RXD-MIPS2
RXD-UP
RXD-UP
SCL1
SCL2
SCL3
B05F (1×)
B06A (1×)
B06G (1×)
B04N (1×)
B06A (3×)
B08D (1×)
B05E (2×)
B06A (3×)
B06D (1×)
B01B (1×)
B04E (2×)
B06A (5×)
B06C (2×)
B06A (2×)
B06A (2×)
B02B (2×)
B04E (2×)
B05F (2×)
B06A (1×)
B06G (1×)
B07D (1×)
B08D (1×)
B04A (3×)
B04E (3×)
B04E (2×)
B04E (3×)
B04E (2×)
B05F (1×)
B06A (1×)
B06G (1×)
B04N (1×)
B06A (3×)
B08D (1×)
B05E (2×)
B06A (3×)
B06D (1×)
B01B (1×)
B04E (2×)
B06A (5×)
B06C (2×)
B06A (2×)
B06A (2×)
B02B (2×)
B04E (2×)
B05F (2×)
B06A (1×)
B06G (1×)
B07D (1×)
B08D (1×)
B04A (3×)
B04E (3×)
B04A (2×)
B04B (1×)
B04P (2×)
B04L (1×)
B08D (1×)
B04L (1×)
B08B (1×)
B04A (2×)
B04A (2×)
B04A (2×)
B04B (1×)
B04A (3×)
B04A (2×)
B04A (3×)
B01B (1×)
B04A (2×)
B08D (1×)
B04A (2×)
B06C (2×)
B06C (2×)
B06C (2×)
B06C (2×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B06E (1×)
B06G (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B04N (2×)
B04N (2×)
B07F (1×)
B04N (2×)
B07F (1×)
B02A (5×)
B02A (5×)
B02A (4×)
B02A (5×)
B02A (6×)
B02A (5×)
B02A (5×)
B02A (5×)
B02A (5×)
B02A (5×)
B02A (6×)
B02A (2×)
B02B (2×)
B02A (2×)
B02B (2×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
SCL-AMBI-3V3
SCL-AMBI-3V3
SCL-AMBI-3V3
SCL-BOLT-ON
SCL-BOLT-ON
SCL-BOLT-ON
SCL-DISP
SCL-DISP
SCL-DISP
SCL-SET
SCL-SET
SCL-SET
SCL-SET
SCL-SET0
SCL-SET1
SCL-SSB
SCL-SSB
SCL-SSB
SCL-SSB
SCL-SSB
SCL-SSB
SCL-SSB
SCL-UP-MIPS
SCL-UP-MIPS
SDA1
SDA2
SDA3
SDA-AMBI-3V3
SDA-AMBI-3V3
SDA-AMBI-3V3
SDA-BOLT-ON
SDA-BOLT-ON
SDA-BOLT-ON
SDA-DISP
SDA-DISP
SDA-DISP
SDA-SET
SDA-SET
SDA-SET
SDA-SET
SDA-SET0
SDA-SET1
SDA-SSB
SDA-SSB
SDA-SSB
SDA-SSB
SDA-SSB
SDA-SSB
SDA-SSB
SDA-UP-MIPS
SDA-UP-MIPS
SDM
SDM
SENSE+1V2-PNX85XX
SPDIF-IN1
SPDIF-IN1
SPDIF-OUT
SPDIF-OUT
SPI-CLK
SPI-CSB
SPI-PROG
SPI-PROG
SPI-SDI
SPI-SDO
SPI-WP
STANDBY
STANDBY
STANDBY
SUPPLY-FAULT
TACHO1
TACHO1-INV
TACHO2
TACHO2-INV
TCK
TCK
TDI
TDI
TDO
TDO
TMS
TMS
TSINO-DATA0
TSINO-DATA0
TSINO-DATA1
TSINO-DATA1
TSINO-DATA2
TSINO-DATA2
TSINO-DATA3
TSINO-DATA3
TSINO-DATA4
TSINO-DATA4
TSINO-DATA5
TSINO-DATA5
TSINO-DATA6
TSINO-DATA6
TSINO-DATA7
TSINO-DATA7
TSO-BIT-CLK
TSO-BIT-CLK
TSO-BIT-ERR
TSO-BIT-VALID
TSO-BIT-VALID
TSO-SYNC
TSO-SYNC
TUN-P1
TUN-P10
TUN-P11
TUN-P2
TUN-P3
TUN-P4
TUN-P5
TUN-P6
TUN-P7
TUN-P8
TUN-P9
TUN-SCL
TUN-SCL
TUN-SDA
TUN-SDA
TX1ATX1A+
TX1BTX1B+
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B05E (3×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (2×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B04O (1×)
B06D (1×)
B06G (1×)
B05E (1×)
B06A (1×)
B05E (1×)
B06A (1×)
B08D (3×)
B05E (1×)
B06A (1×)
TX1CTX1C+
TX1CLKTX1CLK+
TX1DTX1D+
TX1ETX1E+
TX2ATX2A+
TX2BTX2B+
TX2CTX2C+
TX2CLKTX2CLK+
TX2DTX2D+
TX2ETX2E+
TX3ATX3A+
TX3BTX3B+
TX3CTX3C+
TX3CLKTX3CLK+
TX3DTX3D+
TX3ETX3E+
TX4ATX4A+
TX4BTX4B+
TX4CTX4C+
TX4CLKTX4CLK+
TX4DTX4D+
TX4ETX4E+
TX851ATX851ATX851ATX851A+
TX851A+
TX851A+
TX851BTX851BTX851BTX851B+
TX851B+
TX851B+
TX851CTX851CTX851CTX851C+
TX851C+
TX851C+
TX851CLKTX851CLKTX851CLKTX851CLK+
TX851CLK+
TX851CLK+
TX851DTX851DTX851DTX851D+
TX851D+
TX851D+
TX851ETX851ETX851ETX851E+
TX851E+
TX851E+
TX852ATX852ATX852ATX852A+
TX852A+
TX852A+
TX852BTX852BTX852BTX852B+
TX852B+
TX852B+
TX852CTX852CTX852CTX852C+
TX852C+
TX852C+
TX852CLKTX852CLKTX852CLKTX852CLK+
TX852CLK+
TX852CLK+
TX852DTX852DTX852DTX852D+
TX852D+
TX852D+
TX852ETX852ETX852ETX852E+
TX852E+
TX852E+
TXCLKTXCLKTXCLK+
TXCLK+
TXD
TXDATTXDAT-
B05E (1×)
B06A (1×)
B04E (2×)
B08D (3×)
B04E (2×)
B06B (1×)
B04A (2×)
B08D (4×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B06D (1×)
B06G (1×)
B04A (2×)
B08D (2×)
B08D (2×)
B04E (2×)
B07C (1×)
B04E (2×)
B07C (1×)
B04E (1×)
B07C (1×)
B04P (2×)
B04L (4×)
B04P (2×)
B04L (1×)
B04P (2×)
B04O (1×)
B04P (1×)
B06F (2×)
B06F (1×)
B06G (16×)
B01A (1×)
B01B (1×)
B04K (1×)
B08B (1×)
B04E (1×)
B05F (2×)
B07D (1×)
B04A (2×)
B07F (2×)
B07D (1×)
B07E (1×)
B08B (1×)
B04F (1×)
B07F (2×)
B04F (1×)
B07F (2×)
B04K (1×)
B08B (1×)
B08A (1×)
B08B (1×)
TXDAT+
TXDAT+
TXD-MIPS
TXD-MIPS
TXD-MIPS2
TXD-MIPS2
TXD-UP
TXD-UP
TXF1ATXF1ATXF1A+
TXF1A+
TXF1BTXF1BTXF1B+
TXF1B+
TXF1CTXF1CTXF1C+
TXF1C+
TXF1CLKTXF1CLKTXF1CLK+
TXF1CLK+
TXF1DTXF1DTXF1D+
TXF1D+
TXF1ETXF1ETXF1E+
TXF1E+
TXF2ATXF2ATXF2A+
TXF2A+
TXF2BTXF2BTXF2B+
TXF2B+
TXF2CTXF2CTXF2C+
TXF2C+
TXF2CLKTXF2CLKTXF2CLK+
TXF2CLK+
TXF2DTXF2DTXF2D+
TXF2D+
TXF2ETXF2ETXF2E+
TXF2E+
UART-SWITCH
UART-SWITCH
UART-SWITCHn
USB20-DM
USB20-DM
USB20-DP
USB20-DP
USB-OC
USB-OC
VDDA-ADC
VDDA-AUDIO
VDDA-AUDIO
VDDA-DAC
VDDA-DAC
VDDA-LVDS
VDDA-LVDS
VREF-DDR1
VREF-FPGA1
VREF-FPGA1
VSW
VSW
V-SYNC-VGA
V-SYNC-VGA
WC-EEPROM-PNX5100
WC-EEPROM-PNX5100
WC-EEPROM-PNX5100
WP-NANDFLASH
WP-NANDFLASH
WRITE-PROT
WRITE-PROT
WRITE-PROT
XIO-ACK
XIO-ACK
XIO-SEL-NAND
XIO-SEL-NAND
Y_CVBS-MON-OUT
Y_CVBS-MON-OUT
Y_CVBS-MON-OUT-SC
Y_CVBS-MON-OUT-SC
18310_701_090309.eps
090309
3104 313 6343.2
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 137
1E00
2E87
6E01
3EA8
2EAK
3EAY
2EAM
3EAZ
2EAN
2ECD
2EAL
3ECH
3EC1
3E81
5T55
3T79
3T72
7T52
3T71
1004
2HTF
3H97
3H84
5HR2
2H89
2HSJ
3HRU
2HSK
5HR5
3HS2
9H05
3H22
7H03
3HS1
2HSM
2HS7
2HS9
2H82
3HRV
5HR0
3HRR
2H83
5H81
3H82
3H81
3H96
2HS8
2H88
2T62
7T51
3T65
3T64
3T62
3HF3
1T01
1T11
1T21
3H25
3H12
3H72
2HTG
3H47
2H84
2H85
7HF2
3H24
3HSB
2HTD
5HRA
3HSD
6HF0
9H28
3H83
3H40
1T25
5H82
3H58
2H94
5HR9
3HSA
7HD0
2H95
2HTB
2HTC
2HTE
2H86
3H64
3H89
5H86
3H90
2H91
3H85
3H98
3H87
5H85
2H92
3H99
2H93
3H91
2H97
2H90
3HSE
2HF1
IH95
2HF0
3HPN
3H29
5H87
3H93
2H98
3H88
3T70
3T60
3T63 2T60
3T75
2T63
1HF0
6E43
2E37
9T63
3T78
3H05
7T53
3T76 3T77
3T95
1H11
3H36
2T61
3H04
IH94
7H00
2E42
3E76
3E78
2E98
3E77
1005
2HS1
5H80
3H80
3H79
3H95
2H87
3HS9
3HS8
9E14
9T24
3E74
2HSN
2HSP
3HST
2HTZ
3HSV
2HSU
7HG1
2HUC
2HSR
2HSA
3HS3
2HTU
2HU0
6E41
2HTV
1P10
3HT4
2HUB
3HRT
3HB2
3HB3
9T40
3T11
3T10
3T12
9P22
9T23 5T10
2T25 9T30
2T22
2T11
5T11
9T15
2T10
9T13
9T29
3T14 2T36 3T15 2T26
9T41
3T16
2T37
3T13
2T29
2T14
9T12
9T20
2T28
9T10 2T39 2T27
2T23 3T22 9T25
2T35
9T16
2H08
9T27
9T18
3H73
3HB5
3HB4
9H08
6T11
6T10
3HWV
9H07
9H06
3HB7
5AC2
1006
3H92
2T12
3HF5
7H04
3HRS
2H09
9HK0
3HFE
3HWN
3HT3
3HB6
2H44
3HWR
2HS4
7H05
TH04TH05
TH06
TH09
TH11
TH13
TH14
TH16
TH10
TH03
TH02
TH08
3HFD
TH12
TH15
2HTL
3HSF
TH01
3E75
3HSN
3HSQ
TH07
1007
9E13
5HRG
3HS4
2HSS
1E14
5HRL
3HSU
2HSB
6E20
3HSR
1P07
2HT8
3HRW
2HSE
3H34
2E35
3HRY
9T11
2HSD
3HS0
9T21
3HRZ
2HSF
5HR3
3AC0
1P9B
1P9A
5P07
2P59
2P24
BP5N
BP5M
2P03
BP1W
3P39
3P48
7P17
7P07
IP16
2P05
BP50
2P47
5P14
5P13
2P49
BP52
2P12
9P203P28
5P06
9P33
2N13
3N0Y
2N0M
7N04
BN0A
BP51
3P29
BP5A
BP55
3P303P31 3P22
9P19
BP1J
BP1K
BP57
BP1D
2P60 3P35
BP5C
BP5B
2D07
2D08
BP1U
BP1A
BP1E
2P58
BP1V
2D18
2D15
2D02
5D05
1D52
3P83 3P82
5D01
1D51
1735
1D50
3D06
3D11
2D13
2D14
3P87
7P16
3P57
2D06
1D53
BP1B
2D10
2D31
1D38
BP1F
1P00
BP5F
BP5H
BP5E
1P02
1P03
1P06
9P31
1P04
BP1T
BP5Z
2D09
2D19
BP1R
2D16
2U8C
2U8D
BP1M
2P15
2D11
1M96
3P80
2D30
5D02 2D12
BP5D
BP56
9P30
9P29
2U8G
2U01
2U8A
7U0D
7U0H
5U18
6U09 5U05
BP1C
BP1P
BP1H
2D24
2U8H
2D20
2D17
5U04
BP53
BP1L
2D23
5U08
BP5G
IN0N
2N1C
BP1S
2U8M
5U19
2U00
2U90
2U8E
5U09
5U31
5U30
1M99
2U21
2U31
IN0T
2U10
2U11
2U36
2U32
5U01
2U23
2U30
IP0J
3P76
3P77
BP1G
IN0V
3U57
3U55
2P17
BP1N
2U14
2U52
3U56
BP5K
2P31
2P573P64
3P63
3P32
3P15
2U0Y
3U66
2U22
7P02
2P27
BP54
2U8K
2U15
1P0A 1P0B
3P34
3P36
2P56
IP68
BN0B
2U06
3U67
2U53
3P21
BN0C
3P37 5P09
3P44
5D04
2U19
7U02 7U08
5U32
BP5R
BN0D
IN0K
2U51
3U58
7P10
2D05
5U02
2P13
2P14
2U0W
BP5P
BP5S
2P28
3U63
3U62
3U76
2U0R
3U85
3U61
3U60
3U82
3U84
3U89
2U40
2U0F
3P40
2U0K
5U00
3U0K
5U03
3U65
3N0G
3P42
3U74
7U06 7U05
5U33
1N00
2P62
3U88
7U0M
2U26
7U40
3U1J
2U1B
1U03 1U01
3U80
7U41
3U86
3U83
2U0Z
5U06
5U20
5U21
2U34
2U33
5U17
2U41
2U35
6U40
2U8F
3U90
CU70
2U25
3U4A
3U3V
2U42
3U64
3P16 2P26
2U47
2U48
3U46
7U0N
5U11
5U10
2U24
3U81
3U97
3U92
3U3W
2U0J
2U43
2U49
3U96
9U06
2U44
5U12
7U50
3U41
9U08
7U10
5U13
3U4B
7U11
3U91
1M20
9U07
3U98
3U93
3U95
3U94
5U07
1M95
2P61
2U2C
1D54
5U16
BP5J
BP5L
3P62 3P60
3P18
3P59
5AC1
1P05
2H81
2HSC
2E36
2H80
3HSH
2HTR
3HSM
2HTP
3HSJ
9P21
2HS3
5HRC
9H13
3HRP
2HS2
2HRZ
5AC4
2U46
1E11
2T65
3T74
3T56
3T73
2H96
2U45
1M36
2E55
2E53
3E80
2HRG
2HRJ
2HRC
2HRK
2HRH
2HRD
2HRE
2HRF
2HR8
IH93
3CH8
2H99
5U14
1HP0
5E01
2E56
2EA3
3EC3
2E54
1010
1003
7HG0
5U15
2E57 2E58
2EA9
3ED1
3EC9
2EB6
7EA1
3EC2
3EC4
2EA2
2EA1
2EAP
7EA3
2EAF
2E45
6E06
1E15
2E40
6E44
3EC0
2HVA
3HV3
2HR5
2HR7
2HR9
2HRB
2HR4
2HR6
2HRA
9H11
2HR1
2HMY
9H12
3HP1
3HP0
2HR0
2HR2
2HR3
2HN1
3HR8
2CH1
1A01
3E79
2E39
2HMP
2HVB
2H02
3HMD
3HT8 3HP5
3HR0
3H68
1M01
6E45
3HRJ
3HRC
3HR3
2HVD
2H25
7HM1
3H00
CU71
1000
3HME
3H67
2AC0
9E32
9E34
2HMJ
2H06
2CBL
3EC5
2E88
2E01
3E98
2E72
1E10
9H27
3HB1
3CA9
7E09
6E03
3E37
3CHB
3CAA
2CBM
1002
9EA5
3H18
2HVE
2HM8
3HMV
2HM1
7HV0
2HM5
2H26
2HM3
2HMT
2HVC
3HMU
3HMZ
7H01
3HMC
2C45
2HYC
3ECS
6E21
7HM2
2HM4
2FHL
3E22
2E04
6E09
2E91 3E27
3E07 2E06
2E97
1E31
3E26
3E19
1009
3EA7
2E80
2E50
2E51
2ECE
3EB3
7E05
6E37
7E14
6E08
3EA9
3HMB
1HV9
3CH9
3CHG
3CHF
1022
3EB0
3E00 2E25
3E67
2E38
3E97 2E93
1250
9H26
9H25
7CH1
9CH0
BCG0
7CH0
3CAC
2CBN
BCG2
3CHA
3E11
6E22
3HML
2HM2
1C00
3CAD
3CAB
2CBP
BCG1
2CBK
BCG3
2C03
3E30 3E15
2E10
3E18
2E30
1023
2E90
3E12
6FH1
3H71
2CG2
3CAE
2CBR
2CBS
3CFK 3CFL
3ECE
3ECF
2E70
3E24
2E29
3E63
3E31
1015
6E07
1024
6E12
3E06
5FH0
3HMA
6CG2
6E14
3E88
2E24
2EAB
2E18
3E32
1E12
2E15
6E23
3E14
2E31
3E34
3E21
2E32
5E00
9EA3
3E44
3E43
1001
3E28
9E23
6E10
2FLD
6FH2
3ECG
2ECB
2E95
6FH6
6FH3
2ECC
9E30
1014
6E02
2E82
1025
6E29
3E39
9E25
7E01
6E48
5FL1
5FL0
2FLE
6FH0
2FHA
1028
9EA1
5E03
3E68
3E57 3E87
1E18
6E26
2E33
3E17
3E16
3E93
9E20
3E38
2E14
9E24
1027
9E152E16
3E02
9E12
2FLH
2FL2
2FLP
3FLG
3FL1
3FL2
3FL3
3FL4
3FL5
3FL6
3FL7
3FL0
6FH7
2F43
3FG1
3FG3
9E33
6E24
6E38
3E96
3E95
2E71
3E86
9E22
2E17
9E16
9E17
1255
6E28
1E13
2E92
1E01
1R07 1R08
3E51
2EA4
6E34
3FGA
3FGE
3FG9
3FG8
1G51
3FG2
3FG4
3FG5
6E36
3E85
3E23
2E03
1E19
2E12
9E279E26
3E61
1E02
1E03
6E52
3E09
2E09
2E20
1E22
2EA5
2E67 3E92
2E68 3E36
1E04
3E33 3E60
6E47
1235
2FLF
3FG6
6E30
6E40
7E10
9E009E11
1026
6E32
1E23
3E54
1E16
9E18
9E19
3E59
2E44
1E25
3EB7
9E10 3E45
3E69
3EAT
7E04
6E04
2E11
6E15
6E05
6E16
2E273E10
1E26
2E19
3E55
6E35
2E96
3C41
2FL1
3EB6
3E73
1013
3E64
7FL0
1E24
3E53 3E48
2E34 2E28
3E50
3FGB
3FGC
7FN0
3E62
1E27
6E31
2E13
1011
1F10
3FLK
3FLH
3FL9
3FL8
3FLA
3FLB
3FLE
3FLD
3FLC
3FLF
3FLL
2FL7
2FL6 3FLJ
2E41
2EAA
5EA1
2E74
3EB8
3E52
6E51
1246
9E06 2E05
3E58
9E04 3E29
3E56
7F54
3F72
2F61
3F68
7F56
3FH8
6F82
6F83
6F84
6F85
3FF4
3FFH
3FF7
3FFC
3FE3
3FE6
9E31
2ECH
9F07
7F51
3FF9
2F74
3FFW
3FE0
7E19
3E20
5E06 2E08
6E46
2F57
2F60 3F69
3FFA
3FFT
2F54
3F71
3F73
2FJ4
2E07
3ECN
3ECK
3FF6
3FF8
3FFB
3FF5
3FFP
3FFL
3FFE
1F51
3C19
CC60
2FJ5
IF33
2FJD
3FH9
2FN9
3C24
3C29
3C34
3C33
3C35
3C36
3C14
3C15
3C18
3C16
3C17
7C00
3FHB
3C95
3FH4
IF32
3FH5
2FJ3
5F02
3E46
2E46
3E82
3E90
3E41
9E35
1E51 1E50
3ECM
2E65
3E03
3E01
3E05
9E01
9E02
2E49 3E25 2E21
1F02
3E72
6E53
6E18
2EB3
3ED3
3EB9
1241
2EB4
2E52
2F09
2F10 1F00
IF35
2FNA
1240
6E11
3E42
3E89
7E03
3F57
3E35 2E64
9E29
9E37
6E13
3E04
3F56
3E70
6E17
3E65
3E13
2F53
2F55
2FJ7
3F51
3E71
IF34
3CD0
1016
1E07
2F34
2F35
2F52 2F51
3F59
3E47
6E25
9FH0
2E26
3ECP
2F50
2FJ6
5F03
2E99 5E05
7E18
3ECL
3F06
3F11
6F51
9F04
2F02
1E05
9EA4
5FC9
1F01
IF36
IF39
3E40
3E08
7F01
1R12
1012
2E73
IF38
7E20
2F01
1029
IF37
2E22
9F05
7F00
3C09
5FC8
3F80 3F79
3F40
3F00
3C07
5FC7
2FND
2F28
3F20
3F21
2F29
2FNE
5FC6
5FC5
9FA2
2F06
3F17
2F07
3F18
3F19
2F08
9FA1
1F29
9F14
9F16
2F00
9F18
9F12
3F02
3C05
6F13
7F08
2F49
9F15 9F11 9F10 9F13 3F24
9F09
7C01
3C08
3C28
3C11
3C06
3C03
3C25
3C12
3C30
3C26
3C13
1G50
3C42
3C31
3C27
2CBY
3CA3
3C32
7C02
9CG9
3CA2
3F36 2F46 3F383F39 2F47
3F37 9F17 9F19 9F20
1242
2EAE
1F53
1008
1R20
1FA0
3F30
2F41
2F42
3F31
1FA1
3F29
2F40
1M59
3F01
7F55 7F52
1M71
2F48
1F05
1E06
Layout Small Signal Board (Top Side)
3P81
7P15
1M97
18310_554_0900309.eps
090309
3104 313 6343.2
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 138
2E77
FEA8
3C38
2C19
2C29
2C30
2C55
2C83
7CG5
3CGR
3CGP
2CGC
3CH5
2CGD
7CG6
2CGB
9CG7
9CG8
7CG4
FCA9
2CH5
FC08
9CA3
9CA2
9CA4
9CA5
9CA0
3CD3
5CG3
5CG2
FCG8
1C02
3CH2
FCG1
5CG0
2CBH
BCG6
2CBE
2CBD
2CAT
2CAS
3CA5
3CA4
FCBN
FCAT
2CBJ
3CD2
5CG1
3HJ3
3HJ4
ICAE
3A19
3A06
FA35
IA24
FA31
FA34
FA30
3A00
3HH9
3HGY
3HGP
3HGS
2HH5
FC19
IA13
2A24
FA32
3HGV
3HH4
3HHA
3HH6
3HGZ
2A23
6A01
3HKM
2HGF
2HGE
2HG6
2HG7
2HGC
2HGD
2HG8
FC12
2CH0
2A52
FA36
2A28
2A29
2HG4
2HG9
2HGA
2HGB
2HG0
2HHM
IA25
2HG3
2HG5
3HH1
3HH8
3HH7
2H29
2A30
3HGT
3HGR
3HGU
3HGW
3HH3
3HH2
3HH0
2HHK
2HGG
3HJ2
3HJ1
3HF2
5HVB
2HVK
2HVU
2H24
5HVD
2HZK
2HU1
2HY5
2CH4
2CH6
2CA2
2CA3
2CBG
3CH7
2CG3
CFH1
FFH1
2HF7
3HFH
3HF4
3HF9
9H18
IH05
2HY8
5HVC
2HHB
3HFM
3HFN
3HFP
3HAH
IHK4
2H41
2H38
2HVL
2H22
2HZE
7HP0
2HPA
3H33
3H09
3H38
3H45
3H37
2H40
2H39
5HP2
5HVG
2HVP
5HVF
2HU3
2HVN
3HP9
2HP5
2HP6
2H23
2HUA
2HY6
2HY7
3HFG
5HRZ
IHSV
5HY7 5HRW
2HP8
2HZH
5HY4
2HZV
2HRN
7A02
9HF4
IA10
2A02
2A21
2A06
3A01
3A09 3A08
3A11
2A10
IA01
FH11
5A00
IA28
5A01
IA07
FA06
7A03
2A50
FA37
2A15
2A16
FA04
IA20
2A07
3A23
3A24
3A25
2A03
3HHE
3HKN
3HHB
2HGM
3HHJ
7A07
3HHD
3HHC
3HHF
2HH3
2HGZ
2HGH
2HH0
2HGU
2HGT
2HGP
2HGW
FA33
2HGV
2A01
2A04
IHYP
IA11
IA08
3A10
3A26
3A27
3HHV
3HHG
2HVY
3HHY
3HHZ
FA02
IA02
3HHW
3HHS
3HPT
2HGR
9HF7
3HPS
2HGK
2HGN
IA09
7A00
3A12
2HGY
2HGJ
3HHN
3HHK
3HPH
3HPV
3HSW
3HHT
3HHU
3HEU
FH04
IH10
IHYN
5HV8
9HF6
2H13
9HF5
3HK0
2HV2
IHY0
5HYB
3HS6
3HPK
IH30
2HGS
3HPF
3H49
9H20
3HPD
9HW1
3HPG
3HPU
IHF1
2HH1
2HH2
3HPM
2HHP
3H50
9HW2
3HPE
2H18
3HPJ
2HVW
IHF2
IHSM
3A07
IA03
2A20
IA30
3HHM
2HHN
2H33
2HZL
2H35
2H19
9H21
2HVV
2HU2
2H15
2HV8
IHY8
2HV7
3HHH
FH05
IHYA
2HV9
3HHR
3HHP
3HP8
3HWP
2A22
IHG0
3HJY
3HJ5
IHF7
5HV9
3HPC
IHY4
2H34
3A16
2A05
3H62
2HV3
5HV1
5HV0
2H37
9HW0
IA21
2H16
2HZM
IHF3
2HVF
2HY2
3HWK
3A05
3HPL
IHYH
5HV6
2HY3
2H14
2H17
IA23
2HH4
3A18
FA03
IA22
3A04
3A03
IHY3
2HZD
2H27
5HV7
2A09
3HJ0
2H28
2HY4
2HYA
5H50
2H51
FC13
ICH5
9CA1
9FG4
7HF1
2HRT
2HVS
5HY2
5HY6
2H30
IH12
BCG5
3H74
IHS0
2HRU
3H11
2HYF
IHYM
5HVA
IHRC
IHK2
3HH5
2A08
IT05
2CAV
2HG1
2HHA
2HVZ
FT23
FCAW
3CHE
2HU6
2HU4
2HYE
2HUK
IHSB
IHS3
FH07
IHSK
2HH6
2CAW
FC14
3CHC
ICH8
3HES
IH26
IH50
IT03
2HY9
2HZC
2HV6
5HV5
3HSK
3HRN
2CAY
FCAV
FC15
IHWF
2H20
IHYF
5HV3
IHRK
3HRM
2CB1
2CB0
2CAZ
FCAY
IA12
IHSE
IHS2
IHR1
IHS6
2H43
7H06
FT22
IHRM
FCAZ
FH06
2HG2
IHK3
2HZG
2HVH
2HKL
BE20
IH60
2H42
5HV2
IHSG
3HRK
2CB2
FCB0
2CG1
3CHD
ICH7
IHSN
2HZB
5HVH
2H32
IHV3
3HT9
9H19
2HZF
IHW0
2HTK
3HS7
2CB4
2CB3
FCB1
FCB2
2HF6
5HG0
2HUP
3HS5
IHRD
IH04
IHPG
2HYB
IHV6
2HST
IHRF
IT11
IHSD
2HV1
2HT6
2HSV
IHS5
3H57
2CB5
FCB3
2HH9
5HV4
IHSH
2HSY
IHR6
IHRE
IHRB
3H55
IH17
2HVR
5HVE
IHY9
FHK1
9H54
IHSC
2H31
2HT5
2HUN
3H86
9H52
2HT7
2HS0
IH61
IT28
IHW1
IHF6
2HTH
2HV5
2HA5
2HU8
IP19
IH16
2HV0
2CB7
2CB6
FCB4
FCG0
ICH6
2HF5
3HFK
IHF0
3HPP
IHK1
3H63
2H21
2H50
IHSA
2CB8
FCB7
FCB8
FCAS
3HPR
IHYC
9H50
2HU7
2H03
BE22
2HU5
2HA4
IHSR
7H16
IT15
IT09
2HT1
2HVJ
IT04
FHC3
3H27
IH44
7H11
3H44
3H78
IT10
IHPF
IH08
9T14
IT14
IH80
IH38
7H14
IH14
FT17
2HSW
2HA3
IHR4
IH20
2HVM
5HY5
FHR6
IHVE
IH49
IHR0
IHR3
6HW2
IT13
FHR5
FHR1
IHST
IH92
7CG1
IHY5
IHSP
IHR5
IH39
IH19
IT0D
3HFY
IH81
IHS8
IHS4
IH35
7H93
IHW5
IHY7
2HD0
IHFA
IH40
IHSS
FE21
IHF9
IHR8
IH34
3H41
IHF8
2H52
6H10
2H11
IH18
2HRP
3H08
2H10
3H06
IH07
IH33
2HU9
2HVT
IHW4
3H23
3H16
3H15
3H43
IT08
3H14
IHW2
3H13
IH36
IHWA
3H10
3H19
2CB9
FCBA
FCB9
FCG7
IHWM
IHFB
IH28
3H20
3H17
IH85
IHD0
IT30
3H26
IHW6
3H42
IH87
IHWB
3HFR
9HG3
9H17
3HP2
IHSL
IH41
IHF5
IHS7
IHF4
IHSW
2HZY
3H30
3H39
3H21
IH45
IH42
IH46
FHD1
5HY3
IHSU
3H48
2H00
FHD2
BE21
3H46
IHSY
IH13
FH03
2H36
3H28
3H32
3H01
FHD0
3HD4
IH91
IT12
IHWH
IHWD
IH09
AT11
IP13
IHWG
FHPE
IHY6
2HV4
9T62
9T64
2T67
IH15
IH00
3H51
2H07
IHW3
IH21
IHC2
IT88
3T66
FH01
3H69
FHC6
IHY1
3H66
3H60
9H51
5T53
FH09
IT86
2HRY
3H65
3H03
9H53
2T80
FT58
FT52
FT25
2HRV
3H02
IHWN
3H54
9H55
2T51
2T66
2T75
2T76
1T50
FT54
3T59
9T70
FT51
9T71
FT24
FT53
IT51
IT60
3T61
2T57 2T58
IH03
IH43
3T67
7H02
IH32
2HP7
3H56
IH37
3H31
3H07
2H12
9T22
2T55 2T56
IH06
IH01
FHC2
IHC1
3HC2
FT50
2HC0
AT10
FE56
2HPB
2HRW
FHC1
3H53
7HC3
FT57
IHRL
3H52
FHC7
3T51
IHPD
7T50
IT53
IT61
IT50
IHY2
2H01
IH02
2T79
IT69
9T34
IT36 9T45
IT17
3HPW
IT59
IT58
IT55
IT57
IT16
FH00
3T81
3T80
FT55
AT50
IT56
9T33
2T19
3T53
3T55
2T20
IT34
IT32
IH11
IHWC
IT94
2T77
IT63
ICH9
IHMG
3H94
2HP4
IHSZ
2CBA
FCBD
FCBC
FCBB
IH55
IHRH
2HRM
2CBB
FCBF
FCBE
9CG1
FC16
1C01
IH52
IHN4
IH22
IHN3
FHV3
9H15
5T50
5T52
2T50
2T21 IT23
3T98
3T18
IT76
2T59
2T53
2T73 2T52
7T10
3T50
3T54
IT26
9T43
9T44
IT21
IT62
2T68
2T81
2T82
2T54
3H76
IHM6
3HAG
3HPB
9H14
AT51
5T12
IT73
IT20
2T18
2T17 2T15
2T13
9T32
IT19
3T19
IT70
IT75
IT25
2H04
3H77
2HYD
IH23
3H70
FH08
7HC4
9T31
2T16
IT24
IH54
3HPA
IT93
2T64
3T52
IT80
IT77
IT95
3T92
3T82
FCBG
9CG0
FH50
IHM1
IH47
IH24
IHND
2HRS
7T55
2CBC
2A122A11
IHRU
IT89
7T54
FT63
FT60
5T54
FE17
FT21
IH25
IHRJ
FCBH
3H75
IH53
IHRY
2CBF
FCBJ
IHMW
IHRZ
FT20
2T74
IT22
BE25
IHS1
2T72
2T71
2T70
FT59
2T24
5T51
3T17
FT18
IT81
IT83
IHWE
IHRV
3HP4
IT84
6T51
2T69
2T78
3T68
FT56
IHNF
IH27
IH48
2T83
IT96
IT97
CFH0
IH51
IHVA
3HP6
2T85
FCBM
FCBK
6CG0
FCB5
IHNK
IHWL
IHV1
FCD3
2FHT
IHN0
IHNH
IHW9
IHRT
IHRW
IT65
IT66
3T57
3HP3
IT91
3T93 3T94
3T69 3T87
3T58
3T90
IT79
IT67
3T89
3T86
7T56 6T50
FT61
3T88 3T91
IT98
3T84
3T83
2T84
FE23
IT90
FHM3
IHNB
2FHM
3CGZ
2C64
2C73
2C96
5C61
3C50
FCD1
FCD4
FCD9
IC50
2CG6
2CG5
ICG2
FCD2
3CD8
3CD9
ICD8
ICG3
3CG1
2C71
ICGW
IC54
3C51
FCD6
2CG7
3CG6
IC81
FCD0
3CD7
3CF1
2CG8
3CG7
3CH0
FCB6
7HM4
3HV4
9FN4
3CG0
2C75
3CA7
3CG8
ICGY
2C81
2C62
IC82
IC83
2C72
2C68
3CDC
3CDD
IC51
3CDB
9C10
FC17
2C70
5C62
5C63
2C78
9FG6
3CFN
2C63
2C80
2C59
9C11
2C91
2C92
3CA6
ICAA
7CJ0
3CJ0 6CJ0
ICA1
ICA2
3CG9
7CG0
2C79
FCJ4
IC90
IC85
3CH1
IC80
2C95
ICA9
2H05
IT68
IT85
FT62
2HMZ
IHMV
9FN7
FCJ5
FCAB
ICG1
3CG5
5C65
2C61
7CG2
ICG5
3CJ1
2CD1
FC10
2CA1
2CA0
3CGA
2C76
2C77
5C60
ICG6
2CH7
5C70
2C89
2C86
2CG4
9C31
2C97
2C66
2C67
2C88
5C68
IC88
2C69
ICG4
IC01
2C00
5C64
2C60
IC84
5C67
2C94
2C82
IC87
2CA4
9C32
FCA0
5C66
IC86
IC04
2C74
2C87
2C57
1CD0
9FGB
2F73
FCA1
2C84
2C85
7CD0
FCG3
FC06
3C01
3C00
2CA5
FCA3
3C21
3C20
3A22
3HMM
IHNE
FHR3
IFNN
FCAD
ICHB
5FG1
FCA2
ICGV
7CG8
2C58
IC89
2C01
2C90
2CA6
2CD0
5FG2
2CA7
FCG5
FCG2
ICGZ
FCD8
FC07
2CA9
2CA8
FCA5
3CGF
FCA4
3C40
2F72
2F85
2CAB
2CAA
FCA8
FCA7
3C10
2F68
2F69
2CAC
FCAC
FCAA
FCA6
3CD1
IHW8
3H35
FHM0
FHV4
3HMY
IHNA
IE72
FHV5
IFNK
FCAE
FCG4
ICGA
2CG0
IHW7
IHM7
BE24
2HVG
7HVA
2HMW
7HM6
IHN6
7HM3
IHWJ
IHM8
FHM1
FE43
IE16
IH31
IHNG
IHN8
3HMW
IHM5
IHM4
FE50
IHM2
3HM1
7HM5
FHM2
IHM0
IHNJ
6HM0
3HM0
IE58
2HMG
3HMF
9HM0
IH29
FFH0
FE22
FE20
9FN0
FCAF
2CAD
3CGG
5C69
FFL2
IFNM
3FH3
2CAH
2CAG
FCAG
3CGJ
ICG8
IFNL
3FH1
3CGN
2C38
ICG7
2C65
FF04
FFL4
9FG3
9FN1
3FH0
FFH2
2CAJ
2CAF
2CAE
ICG9
2F64
2F65
2FN8
3FH2
2FHR
BE23
3CGV
3C37
3C04
FF02
3F03
9FNB
IF02
2F24
3F26
IFNB
2CAK
FCAN
FCAJ
2C18
9CD0
9FN6
FFHT
3C39
2C34
2C16
3C22
2F21
3F13
9FNC
3F25
9FN9
9FNA
IFNA
2CAM
2CAR
2C33
2C32
3CDA
3FH6
IE31
7C03
2C04
2C13
IF00
2F16
2F31
2C35
3F41
FFA7
3FA5
3FA6
2FA6
9F21
7F05
FF54
FF11
9FN8
5FH3
2FJ1
9FND
3FH7
IFNJ
FFH4
2FJ2
2CAN
2CAP
FCAR
ICGH
FCAM
2C02
ICH4
FF08
9FG2
FE42
2FH4
IFNH
3FNG
IFNG
ICGN
FCBR
3CGH
FFL3
2FHJ
2FHE
2FHF
2FHV
3FHL
2FHP
2FLN
IFNF
3CH3
2CBZ
FCAH
2FH7
2FH6
2FLM
IFND
2FN0
2FL5
3CGS
FCAK
9FGC
2FHK
2FHC
FF18
2FH0
2FH1
2FLB
2FLA
2FLC
2FHD
2FHW
3C43
ICHA
IF16
2F80
2F81
2F82
2F83
2F84
2FHZ
IFN9
2FHH
3FNF
BE27
5FH4
FFHA
2FJB
IFN8
2FLR
FFHG
FFHF
IE66
2FN5
2FLK
2FL4
IFL1
FFHC
FFHE
FFHD
3CGT
ICH3
3C02
2C15
2F77 2F75
2F76
2F78
2F79
IFN7
2C44
2FHG
FEA1
IE97
IFN6
2FH3
2FH8
2FN6
2FN3
IEC2
BE26
IE67
2FN1
2FLL
2FH5
FE60
3FLN
3FLM
2FN2
2FL0
IFC5
FE70
IFNC
FFL0
FFHB
FE71
IFN3
FCG6
ICGK
ICGM
FCAP
ICH1
IF15
IF17
2F70
2F71
9FGA
IFN2
2FJP
3FHJ
IFC0
FE61
IE22
FE24
FFHH
6FH8
7FH2
IE34
IEC1
2F66
2F67
3CH4
3C44
9FGD
2FH2
3FHM
FF15
IEC3
FE12
IE20
IEC0
FE73
IFH4
FF16
2F27
9F22
3F15
IFN5
FFH3
2F62
2F63
2C43
2C36
2C42
9FG7
2FLJ
2FLS
9F03
9F08
9F06
9F00 3F07
9F01 3F08
9F02 3F10
2F03 3F09
3FN2
2FL3
FFHL
FE53
FE62
2F22
2F23 3F14
2F39
2F12 2F38
3F16
2F25
2F37
3F85
3F84
3F83
3F82
5FH2
FF19
2FH9
FFL1
IE21
FE72
2F13 2F36
3FN3
IFN0
IFN1
IE14
FE14
FE10
FE11
FF10
2C41
FFHM
2FN7
FEA0
IEC6
IE23
2F33
FF06
3F28
FF48
2FL9
9CG4
FCBP
FF03
3FHG
FFHP
IF62
IEC7
3F22
3F23
FF07
FF14
FE27
BE28
FE25
FF30
FF13
FFHJ
3F64 9F51
IF64 9F50
3F63
FE68
FF09
FFHN
ICGP
ICGR
2C39
2C56
IF18
IFN4
3F74
ICH2
FCJ0
IC03
2C17
IF09
9FG8
IF61
IF69
2F14
2F32
3F27
9FG9
3F61
3F62
5FH1
3F67
IF20
3C23
9FG5
FE74
IF66
IE29
FE63
FE31
FE30
IED1
FE18
IF58
FF05
2F04
3F12
IF19
2FJC
FE75
IEB5
IF07
2FJ0
FE64
IF01
2FJA
IEB4
FE15
9F52
3F65 2F58
IE57
FE49
IE18
IF14
3FN1
FE65
IEC8
FE87
IF63
3F66
FFHK
7F50
FE80
IEB1
FF52
IF13
IC02
2C14
2FJ8
IE68
IE35
IF65
IE05
FE69
IEB0
FE86
IF57
FF01
FF00
7F06
2F17
FF21
IF21
2C40
FFHR
IF60
2F59 3F70
FE34
FFH5
IF59
2EAC
2F56
FFH6
3FHK
2EAD
IEC9
IEC5
IF53
IE01
FE66
3F60 6F50
IED2
IE11
IE79
FFH7
IF68
IEC4
FEB4
3E83
3ECQ
FE88
IEA8
FE48
IE48
IF54
IF12
FC05
FF12
FFH9
3F50
IF67
5F04
IF08
1F03
FF53
IF52
7F53
IE76
2FJJ
FE99
FE59
FFH8
IE15
IE02
IFA8
IF29
FF22
2F30
2F26
3FAB
2F18
FFHS
IE26
3F54
3F55 3F52
BEB2
IE33
IE17
FE95
7F57
IE24
IE62
IE08
FE67
2E62 2E63
2E61
FE93
IE27
FE76
IE06
FE81
FE82
3FAA
IFA9
FE47
FE92
FE51
FE33
IE09
9E09
IE12
FEB6
FE89
6E19
3E84
3EAC
3EAA
3EAB
FE90
FEC0
BEB1
FFA9
FF17
5F05
IE81
6E50
BEB7
IE25
7E17
9E41
9E08
9E03
IE51
IEA4
9E40
FE39
FE35
BEB9
3EC8
IF56
FE45
IE82
IE95
BEB8
IEA2
IF55
FE83
9E05
IEA3
IEA5
BEB0
FE78
FE36
BEB6
FE94
BEB3
2E60
IE84
2F05
FE54
FE57
7FH0
IE92
9EA7
IE78
3EC7
3EAV
FE32
FE77
IE75
9E36 3E91
FE84
6E27
IE03
3ED2
FE96
FE44
IE93
FE41
BEB4
2ECF
FE79
3F58 3F53
IF50
6E54
FE85
IE91
3EC6
IEA7
FE19
FE40
IEA6
FEB8
IF51
IE32
IE98
7E15
2EA6
2EAQ
9EA2
FEB7
FE91
IE10
FEB2
IE19
2FJK
FE16
2FHS
FE52
2FA7
5F06
FFA8
FF20
2F19 2F11
2FJ9
FE58
FE13
IED0
FE38
BEB5
FFC2
7F07
FE55
FE37
IE99
FE28
FFC3
FF51
FE26
IE04
IE94
FEB5
FFC4
IFC1
1F50
FFC5
FF25
FEB9
2FHB
7E02
IEA1
IE38
FF49
FEB3
3E99
IE96
FF50
FEA6
2F15
2F20
FEB1
FEA7
3EA6
FE98
FE29
FF40
FF43
2FHN
9E28
FEB0
IE61
IE70
FF41
FF44
FF31
FEA5
FE97
3EB1
2E78 3EA5
2E79 3EA1
9E07
IE60
FF23
IE07
7E16
FEA9
3EA2
7E06
FF42
FF24
IE13
3EB4
IE90
3EB2
2E75
2E81
2EB1
3EA3
IE89
2E76
5E02
3EB5
9E21
Layout Small Signal Board (Bottom Side)
IAC4
IAC3
FAC0
IAC2
3A20 3A21
3A02
FN05
2N10
IP20
3P33
IU45
3U1V
2U56
2U55
7U09
2U59
3U24
IU62
FU0C
IU11
2U50
3U21
2U61
FU21
FU1D
IU60
FU22
IU63
IU1T
FU1C
IU1P
6U02
3U06
FU20
IU59
FU1B
FU23
1N02
2N32
FU0E
FU1A
FU07
FP33
FP15
FP0G
FU10
3U23
IU0P
2U58
IU57
IN0Z
FU11
FU04
2U62
3U18
IU0U
FN0B
IU19
IU58
2U54
2U57
IN10
3N0K
IU0K
3U22
3U09
2U63
2U60
3U16
3U19
3U25
2U64
2U0B
3U0A
2U0D
3U0G
3U1D
CU77
IU0S
3U30
IU30
IU0N
3U15
FU12
3U17
6N01
IU55
IU06
IU0T
3U13
6U03
IU56
2U65
3U31
3U75
FU0B
IU31
FN0A
6N00
3U20
2U39
5N06
IN0W
FU06
IU61
FP32
FP0H
FP09
3U35
IU20
FU32
FU0A
2U0S
3P17
2N0Y
3N0W
2N0Z
3N0J
IN0Y
2N31
2N0L
2N0Q
2N0P
IN0L
2N0K
IN21
3N30
3N0V
3N34
IN32
7N12
FP0A
IP00
3N33
2N30
2P04
3P25
7N10
3P26
3P24
IN30
2N17
3N0H
IN0M
FP34
2N16
3N32
IP15
FP16
5N07
FN08
IP04
2N0V
IN22
2N0N
2N0W
IN0U
3N0F
FP0B
3N31
7N11
2N15
3N0T
FP35
3N0L
FN15
IP28
2N0R
3N0N
6P06
IP60
3P10
FU30
IU1E
IU07
IP24
FN0C
IN0P
IP14
FU31
IU3C
IU12
FU1F
IP27
IN20
FN06
2P23
FU33
IU41
IU43
FU05
FN07
3P47
IU51
IU42
IU40
IP29
IP23
2P40
FU35
FU34
IU34
FU40
IU44
3U0F
IP11
3P20
2U07 2U0T
2U0V
2N14
2N33
7N13
6P03
IP18
FU36
IU52
3U59
IU49
IU47
IU1R
3P19
FP04
IU53
IU21
IU50
IU48
2U0U
2P19
FP43
IN34
3P09
FU38
IU3T
FU08
3P55
FP40
2A26
3U37
2N0S
IU54
IU1D
2N11
5P12
2A25
IU35
2N0T
IP30
IP10
2U16
2U17
3P56
IP0H
2N12
2P52 2P54
FP23
2P43
2P44
7A01
FA01
FU1H
IN35
FP26
5P15
3P43
2P48
2P36
FP42
2A14
2A13
2A27
FN09
2P37
FP21
7P01
2P18
3P61
3P58
2P32
IP5V
5P08
FP39
FP14
FP22
9P0J
7P11
2P42
2P45
FP24
IP5Z
2P21
2P22
FP25
3P67
3P68
3P38
IP5U
IP5Y
9A01
IA26
2P33
FP20
FP0T
3P75
7P32
3P65
3P66
2P502P39 2P38
2P51
IP32
2P34 2P35
FP0W
2P53 2P463P14 2P41
FP41
IP17
FP0S
FP19
5P11
FP2A
FP0U
IA05
2N0U
3P49
IP26
FP17
IP31
7P13
3P46
3P52 3P50
3P51 2P20
FP03
2P25
3P54
FP44
3A15
3A14
IA06
FP18
7P12 3P53
FP01
2P55
FP0R
IA27
7U03
IP06
6P01
2P06
9A02
3P05
2P07
2P10
6P02
3P07
2P30
FP02
IA04
2A51
3P23
2P08
3P06
5P10
FP27
2P11
3P08
2P09
IP12
3A17
2A19
IA29
2A00
FH12
IP07
FP28
9A00
FP29
3A13
FP45
CH53
3U0J
3U1M
FP31
2U12
IU08
2U0H
IU1B
FP08
FP0F
3D17
FP30
3D16
ID11
IU37
2U28
IU38
3U40
3U3Y
3U47
ID12
IU36
7U0P
FU87
IU29
3P84
ID07
FU00
FD02
FD05
3U42
2U8R
2U38
3U33
3U08
3U10
5D08
3U07
IU25
2U81
2D25
5D09
3U03
2U09
2D27
FP36
2D21
3D10
3U02
IU04
3U05
FU16
2U37
FU90
3U01
IU2A
FD06
2U13
3P85
3U14
ID08
ID05
FU17
IU02
3U00
2U03
3U04
2U66
IP09
7U01
IU13
6U01
FP00
3P27
IU14
2U04
6U00
2U02
IU03
ID09
FU18
2U80
IU01
ID31
3P86
2U8Q
3U12
2U83
5D07
ID32
2P16 3P11
FU15
FU8B
3U27
3U3N
3U2C
2U05
IU10
IP03
FU24
3U2H
2U18
2U20
IU85
3U3G
3U26
3U3F
2U8V
3U2D
IU09
IU2Y
3U2F
3U32
FU8C
3U2G
ID10
FU25
IU2Z
IU00
IP05
3U3J
IU82
IU2D
2U8Y
IU2V
CD10
2U8U
7D10
IU2C
2U8T
FU26
IU3B
FU0D
CU25
IU32
IU15
3U3A
FU39
FP0P
2U08
ID27
ID29
IU33
3U11
ID06
ID38
FU85
3P13
FP0J
FU14
ID30
ID28
FP05
2U2A
ID18
FP0C
6U0C
IU39
7U0Q
3P12
3U43
FU1G
2U67
ID33
3U3Z
ID37
ID19
6U0B
7D03
ID16
ID36
FP13
IP02
2U27
2D22
2D26
FD14
3D14
FP10
3U44
9P32
IP08
3D09
2U29
FP06
2U2B
FP11
FP07
3U45
FP12
FP0E
IP01
3U28
FU13
FU19
IU28
IU05
IU2T
IU16
FU8D
FD07
2D01
FP37
FU80
3D03
FP38
3P88
18310_555_090309.eps
090309
3104 313 6343.2
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 139
Light guide
1
2
4
3
5
6
8
7
11
10
9
13
12
A
A
1
B
2
3
4
5
6
7
8
LIGHT GUIDE
C
A
A
WHITE
D
3009
LTW-M670
6009
3008
150R
150R
B
I010
LTW-M670
6008
3007
150R
I009
LTW-M670
6007
3005
LTW-M670
6006
3004
150R
150R
I008
I007
LTW-M670
6005
3003
150R
I006
LTW-M670
6004
3002
150R
I005
LTW-M670
6003
3001
150R
I004
LTW-M670
6001
E
I003
LTW-M670
I002
6002
3000
150R
100u 16V
B
100n
2001
RES 2002
+5V2
I001
1P09
7001
BC817-25W
1K0
3016
C
3015
+5V2
1735446-4
RES 10K
F
1
2
3
4
I000
1P09 C1
2001 B4
2002 B3
3000 B4
3001 B4
3002 B4
3003 B5
3004 B5
3005 B5
3007 B6
3008 B6
3009 B6
3015 C3
3016 C3
6001 B4
6002 B4
6003 B4
6004 B5
6005 B5
6006 B5
6007 B6
6008 B6
6009 B6
7001 C4
I000 C3
I001 C4
I002 B4
I003 B4
I004 B4
I005 B5
I006 B5
I007 B5
I008 B6
I009 B6
I010 B6
B
C
D
E
C
F
G
G
D
D
H
H
1
2
3
4
5
6
7
8
I
I
CHN
SETNAME
2K9
1
CLASS_NO
2008-10-16
LIGHT STRIP PANEL
J
2008-10-17
3
NAME Luc Buffel
2
3
4
5
6
7
8
DATE
9
130
1
SUPERS.
CHECK
1
J
3104 313 6344
9 LEDS 2K9
C
10
A3
1
ROYAL PHILIPS ELECTRONICS N.V. 2007
11
12
13
18310_560_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 140
3015
6007
6008
3009
6006
3008
2001
3007
6005
3005
7001
6004
2002
6003
3004
6002
3003
6001
3002
3001
3016
Layout guide panel
6009
3000
I010
I009
1P09
I008
I001
I000
I005
I004
I006
I007
I003
I002
18310_559_090420.eps
090508
31043136344.1
2009-May-08
Circuit Diagrams and PWB Layouts
Q549.2E LA
10.
EN 141
Wi-Fi Antenna
3
2
4
5
6
A
A
B
B
C
C
1000
1
2
1000 B1
3
D
D
A
A
owner.
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
1
Layout Wi-Fi Antenna
E
E
3104 313 6328.2
1000
U.FL-R-SMT-1(10) 3 2
B
1
HOT
B
F
F
C
G
C
1
2
G
3
H
H
I
I
CHN
SETNAME
********
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CLASS_NO
WIFI antenna
******
J
**-**-**
*
08-07-07
2
08-10-20
3
3104 303 5212
NAME Maelegheer Ingrid
CHECK
1
1
SUPERS.
DATE
2
****-**-**
130
08-07-07
2
08-10-20
*
**-**-**
*
**-**-**
*
**-**-**
1
J
A4
ROYAL PHILIPS ELECTRONICS N.V. 2008
C
3
1
4
5
6
18310_640_090306.eps
090306
2009-May-08
18310_557_090309
090309