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Download Fujitsu CS90A User's Manual
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130nm node CMOS Process (CS90A) Features Technology Code Transistor Physical Gate Length (nm) Gate Oxide Thickness (nm) Supply Voltage (V) NMOS Ids (µA/µm) PMOS Ids (µA/µm) NMOS Ioff (nA/µm) PMOS Ioff (nA/µm) Gate Leak Current (nA/µm) Basic Gate Delay (ps) Number of Available Poly Layer Number of Available Metal Layer Via Filling ILD Structure SRAM Cell Size (µm2) Dual Gate Oxide Options Mixed Signal Options RF Elements Fuse CS90A UHS 110 2.9 1.2 780 -321 36 -18 0.01 14 HS 110 2.9 1.2 678 -276 4 -3.1 0.01 17 ST 110 2.9 1.2 570 -218 0.18 -0.22 0.01 28 LL 110 2.9 1.2 390 -150 0.005 -0.015 0.01 45 Mie plant 1 8Cu+1Al Cu Dual Damascene Hybrid Low-k 1.98 Available Available MIM cap., Poly Resistor, Inductor RAM Redundancy Technology Roadmap 1000 Physical Gate Length (nm) 500 180-nm Cu 130-nm Cu+Low+k 90-nm Cu+VLK 65-nm 45-nm CS80/80A 32-nm 200 CS90A 100 For ASIC & COT CS100A_LL CS90 CS100A_G 50 CS200A_LL CS100 For COT 20 G: Generic, LL: Low Leakage 10 1998 2000 2002 CS200A_G CS200 2004 2006 Year (Production Start) 2008 2010 2012 130nm node CMOS Process (CS90A) SRAM Transistor 1.65µm Cell Size = 1.98µm2 (1.2µm x 1.65µm) (2nd Generation SRAM) Interconnect Al Al Global Metal: AL (Fuse & Pad) Pitch: 1.8µm 7-Cu 6-Cu SiLK 5-Cu 4-Cu 3-Cu 2-Cu 1-Cu Semi Global Metal: Thick Cu + SiO2 Pitch: 0.6µm Intermediate Metal: Thin Cu + SiLK Pitch: 0.4µm SiO2 FUJITSU MICROELECTRONICS AMERICA, INC. Corporate Headquarters 1250 E. Arques Ave. Sunnyvale, CA 94088-3470 Tel: (800) 866-8608 Fax: (408) 737-5999 E-mail: [email protected] Web Site: http://www.fma.fujitsu.com ©2003 Fujitsu Microelectronics America, Inc. All company and product names are trademarks or registered trademarks of their respective owners. Printed in the U.S.A. WFS-FS-20983-7/2003
