Download Dataram DTM67207B memory module
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DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM Identification DTM67207B 256Mx64 2GB 2Rx8 PC2-4200S-444-12-F1 Performance range Clock/ Module Speed/ CL-tRCD -tRP 266 MHz / DDR2-533 / 4-4-4 200 MHz / DDR2-400 / 3-3-3 Features Description 200-pin JEDEC SO-DIMM Dual-sided assembly 67.60 mm [2.661”] wide by 30.0 mm [1.181”] high The Dataram DTM67207B assembly is a 256M x64bit Unbuffered non-ECC memory module that conforms to the JEDEC PC2-4300 standard. The DTM67207B assembly is Dual-Rank. Each rank is comprised of eight Hynix 128Mx8 DDR2 SDRAMs in 60 Ball FBGA packages. Operating Voltage: 1.8 V ±0.1 I/O Type: SSTL_18 Data Transfer Rate: 5.3 Gigabytes/sec A 2Kbit EEPROM for serial presence detect provides critical timing and configuration information used by the system to identify and configure the memory. Burst Lengths: 4 and 8 Programmable I/O driver strength (OCD) Programmable On-Die Termination (ODT) The assembly is a Small Outline Dual In-line Memory Module intended for mounting into 200pin edge connector sockets. Differential Data Strobe signals SDRAM Addressing (Row/Col/Bank): 14/10/3 Two Physical Ranks Fully RoHS Compliant Pin Configurations Front side 1 VREF 3 VSS 5 DQ0 7 DQ1 9 VSS 11 /DQS0 13 DQS0 15 VSS 17 DQ2 19 DQ3 21 VSS 23 DQ8 25 DQ9 27 VSS 29 /DQS1 31 DQS1 33 VSS 35 DQ10 37 DQ11 39 VSS 41 VSS 43 DQ16 45 DQ17 47 VSS 49 /DQS2 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Pin Names A1 VDD A10/AP BA0 /WE VDD /CAS /S1 VDD ODT1 VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Back side DQ42 2 VSS DQ43 4 DQ4 VSS 6 DQ5 DQ48 8 VSS DQ49 10 DM0 VSS 12 VSS NC 14 DQ6 16 DQ7 VSS /DQS6 18 VSS DQS6 20 DQ12 VSS 22 DQ13 DQ50 24 VSS DQ51 26 DM1 VSS 28 VSS DQ56 30 CK0 DQ57 32 /CK0 VSS 34 VSS DM7 36 DQ14 VSS 38 DQ15 DQ58 40 VSS DQ59 42 VSS VSS 44 DQ20 SDA 46 DQ21 SCL 48 VSS VDDSPD 50 /Event* 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD NC NC VDD A11 A7 A6 VDD A4 A2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A0 VDD BA1 /RAS /S0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 /CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1 Pin name Function /RAS /CAS /WE /S[1:0] CK[1:0],/CK[1:0] CKE[1:0] ODT[1:0] BA[2:0] A[13:0] SCL SDA SA[1:0] DQS[7:0] DM[7:0] DQ[63:0] /Event* VREF VDD VSS VDDSPD NC Row Address Strobe Column Address Strobe Write Enable Chip Select Differential Clock Clock Enable On-Die Termination Bank Select Address Input (Multiplexed) Serial Clock Serial Data I/O Address EEPROM Data Strobes Data Masks Data I/Os: Data Bus Temperature Sensing. Reference Voltage. Power Supply: 1.8V ±0.1 Ground Serial EEPROM Power Supply No Connects * - not used on the DTM67207B. Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 1 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM Front view 67.600 [2.661] 30.000 [1.181] 4.000 [.157] 2.150 [.130] 4.200 [.165] 20.000 [.787] 47.400 [1.866] 11.400 [.449] 2.540 Min [.100 Min] 63.000 [2.480] Back view Side view 3.50 Max [.138 Max] 4.000 Min [.157 Min] 1.000 ±.100 [.040 ±.004] Notes Tolerances on all dimensions except where otherwise indicated are ± .13 [.005]. All dimensions are expressed: millimeters [inches]. Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 2 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM 3 OHMS /S1 /S0 DMR0 DQSR0 /DQSR0 DMR4 DQSR4 /DQSR4 /DQS DQS /CS DQR[7:0] DM /DQS I/O(7:0) DQS /CS DQR[39:32] DMR1 /DQS DQS /CS DM /DQS I/O(7:0) DQS /CS DM I/O(7:0) DQS /CS DM DM /DQS I/O(7:0) DQS /CS DM DQS /CS DM DQS /CS DM I/O(7:0) DMR6 DQSR6 /DQSR6 /DQSR2 /DQS DQS /CS DM /DQS I/O(7:0) DQS /CS /DQS DQS /CS DM I/O(7:0) DQR[55:48] DMR3 DM /DQS I/O(7:0) I/O(7:0) DMR7 DQSR7 /DQSR7 DQSR3 /DQSR3 /DQS DQS /CS DQR[31:24] /DQS I/O(7:0) /DQS DQS /CS DQR[47:40] DMR2 DQSR2 DQR[23:16] DM I/O(7:0) DMR5 DQSR5 /DQSR5 DQSR1 /DQSR1 DQR[15:8] /DQS DQS /CS DM I/O(7:0) DM /DQS I/O(7:0) DQS I/O(7:0) /CS /DQS DQS /CS DM DQR[63:56] DM /DQS I/O(7:0) I/O(7:0) 22 OHMS DQ(63:0) DQR(63:0) DQS(7:0) DQSR(7:0) /DQSR(7:0) /DQS(7:0) 2 X 200 OHMS DMR(7:0) DM(7:0) CK0 SDRAM X 8 /CK0 GLOBAL SDRAM CONNECTS 5.6 pf 10 OHMS BA(2:0) BA(2:0)R A(13:0) A(13:0)R /RAS /RASR /CAS /CASR /WE /WER 2 X 200 OHMS CK1 /CK1 SDRAM X 8 5.6 pf 3 OHMS CKE0 ODT0 CKE0R RANK 0 ODT0R 3 OHMS CKE1R ODT1R CKE1 ODT1 SCL SERIAL PD SA0 SA1 RANK 1 VDDSPD V DD V REF V SS DECOUPLING Serial PD All Devices All SDRAMs All Devices SDA SA2 Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 3 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM Absolute Maximum Ratings (Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.) PARAMETER Symbol Minimum Maximum Unit Temperature, non-Operating TSTORAGE -55 100 C TCASE 0 85 C VDD -0.5 2.3 V VIN,VOUT -0.5 2.3 V DRAM Case Temperature, Operating Voltage on VDD relative to VSS Voltage on Any Pin relative to VSS Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Power Supply Voltage Symbol VDD Minimum 1.7 Typical 1.8 Maximum 1.9 Unit V Note I/O Reference Voltage VREF 0.49 VDD 0.50 VDD 0.51 VDD V 1 Bus Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V 2 Notes: 1. The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may not exceed ±1% of its DC value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(DC) Minimum VREF + 0.125 Maximum VDD + 0.300 Unit V Logical Low (Logic 0) VIL(DC) -0.300 VREF - 0.125 V AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(AC) Minimum VREF + 0.250 Maximum - Unit V Logical Low (Logic 0) VIL(AC) - VREF - 0.250 V Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 4 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER DC Input Signal Voltage Symbol VIN(DC) Minimum -0.300 Maximum VDD + 0.300 Unit V Note 1 DC Differential Input Voltage VID(DC) -0.250 VDD + 0.600 V 2 AC Differential Input Voltage VID(AC) -0.500 VDD + 0.600 V 3 AC Differential Cross-Point Voltage VIX(AC) 0.50 VDD - 0.175 0.50 VDD + 0.175 V 4 Notes: 1. VIN(DC) specifies the allowable DC excursion of each input of a differential pair. 2. VID(DC) specifies the input differential voltage, i.e. the absolute value of the difference between the two voltages of a differential pair. 3. VID(AC) specifies the input differential voltage required for switching. 4. The typical value of VIX(AC) is expected to be 0.5 VDD and is expected to track variations in VDD. Capacitance (TA = 25 C, f = 100 MHz) PARAMETER Input Capacitance, Clock Input Capacitance, Address and Control Input Capacitance Control Input/Output Capacitance Pin Symbol Minimum Maximum Unit CK0, /CK0, CK1, /CK1 CIN1 13 22 pF BA[2:0], A[13:0], /RAS, /CAS, /WE CIN2 16 32 pF CKE0, CKE1, /S0, /S1, ODT0, ODT1 CIN3 8 16 pF DQ[63:0], DQS[7:0], /DQS[7:0], DM[7:0] CIO 5 8 pF DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address ILI -80 80 μA 1 Input Leakage Current /S[1:0],CKE[1:0], ODT[1:0] ILI -40 40 μA 1 Input Leakage Current CK[1:0], /CK[1:0] ILI -40 40 μA 1 Input Leakage Current DM ILI -10 10 μA 1 Output Leakage Current DQS, DQ IOZ -10 10 μA 2 Output Minimum Source DC Current IOH -13.4 - mA 3 Output Minimum Sink DC Current IOL +13.4 - mA 4 Notes: 1. 2. 3. 4. These values are guaranteed by design and are tested on a sample basis only DQx and ODT are disabled, and 0 V ≤ VOUT ≤ VDD. VDD = 1.7 V, VOUT = 1420 mV. (VOUT - VDD)/IOH must be less than 21 Ohms for values of VOUT between VDD and (VDD - 280 mV). VDD = 1.7 V, VOUT = 280 mV. VOUT/IOL must be less than 21 Ohms for values of VOUT between 0 V and 280 mV. Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 5 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Symbol Operating One Bank ActivePrecharge Current IDD0 Operating One Bank Active-ReadPrecharge Current IDD1 Precharge PowerDown Current IDD2P Precharge Standby Current IDD2N Active Power-Down Current IDD3P Active Standby Current IDD3N Operating Burst Write Current IDD4W Operating Burst Read Current IDD4R Burst Refresh Current IDD5 Self Refresh Current IDD6 Operating Bank Interleave Read Current IDD7 Notes: 1. 2. Test Condition tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASMIN(IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching. IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASMIN(IDD), tRCD = tRCD(IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are switching. All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating. All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching. All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating; Fast Power-down exit (Mode Register bit 12 = 0). All banks open; tCK = tCK(IDD), tRAS = tRASMAX(IDD), tRP = tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching. All banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASMAX(IDD), tRP = tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching. All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASMAX(IDD), tRP = tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching. tCK = tCK(IDD); refresh command at every tRFC(IDD) interval; CKE is HIGH, /S is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating. All bank interleaving reads, IOUT= 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching. Max Value Unit 920 mA 1120 mA 110 mA 640 mA 480 mA 720 mA 1360 mA 1360 mA 2040 mA 110 mA 2520 mA All currents are based on DRAM absolute maximum values. Unless otherwise specified, for all IDDX measurements: CL(IDD) = 4 tCK tCK(IDD) = 3.75 ns tRASMAX(IDD) = 70,000 ns tRASMIN(IDD) = 45 ns tRC(IDD) = 60 ns tRCD(IDD) = 15 ns tRFC(IDD) = 127.5 ns tRP(IDD) = 15 ns tRRD(IDD) = 7.5 ns Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 6 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tAC -500 +500 ps CAS-to-CAS Command Delay tCCD 2 - tCK Clock High Level Width tCH 0.45 0.55 tCK Clock Cycle Time tCK 3750 8000 ps Clock Low Level Width tCL 0.45 0.55 tCK tDH 225 - ps tDIPW 0.35 - tCK DQS Output Access Time from Clock tDQSCK -450 +450 ps Write DQS High Level Width tDQSH 0.35 - tCK Write DQS Low Level Width tDQSL 0.35 - tCK DQS-Out Edge to Data-Out Edge Skew tDQSQ - 300 ps Data Input Setup Time Before DQS Strobe tDS 100 - ps DQS Falling Edge from Clock, Hold Time tDSH 0.2 - tCK DQS Falling Edge to Clock, Setup Time tDSS 0.2 - tCK Clock Half Period tHP minimum of tCH or tCL - ns Address and Command Hold Time after Clock tIH 375 - ps Data Input Hold Time after DQS Strobe DQ Input Pulse Width tIS 250 - ps Load Mode Command Cycle Time tMRD 2 - tCK DQ-to-DQS Hold tQH tHP - tQHS - - Data Hold Skew Factor tQHS - 400 ps Active-to-Precharge Time tRAS 45 70K ns Active-to-Active / Auto Refresh Time tRC 60 - ns RAS-to-CAS Delay tRCD 15 - ns Average Periodic Refresh Interval tREFI - 7.8 μs Auto Refresh Row Cycle Time tRFC 127.5 - ns Row Precharge Time tRP 15 - ns Read DQS Preamble Time tRPRE 0.9 1.1 tCK Read DQS Postamble Time tRPST 0.4 0.6 tCK Row Active to Row Active Delay tRRD 7.5 - ns Internal Read to Precharge Command Delay tRTP 7.5 - ns Write DQS Preamble Time tWPRE 0.35 - ps Write DQS Postamble Time tWPST 0.4 0.6 tCK tWR 15 - ns Address and Command Setup Time before Clock Write Recovery Time Internal Write to Read Command Delay tWTR 7.5 - ns Exit Self Refresh to Non-Read Command tXSNR tRFC(min) + 10 - ns Exit Self Refresh to Read Command tXSRD 200 - tCK Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 7 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM SERIAL PRESENCE DETECT MATRIX Byte# Function Value Hex 0 Number of Bytes Utilized by Module Manufacturer 128 bytes 80 1 Total number of Bytes in SPD device 256 bytes 08 2 Memory Type 3 Number of Row Addresses 14 0E 4 Number of Column Addresses 10 0A DDR2 SDRAM 08 Module Attributes - Number of Ranks, Package and Height 5 6 Module Data Width 7 Reserved 8 Voltage Interface Level of this assembly 9 10 61 Number of Ranks Card on Card DRAM Package - 2 No Planar Module Height - 30mm 64 40 UNUSED 00 SSTL/1.8V 05 SDRAM Cycle time. (Max. Supported CAS Latency). CL=X (ns) 3.75 3D SDRAM Access from Clock. (Highest CAS latency). (tAC) (ns) 0.5 50 DIMM configuration type (Non-parity, Parity or ECC) 00 Data Parity Data ECC Address/Command Parity TBD TBD TBD TBD TBD - 11 12 Refresh Rate/Type (μs) 7.8 (SR) 82 13 Primary SDRAM Width 8 08 14 Error Checking SDRAM Width None 00 15 Reserved UNUSED 00 SDRAM Device Attributes: Burst Lengths Supported TBD TBD Burst Length = 4 Burst Length = 8 TBD TBD TBD TBD - 16 17 0C SDRAM Device Attributes - Number of Banks on SDRAM Device Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 X X 8 08 Page 8 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM SDRAM Device Attributes: CAS Latency TBD TBD Latency = 2 Latency = 3 Latency = 4 Latency = 5 Latency = 6 TBD - 18 19 18 DIMM Mechanical Characteristics. Max. module thickness. (mm) X X x </= 3.80 DIMM type information 20 21 04 Regular RDIMM (133.35mm) Regular UDIMM (133.35mm) SODIMM (67.6mm) Micro-DIMM (45.5mm) Mini RDIMM (82.0mm) Mini UDIMM (82.0mm) TBD TBD SDRAM Module Attributes (Refer to Byte 20 for DIMM type information) Number of active registers on the DIMM (N/A for SODIMM) Number of PLL on the DIMM (N/A for UDIMM) FET Switch External Enable TBD Analysis probe installed TBD - X 00 1 0 No No SDRAM Device Attributes: General 22 01 Includes Weak Driver Supports 50 ohm ODT Supports PASR (Partial Array Self Refresh) TBD TBD TBD TBD TBD - 23 Minimum Clock Cycle Time at Reduced CAS Latency, CL = X-1 (ns) 24 Maximum Data Access Time (tAC) from Clock at CL = X-1 (ns) 25 02 X 5 50 0.5 50 Minimum Clock Cycle Time at CL = X-2 (ns) UNUSED 00 26 Maximum Data Access Time (tAC) from Clock at CL = X-2 (ns) UNUSED 00 27 Minimum Row Precharge Time (tRP) (ns) 15 3C 28 Minimum Row Active to Row Active Delay (tRRD) (ns) 7.5 1E 29 Minimum RAS to CAS Delay (tRCD) (ns) 15 3C 30 Minimum Active to Precharge Time (tRAS) (ns) 45 2D Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 9 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM 31 Module Rank Density 1GB 01 32 Address and Command Setup Time Before Clock (tIS) (ns) 0.25 25 33 Address and Command Hold Time After Clock (tIH) (ns) 0.37 37 34 Data Input Setup Time Before Strobe (tDS) (ns) 0.1 10 35 Data Input Hold Time After Strobe (tDH) (ns) 0.22 22 36 Write Recovery Time (tWR) (ns) 15 3C 37 Internal write to read command delay (tWTR) (ns) 7.5 1E 38 Internal read to precharge command delay (tRTP) (ns) 7.5 1E 39 Memory Analysis Probe Characteristics. UNUSED 00 Extension of Byte 41(tRC) and Byte 42 (tRFC) (ns) 40 06 Add this value to byte 41 - 0 Add this value to byte 42 - 0.5 41 SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) (ns) 42 SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC). (ns) 43 SDRAM Device Maximum Cycle Time (tCK max). (ns) 44 60 3C 127.5 7F 8 80 SDRAM Dev DQS-DQ Skew for DQS & DQ signals (tDQSQ) (ns) 0.3 1E 45 DDR SDRAM Device Read Data Hold Skew Factor (tQHS) (ns) 0.4 28 46 PLL Relock Time (μs) UNUSED 00 DRAM maximun Case Temperature Delta. (C) 47 48 00 DT4R4W Delta (Bits 0:3) - 0 Tcasemax delta (Bits 7:4) - 0 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM). (C/Watt) UNUSED DRAM Case Temperature Rise from Ambient due to Activate-Precharge/ Mode Bits (DT0/Mode Bits). (C) 49 4E 20 Bit 0: If "0" DRAM does not support high temperature self-refresh entry - 0 Bit 1: If "0" Do not need double refresh rate for the proper operation - 0 DT0: (Bits 2:7) - 0 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q). (C) UNUSED 1E 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P). (C) UNUSED 23 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N). (C) UNUSED 16 53 DRAM Case temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast). (C) UNUSED 2C Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 10 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM 54 DRAM Case temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow). (C) UNUSED 1E DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit). (C) 55 2E Bit 0: "0" if DT4W is greater than DT4R - 0 Bits 1:7 - DT4R - 0 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B). (C) UNUSED 1F 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7). (C) UNUSED 28 58 Thermal Resistance of PLL Package from Top to Ambient (Psi T-A PLL). (C/Watt). UNUSED 00 59 Thermal Resistance of Register Package from Top to Ambient ( Psi T-A Register). (C/Watt). UNUSED 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active). (C). UNUSED 00 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit). 61 Bit 0: If "0" Unit for Bits 2:7 is 0.75C - 00 0.75 Bit 1: RFU. Default: 0 - 0 Bits 2:7 - Register Active - 0 62 SPD Revision Revision 1.2 12 63 Checksum for Bytes 0-62 [Checksum] 1F 64 Module Manufacturer’s JEDEC ID Code Dataram ID 7F 65 Module Manufacturer’s JEDEC ID Code Dataram ID 91 UNUSED 00 UNUSED 00 [Space] 20 UNUSED 00 [Date Code] ## 66-71 Module Manufacturer’s JEDEC ID Code 72 Module Manufacturing Location 73-90 Module Part Number 91,92 Module Revision Code 93,94 Module Manufacturing Date 95-98 Module Serial Number 99-127 Manufacturer’s Specific Data Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 [Serial Number] ## UNUSED 00 Page 11 DTM67207B 2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Dataram. Dataram reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Dataram. Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 12