Download Transcend 256MB SDRAM PC133 ECC Unbuffer Memory
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168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D Description Placement The TS32MLS72V6D is a 32M x 72bits Synchronous Dynamic RAM high-density for PC-133. The TS32MLS72V6D consists of 18pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 168-pin printed circuit board. The TS32MLS72V6D is a Dual In-Line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operation frequencies, A programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. B Features D • Performance Range : PC-133 CL3 • Conformed to JEDEC Standard Spec. E • Burst Mode Operation. C • Auto and Self Refresh. • CKE Power Down Mode. E • DQM Byte Masking (Read/Write) H • Serial Presence Detect (SPD) with serial EEPROM G • LVTTL compatible inputs and outputs. F • Single 3.3V ± 0.3V power supply. • MRS cycle with address key programs. Latency (Access from column address) PCB :09-7149 Burst Length (1,2,4,8 & Full Page) Data Sequence (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. Transcend Information Inc. 1 I 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D Dimensions Pin Identification Side Millimeters Inches A 133.35±0.40 5.250±0.016 B 65.67000 2.585000 C 23.49000 0.925000 D 8.89000 0.350000 E 3.00000 0.118000 F 31.75±0.2000 1.250±0.0080 G 19.8000 0.780000 H 15.80 0.622 I 1.27±0.10 0.050±0.004 Symbol A0~A11, BA0, BA1 Address input DQ0~DQ63, C0~C7 Data Input / Output. (Refer Placement) Transcend Information Inc. Function 2 CLK0~CLK3 Clock Input. CKE0, CKE1 Clock Enable Input. /CS0~/CS3 Chip Select Input. /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQM0~DQM7 Data (DQ) Mask SA0~SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add/Data input/output Vcc +5.0 Voltage Power Supply Vss Ground NC No Connection 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D Pinouts: Pin Pin Pin Pin No Name No Name 01 Vss 43 Vss 02 DQ0 44 NC 03 DQ1 45 /CS2 04 DQ2 46 DQM2 05 DQ3 47 DQM3 06 Vcc 48 NC 07 DQ4 49 Vcc 08 DQ5 50 NC 09 DQ6 51 NC 10 DQ7 52 *C2 11 DQ8 53 *C3 12 Vss 54 Vss 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 Vcc 18 Vcc 60 DQ20 19 DQ14 61 NC 20 DQ15 62 *Vref 21 *C0 63 *CKE1 22 *C1 64 Vss 23 Vss 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 Vcc 68 Vss 27 /WE 69 DQ24 28 DQM0 70 DQ25 29 DQM1 71 DQ26 30 /CS0 72 DQ27 31 NC 73 Vcc 32 Vss 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 Vss 37 A8 79 *CLK2 38 A10/AP 80 NC 39 BA1 81 NC 40 Vcc 82 SDA 41 Vcc 83 SCL 42 CLK0 84 Vcc * Please refer Block Diagram Transcend Information Inc. Pin No 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 3 Pin Name Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 *C4 *C5 Vss NC NC Vcc /CAS DQM4 DQM5 */CS1 /RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vcc *CLK1 *A12 Pin No 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name Vss CKE0 */CS3 DQM6 DQM7 *A13 Vcc NC NC *C6 *C7 Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC *Vref *REGE Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss *CLK3 NC SA0 SA1 SA2 Vcc 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D Block Diagram A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 /RAS /RAS /RAS /RAS /RAS CKE /CS CKE /RAS /CAS /WE /WE /CS /CS CKE DQM0 DQM1 DQM2 DQM3 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 CLK /CS /CAS 16Mx8 SDRAM DQM CKE /WE /WE CLK /CS /CAS 16Mx8 SDRAM DQM CKE0 /CAS CLK /WE 16Mx8 SDRAM DQM /WE /CS0 CLK /CAS 16Mx8 SDRAM DQM /CAS A0~A11, BA0,BA1 CKE 16Mx8 SDRAM CLK A0~A11, BA0,BA1 DQ0~DQ7 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 DQM A0~A11, BA0,BA1 DQ0~DQ63 C0~C7 DQM1 CLK CLK DQM6 DQM7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 /RAS /RAS /RAS /RAS /RAS CKE CKE /WE /CS /CS CKE DQM0 DQM1 DQM2 DQM3 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 A0~A11, BA0,BA1 DQ0~DQ7 CKE 16Mx8 SDRAM DQ0~DQ7 /CS /CAS /WE CLK /WE /CS /CAS 16Mx8 SDRAM DQM /WE 16Mx8 SDRAM CLK /CAS DQM /CAS CLK CLK CKE DQM /CS 16Mx8 SDRAM DQM 16Mx8 SDRAM CLK CKE DQM /WE /CS 16Mx8 SDRAM DQM CKE /CAS DQM5 /WE CKE1 /WE /CS 16Mx8 SDRAM DQM CKE /CAS DQM4 /CAS /CS1 /WE DQM CKE 16Mx8 SDRAM /CAS /CS DQM /WE /CS 16Mx8 SDRAM /RAS /RAS /RAS /RAS /CAS CLK CLK /CS2 CLK0 CLK2 C0~C7 DQM5 16Mx8 SDRAM /CAS /CAS /CAS /WE /CS DQM4 CKE CKE DQM6 DQM5 DQM /WE /CS DQM /WE /CS DQM /WE /CS CKE CLK CLK 16Mx8 SDRAM CKE 16Mx8 SDRAM DQM 16Mx8 SDRAM /RAS /RAS /RAS /RAS /CAS CLK CLK /CS3 CLK1 CLK3 DQM7 Serial EEPROM SCL SCL A0 SDA A1 SDA A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 4 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply to Vss Storage temperature Power dissipation Short circuit current Mean time between failure Temperature Humidity Burning Temperature Cycling Test Note: Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS MTBF THB TC Value -1.0~4.6 -1.0~4.6 -55~+150 18 50 50 85°C/85%, Static Stress 0°C ~ 125°C Cycling Unit V V °C W mA year °C-% °C Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDD+0.3 V Input low voltage VIL -0.3 0 0.8 V Output high voltage VOH 2.4 V Output low voltage VOL 0.4 V Input leakage current ILI -10 10 uA Note 1 2 IOH=-2mA IOL=2mA 3 Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200mV) Parameter Symbol Min Max Unit CADD 50 95 pF CIN 50 95 pF CKE (CKE0 ~ CKE1) CCKE 28 50 pF Clock (CLK0 ~ CLK3) CCLK 18 25 pF /CS (/CS0 ~ /CS3) CCS 18 30 pF DQM (DQM0 ~ DQM7) CDQM 13 20 pF DQ (DQ0 ~ DQ63) COUT1 13 18 pF CB (CB0 ~ CB7) COUT2 13 18 pF Address (A0 ~A11, BA0 ~BA1) /RAS, /CAS, /WE DC CHARACTERISTICS Transcend Information Inc. 5 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating Current (One Bank Active) Symbol ICC1 Precharge Standby Current ICC2P in power-down mode ICC2PS ICC2N Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC2NS Test Condition Burst Length =1 tRC≥tRC(min) IO=0mA Unit Note 1,080 mA 1 CKE≤VIL(max), tCC=10ns 36 CKE & CLK≤VIL(max), tCC=∞ 36 CKE≥VIH(min), /CS≥VIH(min), tCC=10ns Input signals are changed one time during 20ns CKE≥VIH(min), CLK≤VIL(max), tCC=∞ Input signals are stable mA 180 CKE≤VIL(max), tCC=10ns 90 ICC3PS CKE & CLK≤VIL(max), tCC=∞ 90 ICC3N CKE≥VIH(min), /CS≥VIH(min), tCC=10s Input signals are changed one time during 30ns ICC3NS mA 540 mA CKE≥VIH(min), CLK≤VIL(max), tCC=∞ 450 IOL= 0 mA Page Burst 4 Banks activated tccD = 2CLKs 1,620 mA 1 2,070 mA 2 36 mA Operating Current (Bust Mode) ICC4 Refresh Current ICC5 tRC≥tRC(min) Self Refresh Current ICC6 CKE≤0.2V 1. Measured with outputs open. 2. Refresh period is 64ms 3. Unless otherwise noted, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ) AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C) Transcend Information Inc. mA 360 ICC3P Input signals are stable Note: Value 6 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D Parameter Value AC Input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Unit 2.4/0.4 V 1.4 V tr/tf=1/1 ns 1.4 V See Fig. 2 Vtt=1.4V 3.3V 50 Ohm 1200 Ohm Output Output VOH (DC)=2.4V, I OH=-2mA VOL (DC)=0.4V, I OL=2mA Z0=50 Ohm 50pF 50pF 870 Ohm (Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Value Unit Note Row active to row active delay tRRD(min) 15 ns 1 /RAS to /CAS delay tRCD(min) 20 ns 1 Row precharge time tRP(min) 20 ns 1 tRAS(min) 45 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 65 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to Active precharge tDAL(min) 2 CLK + 20ns - Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Row active time Number of valid output data Note: CAS latency=3 2 CAS latency=2 - 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time, and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Transcend Information Inc. 7 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Refer to the individual component, not the whole module. Parameter CLK cycle time CAS latency=3 CAS latency=2 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 Symbol Min 7.5 tCC Max Unit Note 1000 ns 1 ns 1, 2 ns 2 - tSAC CAS latency=2 tOH CAS latency=2 - 5.4 - - 3 - - - CLK high pulse width tCH 2.5 - ns 3 CLK low pulse width tCL 2.5 - ns 3 Input setup time tSS 1.5 - ns 3 Input hold time tSH 0.8 - ns 3 CLK to output in Low-Z tSLZ 1 - ns 2 - 5.4 - - CLK to output in Hi-Z Note: CAS latency=3 tSHZ CAS latency=2 ns 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)= 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Transcend Information Inc. 8 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D SIMPLIFIED TRUTH TABLE COMMAND Register CKEn-1 CKEn Mode Register Set Auto Refresh Refresh H Entry Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Burst Stop Auto Precharge Enable Precharge H Bank Selection X H /CS /RAS /CAS /WE DQM L L L L X OP CODE L L L H X X Active Power Down Precharge Power Entry Exit 1,2 3 3 L H L H H H X H X H L X L X H X H X V H X L H L H X V 3 H X L H L L X H X L H H L X H X L L H L X H H X X X L V V V L X L H X X X X H L H X X X L H H H H X X X L V V V L H Exit DQM H No Operation Command H X X H X X X L H H H 3 X Row Address L H Entry Down Mode A10/AP A11, A0~A9 Note L Both Banks Clock Suspend or BA0,1 V L H X V L X H Column Address (A0~A8) Column Address (A0~A8) 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) Note: 1. OP Code : Operand Code A0~A11, BA0~BA1 : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatically precharge without row precharge command is meant by “Auto”. Auto/self refresh can be issued only at both banks precharge state. 4. BA0~BA1: Bank select address. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected. If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Transcend Information Inc. 9 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D Serial Presence Detect Specification Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Number of Bytes Written into Serial Memory Total # of Bytes of S.P.D Memory Fundamental Memory Type Number of Row Addresses on this Assembly Number of Column Addresses on this Assembly Number of Module Rows on this Assembly Data Width of this Assembly Data Width of this Assembly Voltage Interface Standard of this Assembly SDRAM Cycle Time @CAS latency of 3 SDRAM Access Time from Clock @CAS latency of 3 DIMM configuration type Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width Min Clock Delay for Back to Back Random Address SDRAM Device Attributes: Burst Lengths Supported SDRAM Device Attributes: # of banks on SDRAM device SDRAM Device Attributes: CAS Latency SDRAM Device Attributes: CS Latency SDRAM Device Attributes: Write Latency 80 08 04 0C 0A 02 48 00 01 75 54 02 80 08 08 01 8F 04 06 01 01 21 SDRAM Module Attributes 22 SDRAM Device Attributes: General 128bytes 256bytes SDRAM 12 10 2 rows 72bits LVTTL 7.5ns 5.4ns ECC 15.625us/Self Refresh X8 X8 tCCD=1CLK 1,2,4,8 & Full page 4 bank 2,3 0 clock 0 clock Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 15ns 20ns 45ns 2 rows of 128MB 1.5ns 0.8ns 1.5ns 0.8ns - 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 SDRAM Cycle Time @CAS Latency of 2 SDRAM Access Time from Clock @CAS Latency of 2 SDRAM Cycle Time @CAS Latency of 1 SDRAM Access Time from Clock @CAS Latency of 1 Minimum Row Precharge Time (=t RP) Minimum Row Active to Row Activate (=t RRD) Minimum RAS to CAS Delay (=t RCD) Minimum Activate Precharge Time (=t RAS) Module Row Density Command and Address Signal input Setup Time Command and Address Signal input Hold Time Data Signal Setup Time Data Signal Hold Time Superset Information Transcend Information Inc. 10 00 0E A0 60 00 00 14 0F 14 2D 20 15 08 15 08 00 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS72V6D 62 63 64-71 72 SPD Data Revision Code Checksum for Bytes 0-62 Manufacturers JEDEC ID Code per JEP-108E Manufacturing Location JEDEC2 Transcend T 73-90 Manufacturers Part Number TS32MLS72V6D 91-92 93-94 95-98 99-125 126 127 128~ By Manufacturer By Manufacturer CL=2, 3 Clock 0 Open Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Intel Specification Frequency Intel Specification CAS# Latency/Clock Signal Support Unused Storage Locations Transcend Information Inc. 11 02 B2 7F, 4F 54 54 53 33 32 4D 4C 53 37 32 56 36 44 20 20 20 20 20 20 0 Variable Variable 0 64 F6 FF