Download Transcend 128MB SDRAM PC133 Unbuffer Non-ECC Memory

168PIN PC133 Unbuffered DIMM
128MB with 16Mx16 CL3
TS16MLS64V6G
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf=1/1
1.4
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
Unit
V
V
ns
V
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
@Operation
Row cycle time
Last data in to new col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Value
Unit
Note
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
15
20
20
45
100
ns
ns
ns
ns
us
1
1
1
1
tRC(min)
65
ns
1
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
1
2
1
1
CLK
CLK
CLK
CLK
2
2
2
3
2
ea
4
CAS latency=2
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
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