Download clevo d900f

Schematic Diagrams
Power Sequence Diagram
11
D900F V0.0 BOOT BLOCK DIAGRAM
IOH_CLPWROK
13-1
7a
PLLDET_3V(COREPLLPWRDET)
1
PWR_SW#
Power Bottom
13-3 H_PWRGD_IOH(COREPWRGOOD)
B.Schematic Diagrams
VDD3/VDD5
VR
LTC3850
3V
3
5V
3
12V
3
LP2951CDR2G
EC
Sheet 47 of 47
Power Sequence
Diagram
DRAM VR
ITE8512E
SC486
DELAY
DD_ON
75 ms
PWR_BTN#
4a
RSMRST#
4b
SUSC#
5a
SUSB#
5b
MXM_PWR_EN
M XM3. 0
MXM_PRESNT#
Tylersberg
16
17
H_CPURST#
15
PLTRST_DLY#(CORERST#)
14 PLTRST#(VCCPWRGD)
IOH_CSI_RST
2
DD_ON
MXM_PWR_EN
7b
NORTH BRIDGE
1.5V
3
0.75VS
6
Other
P latf orm
Devices
SOUTH BRIDGE
MXM_PRESNT# 7b
13-2
H_PWRGD
Processor
Bloomfield
7a
11
ICH10R
IOH_CLPWROK
MXM_PRESNT# 7b
14
PCIRST#
Oth er P CI
Devi ces
(NEW Car d)
VCORE_ON
9
VTT_PWRGD
9
NCP5392MNR2G
VCORE
11
VRM_PWRGD
12
PWROKICH
VCORE VR
12-1 CK_PWRGD
10
CV193
11
6
VRM_PWRGD->ICH_VRM_PWRGD
PM_PWROK
3VS
14
G690L293T73
5b
1.1VS
ISL6314CR
8
VTT_PWRGD
B - 48 Power Sequence Diagram
PLTRST#
6
1.1V EN
1.5VS
6
1.8VS
6
3.3VS
6
5VS
15
Delay 2ms
11
SUSB#
ICH_VRM_PWRGD
6
SC412A
8
CPU_VTT
Clock Generator
13-1
2N3904
Delay
MOSFET
PLTRST_DLY#(CORERST#)
PLLDET_3V(COREPLLPWRDET)
H_PWRGD_IOH(COREPWRGOOD)
13-3
Follow Design Guide