Download Intel SE7500CW2 Motherboard

Intel® Server Board SE7500CW2 TPS
Functional Architecture
In addition to the circuitry described above, the processor subsystem contains the following:
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Reset configuration logic.
Processor module presence detection logic.
APIC bus.
Server monitoring registers and sensors.
3.1.1.1
Processor VRD
The Server Board SE7500CW2 has a single VRD (Voltage Regulator Down) to support two
processors. It is compliant with the VRM 9.1 specification and provides a maximum of 130
AMPs, which is capable of supporting current supported processors as well as those supported
in the future.
The board hardware and PMC must read the processor VID (voltage identification) bits for each
processor before turning on the VRD. If the VIDs of the two processors are not identical, then
the PMC will not turn on the VRD and a beep code is generated.
3.1.1.2
Reset Configuration Logic
The BIOS determines the processor stepping, cache size, etc through the CPUID instruction.
The requirements are as follows:
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All processors in the system must operate at the same frequency, have the same cache
sizes, and same VID. No mixing of product families is supported.
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Processors run at a fixed speed and cannot be programmed to operate at a lower or
higher speed.
Note: The processor speed is the processor power on reset default value.
The processor information is read at every system power-on.
Note: No manual processor speed setting options exist either in the form of a BIOS setup option
or jumpers.
3.1.1.3
Processor Module Presence Detection
Logic is provided on the baseboard to detect the presence and identity of installed processors.
The PMC checks the logic and will not turn on the system DC power unless the VIDs of both the
processors mach in a DP configuration.
3.1.1.4
Interrupts and APIC
Interrupt generation and notification to the processors is done by the APICs in the ICH3 and the
P64H2 using messages on the front side bus.
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Revision 1.50