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10-BIT A/D CONVERTER
S3F84A5_UM_REV1.10
A/D Converter High-byte Control Register (ADCONH)
FBH, Set1, Bank0, Reset=00H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
A/D input pin selection bits:
A/D conversion Start bit:
000 = ADC0
0 = Disable operation
End-of-conversion (EOC)
001 = ADC1
1 = Start operation (Auto-clear)
status bit:
010 = ADC2
0 = A/D conversion is in progress
011 = ADC3
1
= A/D conversion complete
100 = ADC4
101 = ADC5
Clock source selection bits:
110 = ADC6
00 = fxx/16 (fosc = 8MHz)
111 = ADC7
01 = fxx/8 (fosc = 8MHz)
10 = fxx/4 (fosc = 8MHz)
11 = fxx (fosc = 2.5MHz)
NOTE:
Maximum ADC clock input = 2.5MHz
Figure 15-2. A/D Converter High-byte Control Register (ADCONH)
A/D Converter Low-byte Control Register (ADCONL)
F3H, Set1, Bank0, Reset=00H, R/W
MSB
.7
Reserved
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
A/D conversion complete
A/D converter event trigger source selection bit:
interrupt pending bit:
000 = Disable A/D converter event trigger function
0 = No interrupt pending
001 = A/D conversion complete int
0 = Clear pending bit (when write)
010 = PWM 8-bit counter overflow int
1 = Interrupt is pending (when read)
011 = PWMA group match int
1 = No effect (when write)
100 = PWMB group match int
A/D conversion complete interrupt enable bit:
101 = Timer 0 overflow int
0 = Disable interrupt
110 = Timer 0 match/capture int
1 = Enable interrupt
111 = P3.0 external int (INT2)
NOTE:
1. The reserved bit must be logic “0”.
2. If you are using the event trigger, whenever the current conversion is not finished, any
event trigger source is masked, thus it can not start any new A/D conversion.
Figure 15-3. A/D Converter Low-byte Control Register (ADCONL)
15-4