Download RF Technology R50 Eclipse Series Operating instructions

Eclipse Ser ies
RF Technology
[email protected]
August, 2003
Revision 2
T50 Tr ansmitter
Operation and Maintenance Manual
This manual is produced by RF Technology Pty Ltd
10/8 Leighton Place, Hornsby NSW 2077 Australia
Copyright © 2001 RF Technology
1
Contents
1
2
3
Operating Instructions
5
1.1
Front Panel Controls and Indicators
5
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
5
5
6
6
6
PTT
Line
POWER LED
TX LED
ALARM LED
Transmitter Internal J umper Options
6
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.11
2.9
6
7
7
7
7
7
7
7
7
7
8
8
8
Serial I/O Parameters
Line Terminations
Exciter Low Battery Level
External PA Parameters
Generate Loop
External Tone Input
External Tone, High Pass Filter Bypass
Transmit Time
Channel Select Override
CWID Start Delay
CWID Period
CWID Message
Channel Selectable Parameters
Transmitter I/O Connections
8
3.1
3.2
8
9
25 Pin Connector
9 Pin Front Panel Connector
4
Channel and Tone Frequency Programming
9
5
Circuit Description
10
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
10
10
13
14
15
16
18
20
20
6
7
T50 Master Schematic (Sheet 1)
Microprocessor (Sheet 2)
Audio Processing Section (Sheet 3)
Line Input Processing Section (Sheet 4)
Tone Generation Section (Sheet 5)
Frequency Synthesiser (Sheet 6)
Voltage Controlled Oscillators (Sheet 7)
1W Broadband HF Power Amplifier (Sheet 8)
Power Generation Section (Sheet 9)
Field Alignment Procedure
21
6.1
6.2
21
21
22
22
24
25
25
26
Standard Test Equipment
Invoking the Calibration Procedure Manually
6.2.1
The “Miscellaneous” Calibration Procedure
6.2.2
The “Reference” Calibration Procedure
6.2.3
The “Deviation” Calibration Procedure
6.2.4
The “Tone Deviation” Calibration Procedure
6.2.5
The “Line” Calibration Procedure
6.2.6
The “Power” Calibration Procedure
Specifications
28
2
7.1
Overall Descr iption
28
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
28
28
28
29
29
Channel Capacity
CTCSS
Channel Programming
Channel Selection
Microprocessor
7.2
Physical Configuration
29
7.3
Front Panel Controls, Indicators and Test Points
29
7.3.1
7.3.2
7.3.3
29
29
29
7.4
7.5
A
A.1
A.2
A.3
Controls
Indicators
Test Points
Electrical Specifications
29
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
7.4.15
7.4.16
7.4.17
7.4.18
7.4.19
7.4.20
7.4.21
7.4.22
7.4.23
7.4.24
29
29
30
30
30
30
30
30
30
30
30
30
30
30
30
31
31
31
31
31
31
32
32
32
Power Requirements
Frequency Range and Channel Spacing
Frequency Synthesizer Step Size
Frequency Stability
Number of Channels
Output Power
Transmit Duty Cycle
Spurious and Harmonics
Carrier and Modulation Attack Time
Modulation
Distortion
Residual Modulation and Noise
600Ω Line Input Sensitivity
Test Microphone Input
External Tone Input
T/R Relay Driver
Channel Select Input / Output
DC Remote Keying
PTT in
Programmable No-Tone Period
Firmware Timers
CTCSS
DCS Codes
CWID
Connectors
32
7.5.1
7.5.2
7.5.3
32
32
32
RF Output Connector
Power and I/O Connector
External Reference Connector (optional)
Engineering Diagrams
33
Block Diagram
Circuit Diagrams
Component Overlay Diagrams
33
33
33
B
T50 Parts List (Rev. 4)
34
C
T50 Parts List (Rev. 3)
46
D
EIA CTCSS Tones
48
3
WARNING
Changes or modifications not expressly approved by RF
Technology could void your authority to operate this
equipment. Specifications may vary from those given in this
document in accordance with requirements of local authorities.
RF Technology equipment is subject to continual improvement
and RF Technology reserves the right to change performance
and specification without further notice.
1 Oper ating Instr uctions
1.1 Fr ont Panel Contr ols and Indicator s
1.1.1
PTT
A front-panel push-to-talk (PTT) button is provided to facilitate bench and field tests
and adjustments. The button is a momentary action type. When keyed, audio from the
line input is disabled so that a carrier with subtone is transmitted. The front-panel
microphone input is not enabled in this mode, but it is enabled when the PTT line on
that socket is pulled to ground.
The PTT button has another function when transmission is keyed up, and the TX LED
light is showing. If there is a “forward power low” alarm (the ALARM LED flashes
three times, then pauses), pressing this will cause the ALARM LED to flash 6, 7, 8, or 9
times before the pause (see Table 2). This will indicate what has caused the low power
alarm.
1.1.2
Line
The LINE trimpot is accessible by means of a small screwdriver from the front panel of
the module. It is used to set the correct sensitivity of either line input or the direct
audio input. It is factory preset to give 60% of rated deviation with an input of 0dBm
(1mW on 600Ω, equivalent to 775mV RMS or about 2.2V peak-to-peak) at 1kHz. By
this means an input sensitivity from approximately -12dBm to +12dBm may be
established.
An internal, software selectable, option, provides an extra gain step of 20dB. This,
effectively changes the input sensitivity to –32 to –8dBm.
LED Flash Cadence
Fault Condition
9 flashes, pause
External PA failure – reason unknown
8 flashes, pause
Low dc supply on External PA
7 flashes, pause
External PA Over Current Condition
6 flashes, pause
External PA Over Temperature
5 flashes, pause
One or both synthesizers could not lock.
4
4 flashes, pause
Either PLL is near its operational limit
3 flashes, pause
Unable to communicate with the External PA.
2 flashes, pause
The current channel is not programmed or the channel
frequency is out of range.
1 flash, pause
Low dc supply voltage
LED ON continuously
Transmitter timed out
Table 1: Interpretations of LED flash cadence (TX LED Off)
LED Flash Cadence
Fault Condition
9 flashes, pause
External PA failure (if PTT is pressed)
8 flashes, pause
Low dc supply on External PA (if PTT is pressed)
7 flashes, pause
External PA Over Current Condition(if PTT is pressed)
6 flashes, pause
External PA Over Temperature(if PTT is pressed)
3 flashes, pause
Forward Power Out of Range(if PTT is not pressed)
2 flashes, pause
Reverse Power ratio exceeded.
1 flash, pause
Low dc supply voltage
LED ON continuously
Transmitter timed out
Table 2: Interpretations of LED flash cadence (TX LED On)
1.1.3
POWER LED
The PWR LED shows that the dc supply is connected to the receiver and that the
microprocessor is not being held in a RESET state.
1.1.4
TX LED
The TX LED illuminates when the transmitter is keyed. It will not illuminate (and an
ALARM cadence will be shown) if the synthesizer becomes unlocked, or the output
amplifier supply is interrupted by the microprocessor.
1.1.5
ALARM LED
The Alarm LED can indicate several fault conditions if they are detected by the self test
program. The alarm indicator shows the highest priority fault present. See Tables 1
and 2.
2 Tr ansmitter Options
There are NO internal jumpers in the T50.
There are many software selectable options. Some options are selected on a per channel
basis, and some are defined globally (i.e. the parameter is fixed irrespective of which
channel is selected). Below is a description of these global parameters
2.1 Ser ial I/O Par ameter s
There are two serial ports. There is the main serial port which is brought out to the front
panel connector. This is referred to as PORT0. There is another serial port which is for
factory use only. It is referred to as PORT1.
The baud rate, can be defined for PORT0. PORT0 is set by default to 57.6Kbps, with
No parity.
5
2.2 LINE Ter minations
There are two main audio inputs, plus a direct audio (TONE) input. The direct audio
input is a High Impedance Balanced DC input, but the two audio inputs are AC coupled
(> 10Hz) inputs which can be High Impedance(HiZ), or 600 ohm inputs. Each input
can be software selected to be HiZ, or 600 ohms.
2.3 Exciter Low Batter y Level
This is factory set to 24.0V, and defines the level of the DC supply that will cause an
Exciter dc supply low alarm.
2.4 Exter nal PA Par ameter s
There are several user definable parameters associated with the external PA provided
with each exciter.
These are the PA low battery alarm level (default is 26V), the PA Set Forward Power
Level (defaults to 100W), the Forward Power Low Alarm Level (defaults to 90%), and
the Reverse Power Alarm Level (defaults to 25% - corresponding to a VSWR of 3:1).
2.5 Gener ate LOOP
Normally the transmitter will key up if dc current is sensed flowing in either direction
between Line1+ and Line1- (>=1mA). If the LOOP_VOLTS option is set to its nondefault setting, then a 12Vdc supply is applied to the pair through 660 ohms of source
impedance. (It would be expected, normally, that if this option is selected, then the
option to remove the 600 terminator from Line1, would also be selected). If dc current
flows from having applied this potential, then the transmitter will key up.
2.6 Exter nal TONE Input
Normally any signal applied to the TONE+/TONE- pair is ignored. If this option is
selected, then a Direct Audio input will be mixed with any audio received on either of
the other two lines, and with any CTCSS tones, or DCS codes being generated.
2.7 Exter nal Tone High Pass Filter Bypass
Normally the Direct Audio, and the CTCSS/DCS outputs are passed through a 250Hz,
low pass filter. This filter can be bypassed by selecting this option.
2.8 Tr ansmit Time
This parameter defines a maximum time limit for continuous transmission. It is
expressed in seconds and can be arbitrarily large (months in fact). If it is set to zero
seconds, then the transmitter can stay keyed up permanently.
2.9 Channel Select Over r ide
This parameter allows the user to override the channel number that is read in via
connector P3. Normally it is InActive, but if it is set to a value from 0 to 255, then the
exciter will behave as though that channel was hard-wired at the rear.
2.10 CWID Star t Delay
If CWID (Continuous Wave Identification) is enabled, then this value indicates the time
in tenths of a second, from keying up an exciter to when the first station identication
6
message is sent. If this timer value is negative, then CWID transmission is disabled.
This feature is only available on models from Rev. 4.
2.11 CWID Per iod
If CWID (Continuous Wave Identification) is enabled, then this value indicates the time
in tenths of a second from one transmission to the next. If the value is zero, then the
CWID message is transmitted only once. This feature is only available on models from
Rev. 4.
2.12 CWID Message
This parameter allows the user to specify the message string to be transmitted as the
station ID. This feature is only available on models from Rev. 4.
2.13 Channel Selectable Par ameter s
Each channel defines two complete set of parameters. One set of parameters is used
when a transmitter keys up from the PTT-in input, and the other set is used when the
transmitter keys up from the LOOP-in, the PTT switch, or the microphone PTT input.
Each set defines what frequency to use, what CTCSS sub-tone (if any) to use, what
maximum line deviation to use, what tone deviation to use, what transmit delay (a delay
applied from PTT-in or LOOP-in to transmission), what transmit tail (delay from PTTin, or LOOP-in, to transmission being stopped, and No-TONE period (a period of extra
transmission in which No Tone is applied after PTT-in or LOOP-in has been released.
As well as these parameters, which Line (or Lines) can be selected, and whether the
lines should have flat frequency response or have pre-emphasis applied. Also, it can
enable or disable, the extra 20dB gain pad.
Note that both Line1 and Line 2 can be selected (each with or without pre-emphasis),
and if so, then the two signals will be mixed, and the Line potentiometer will adjust the
level of them both.
3 Tr ansmitter I/O Connections
3.1 25 Pin Connector
The female D-shell, 25 pin, connector is the main interface to the transmitter. The pin
connections are described in table 3.
Function
dc power
Serial
Communications
Signal
Pins
Specification
+28Vdc(in)
13, 25
+24 to 32 Vdc
0 Vdc
1, 14
Common Voltage
+5Vdc(out)
17
Output for external Logic(100mA)
+12Vdc(out)
15
Output for an external relay(120mA)
Vref
4
Reference voltage for Tests
SCLK
12
Serial Clock
MOSI
6
Bi-directional Data Pin
CH_EN
18
Enables Channel Select Shift Register
PA_CS
24
Enables PA A/D chip
7
SPARE_SEL 5
Spare Select (for future use)
Line1+
8
Line1-
19
Transformer Isolated Balanced 0dBm
Input
Line2+
10
Line2-
22
Transformer Isolated Balanced 0dBm
Input
Direct PTT input
11
Ground to key PTT
T/R Relay
output
23
Open collector, 250mA /12V
Tone+
9
>10kΩ, dc coupled
Tone-
21
600Ω/HiZ Line
600Ω/HiZ Line
driver
Sub-Audible Tone
Input
Table 3: Pin connections and explanations for the main 25-pin, D connector.
3.2 9 Pin Fr ont Panel Connector
The female D-shell, 9 pin, front panel connector is an RS232 interface for serial
communications to a terminal, a terminal emulator, or to a computer. The pin
connections are described in table 4.
Function
Pins
Specification
Pin name on IBM PC
TXD
2
Transmit Data (Output)
RxD
RXD
3
Receive Data (Input)
TxD
RTS
8
Request To Send (Output)
CTS
CTS
7
Clear To Send (Input)
RTS
DTR
6
Data Terminal Ready(Output)
DSR
DSR
1
Data Set Ready (Input)
DCD
GND
5
GND
GND
Table 4: Pin connections for the front panel 9 pin D connector.
The pinout for the connector has been chosen so that a straight-through BD9 male to
DB9 female cable can connect the transmitter to any male DB9 serial port on an IBM
PC compatible computer.
Note that for connection to a modem, a cross-over cable will be required.
4 Channel Pr ogr amming and Option Selection
Channel and tone frequency programming is most easily accomplished with RF
Technology WinTekHelp software. This software can be run on an IBM compatible PC
and can be used to calibrate a T50, R50, and PA50 as well as program channel
information. See the WinTekHelp manual for further information.
8
5 Cir cuit Descr iption
The following descriptions should be read as an aid to understanding the block and
schematic diagrams given in the appendix of this manual.
There are 9 sheets in the schematic in all.
5.1 T50 Master Schematic (Sheet 1)
Sheet 1, referred to as the “T50 Master Schematic”, is a top level sheet, showing five
circuit blocks, and their interconnection with each other, as well as the interconnection
with all connectors and external switches.
JP12 is the connector, on the printed circuit board, for the microphone input.
P3 represents the rear female DB25 connector.
J1 is the nominal 1W RF output (BNC) connector, which is used to connect to the
External Power Amplifier.
J4 is an optional BNC connector for an external reference clock. If an external
reference clock, with power level from +5 to +26dBm is attached here, the firmware
will automatically track the channel VCO to the reference.
Note that the external reference frequency is limited to:
500kHz, or any multiple
any multiple of 128KHz greater than or equal to 512kHz
any multiple of 160KHz greater than or equal to 480kHz
and cannot be greater than 10MHz in Rev 4 or older versions. In Rev 5, the external
frequency can be as high as 20MHz.
P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal
emulator, or to an IBM PC running the WinTekHelp software.
JP2 is for the attachment of an LCD display module. This has been included for later
development. This connector, is not normally fitted
JP3, and JP4 are specialised connectors for test and factory configuration use only.
RV100 represents the front panel LINE potentiometer.
SW1 represents the PTT test pin.
D102, D103, and D104 represent the three front panel LEDs.
5.2 Micr opr ocessor (Sheet 2)
Sheet 2 describes the basic microprocessor circuitry.
The core CPU is the Motorola XC68HC12A0. It is configured in 8 bit data width
mode.
The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising the
JFET Q202, and two switching transistors Q203 and Q204.
The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,
AN1, …, AN7.
AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL)
circuits (see 5.6)
AN5 is used to sense whether or not the dc supply is within spec or not.
9
AN4 is multiplexed between the LINE control potentiometer and the Channel reference
crystal’s temperature sense. Which analogue input drives this analogue input, is defined
by the state of TEMP_LEVEL_IN which is a CPU output signal.
AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO
control varactor for each VCO.
AN2 is used to sense the average peak voltage of the audio input.
AN0 is used to sense the average peak voltage of the RF output.
FRDY is an output from the flash. It goes low when the Flash starts to write a byte of
data, or erase a block, or erase the whole chip, and it returns to its default high state
when the action requested has completed.
FPSW1 is the switch input from the PTT Test pin.
FPSW2, and FPSW3 are two pins that have been reserved for future use as switch
inputs.
LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the
audio output.
TONE_DEV_U/D and TONE_DEV_INC are CPU outputs that are used to control the
digital potentiometer that sets the TONE deviation level. (see 5.5)
EXT_TONE_SEL is a CPU output that when low enables differential analogue input
from the TONE+/TONE- pair. (see 5.5)
LINEINP_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue
converter (DAC) that sets the levels for the two Line input Voltage Controlled
Amplifiers, the output RF power amplifier bias voltage, and the LCD bias circuit. (see
5.4)
LINEINP_DSEL is also a serial bus select pin. It is used to select the shift register that
is used to control most of the analogue switches in the audio Line input circuitry, as
well as the digital POT used to set the maximum deviation level. (See 5.4)
PWR_CNTRL_HIGH is a CPU output that can be low, tri-state, or high. This adjusts,
slightly, the range of the power amplifier bias circuitry allowing finer control of the
output power level. (see 5.4 and 5.8)
CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500), which
is used to generate CTCSS tones. (see 5.5)
CHAN_PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the
Channel PLL circuit (U604). (See 5.6)
SIGGEN_ADSEL is a serial bus select pin. It is used to select the quad DAC in the RF
area. This DAC controls the reference oscillator bias voltages, and the BALANCE
voltage controlled amplifier. (See 5.6)
CHAN_VCO_EN is a CPU output that enables (when high) the Channel VCO. (See 5.6
and 5.7)
EXT_REF_DIV is a CPU timer input. It is the output of the external reference clock
divided by 3200. The software can measure what the reference frequency is, and then
use this input to calculate the frequency error of the channel PLL reference oscillator. It
can then adjust the channel reference oscillator to reduce this error to less than 0.3ppm.
(See 5.6)
SPARE_SEL is a serial bus select. It has been reserved for future use, and has been
brought out to the rear DB25 connector. (see 5.1)
10
CH_EN is a serial bus select. It is brought out to the rear panel and is used to interface
to the channel encoder on the rear daughter-board. (See 5.1)
Any GPS pulses are isolated from the on-board electronics by the opto-isolator U212.
The output of that opto-isolator is then connected to the GPS timer input of the CPU.
This has been included for future use to be able to auto-adjust the reference oscillator
frequencies to low, or high frequency clock pulses from an external clock reference of a
GPS receiver.
TERM_EN2 and TERM_EN1 are used to enable (when low) 600 ohm termination of
Line2, and Line1 respectively. (See 5.3)
The Fo outputs from the Modulation PLL and the Channel PLL are divided by two, and
these are called FO_MOD_2 and FO_CHAN_2 respectively. They should be 200Hz
square waves, except for brief periods when frequencies are being changed. (See 5.6)
ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz
on it.
TX_LED, ALARM_LED, are CPU outputs that drive (when low) the TX LED, and the
ALARM LED on.
T/R_RELAY_H, when high, drives the T/R RELAY output low, and also enables the
RF power amplifier. The T/R RELAY output can activate at least one conventional
12V relay. (See 5.1)
SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and MOSI
is a bi-directional data pin.
PA_CS is a serial select pin. It is passed, via the rear DB25 connector to the External
Power Amplifier (PA). (See 5.1)
DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which
are connected to the debug port after conversion to/from RS232 compatible voltage
levels by U202 and U201.
TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232 data
pins which are connected to the main front panel serial port after conversion to/from
RS232 compatible voltage levels by U202 and U201.
PTT_uPHONE is a CPU input and it reflects the state of the PTT pin on the microphone
handset.
TONE_INT is a CPU input that comes from the FX805 (U500). This pin is used to
indicate when a Tone has been decoded, or there is some other need to service the
FX805. As yet, this pin is not used in the T50. (See 5.5)
LOOP_DET is a CPU pin that is asserted low if there is dc loop current detected
through the centre tap input of Line2. (See 5.3)
FILTER_OFF is a CPU output that is used to by-pass, when low, the low pass filter in
the Tone Input Circuitry. (See 5.5)
PTT-in is an input from the rear DB25 connector that causes the INT pin of the CPU to
be asserted (low) when 1mA of current is drawn via that pin. If PTT-in is pulled to
ground, through a resistance of at most 3.9kohms, it will cause INT to be asserted. If it
is pulled low via a 2K2 resistor, and as many as three diodes in series, it will still cause
the INT pin to be asserted. This latter example shows that quite complex diode logic
can be used on this pin.
BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is
connected to the debug port and is utilised by specialised hardware to control the CPU
externally, even without any firmware being present in the Flash.
11
MORSE is a CPU output that can be used to generate a CWID (Continuous Wave
Identification) code. This is a 1028Hz tone which is keyed on and off in a Morse code
as a staion identifier. (See 5.4)
The RESET pin is both a low active input and a low active output to the CPU. If
generated externally to the CPU, it forces the CPU into reset, and if the CPU executes a
RESET instruction, this pin will be driven low by the CPU.
Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it
will keep its RES output low. After the voltage has met the right level it will assert its
output low for another 200 milliseconds. Thus the CPU will be held in reset until VCC
is at the correct level. Thus the PWR_OK LED will only light when VCC is within
specification, and RESET has been released.
S200 is a momentary push-button switch that, when pressed, will cause the CPU to be
reset.
MOD_PLL_SEL is a serial bus select pin. It is used to select the Modulation PLL chip
(U602). (See 5.6)
LCD_DB7, LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to an LCD
display module. Note that this feature has not been implemented.
U205 is used to select whether the Flash or RAM is to be read or written.
U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is
used to store the firmware.
U208 is a 1, or 4, Megabit Static RAM in an SOP-32 package, and is used for both code
and data. The code in the RAM is copied from the Flash, at start-up.
5.3 Audio Pr ocessing Section (Sheet 3)
Sheet 3 is a schematic, which itself refers to two other sheets.
Sheet 3 shows how the two Line inputs go to audio transformers T300 and T301, are
then optionally terminated by analogue switches U301B, and U301C, before being
passed to the audio input stages described by Sheet 4.
It also shows how the Direct Audio (TONE) signal is passed to the Tone circuitry (sheet
5).
It also shows how dc current in Line1 will cause the opto-isolator (U300) to generate
the CPU input LOOP_DET.
Relay RL300 is used to drive current back through an externally generated dc loop,
when the CPU output LOOP/VOLTS_SEL is high.
The output of the Tone circuitry and the Audio circuitry are mixed (summed) and
amplified by U302. It is then passed through a high order low pass filter (3.1kHz),
before being attenuated by digital POT U303.
U403D adds an extra 1.8% gain of the summed modulation signal. It effectively adds
another bit of control to the maximum deviation level.
The Digital POT (U303), in conjunction with U403D, set the Maximum deviation.
U302C then adds 6dB of gain before sending the audio to the modulator.
R317, D307, and C304, act as an average peak detector. This enables the CPU to
determine the size of signals being handled by the audio section.
12
Note that the Line inputs, and the TONE input, are protected by transils and fuses
against accidental connection to damaging voltages. The fuses (F300, F301, and F302)
are not user replaceable. They are surface mount devices and must be replaced by
authorised service personnel.
5.4 Line Input Pr ocessing Section (Sheet 4)
The two audio inputs are passed, after transformer coupling, to sheet 4.
In Sheet 4, the two Line Inputs are input to a transconductance amplifier (U402A, and
U402B). A transconductance amplifier is a current controlled, current amplifier, i.e. it
amplifies input current, but its level of amplification is controlled by the level of current
that is injected into pin1 (or pin16). By converting a DAC output into a current, and
converting the input voltage into an input current, U402A and U402B are converted into
Voltage Controlled, Amplifiers(VCAs).
Two of the DAC outputs are converted to currents by U400B, U400C, Q401, and Q400,
and these currents are used to control the gain of the transconductance amplifiers.
The input voltages are converted to current by the input load resistors R402, and R403.
The output currents are converted to voltages by resistors R420 and R424.
The outputs of the transconductance amplifiers are buffered by the darlington buffers
provided with the amplifiers (U402C, and U402D).
The output of each VCA is then amplified by U405B and U405C respectively.
The level of amplification of each VCA is adjusted in software in accordance with any
adjustments made to the LINE POT. The software converts the linear range of the
LINE POT into a logarithmic scale, such that if the LINE POT is wound down to zero,
the amplification of each VCA is reduced by 12db relative to its centre position.
Similarly if the POT is wound to its maximum position, both amplifiers increase their
gain by 12dB.
The outputs of these amplification stages are then attenuated. Analogue switches
U404A and U404Bare used to select which attenuation circuit is used for Line 2, and
U404D and U404C are used to select which attenuation circuit is used for Line 1.
If the resistive divider formed by R425, R426, and R439 is selected then the Line 2
audio signal frequency response is unaffected (it is Flat). If the reactive divider defined
by C402, R431, and R439 is selected, then higher frequencies of the Line 2 audio signal
are attenuated less than lower frequencies, i.e. Pre-emphasis is applied to the audio
signal.
Line 1 has an identical circuit.
The outputs of these pre-emphasis/flat frequency response attenuators are then buffered
by U405A, and U405D respectively.
The microphone input is amplified by U400D, after being limited by D400. It is passed
through a pre-emphasis network (defined by C404, R433, and R436), and is enabled, or
disabled by switch U403A.
The outputs of the Line 1 conditioning circuit, the Line 2 conditioning circuit, and the
microphone input amplifier, are then mixed (summed) and amplified by U407A. Its
output is, in turn, amplified by U407B, but the gain of U407B is either 2.7 or 27
depending on the state of analogue switch U403B.
The CPU is capable of injecting a signal into the audio path. This can be achieved via
the MORSE output. This is partially filtered by R446 and C421. C420 provides DC
13
isolation, and R446, and R448 set the level to be approximately 30% of maximum
deviation.
The output of U407B is passed (signal LINE_INP) to the Line Level Sense circuitry
(sheet 3) so that the CPU can determine the input line level.
U407B’s output is also passed to the limiter defined by D402, and D401. Resistors
R442, and R444 are used to “soften” the clipping, i.e. to “round off” the edges as the
voltage hits the clipping levels. This reduces the level of the lower order harmonics
produced.
U407C then buffers the output for mixing with the tone output circuitry.
The PWR_CNTRL_RAW DAC output is used to control the bias to the on-board RF
amplifier (see Sheet 8). The CPU output pin PWR_CNTRL_HIGH is effectively
summed with the DAC output to define three control ranges:
State of PWR_CNTRL_HIGH
PWRCNTRL Voltage Range
TriState
2.98 – 5.86
Low (0V)
0.6 – 3.0
High (5V)
3.55 - 5.96
Table 9: Power Control Ranges.
Note that in practice only the first two power ranges are used.
U401 is an octal shift register and octal latch combined. When there is a rising edge on
LINEINP_DEN, the 8 shift register outputs are latched into the octal latch. The outputs
of the octal latch are the outputs Q0 to Q7. Thus the last 8 data bits clocked onto MOSI,
by SCLK, before LINEINP_DEN is clocked high, will appear on Q0 to Q7.
U406 is a quad 8 bit DAC. The CPU communicates with the DAC via SCLK, MOSI,
and the select signal LINEINP_ADSEL, which is low when the DAC is selected.
U302B is used to convert the DAC output into a bias level for the LCD. Note that, at
this stage, the LCD display option is not developed.
5.5 Tone Gener ation Section (Sheet 5)
U500 is a CTCSS tone encoder and decoder. The integrated circuit is also capable of
generating DCS signals.
The CPU accesses U500 via the serial bus using MOSI, SCLK, and the low active
Select signal CTCSS_SEL.
The output of the tone generator is mixed (summed) with any signals that are allowed
through analogue switch U301D.
U502 is set up as a balanced differential amplifier. The resistors R530, R531, R508,
R509, R510, R532, R533, and R511, are precision resistors to improve the CMRR of
the differential amplifier.
U502A amplifies, as well as mixes, the two audio inputs, and its output is either passed
through a low pass filter (at 250Hz), or not, depending on the state of analogue switch
U301A.
The output of U502C is then attenuated by a digital POT, before being buffered by
U502D.
14
The digital POT performs two functions. It is used to help set the maximum CTCSS
tone deviation. It does this in conjunction with U500, as it is also possible for the
CTCSS tones that are launched by U500 to be adjusted using software.
The second function of the digital POTs is enabled when U301D is enabled. The level
of attenuation by the digital POT is adjusted as part of the calibration procedure to set
the tone deviation caused when a signal is applied to the tone input.
R526, D502, and D503, form a limiter, that prevents any signal arriving from the TONE
pair from ever exceeding 3kHz deviation.
5.6 Fr equency Synthesiser (Sheet 6)
This circuit also includes Sheet 7 as a block diagram. Sheet 7 contains the schematic
for the two Voltage Controlled Oscillators.
There are two complete Phase Locked Loops. One is called the Modulation PLL, and
the other is referred to as the Channel PLL.
The Modulation PLL does change frequencies slightly, but by less than +/- 240kHz.
The Channel PLL is the principal PLL that changes frequencies when the exciter
changes frequency.
As its name suggests, modulation is performed on the Modulation PLL.
The modulation is a conventional 2 point FM modulation. Modulation by signals,
whose frequency components are well below the PLL loop frequency, is effected by
modulating the reference oscillator of the Modulation PLL. Frequencies well above the
PLL loop frequency are effected by modulating the Modulation VCO directly, and
frequencies in the cross-over region are a combination of the two.
The heart of this schematic are the two PLL chips U602, and U604.
Each is, in fact, a dual PLL chip, but only one PLL, in each, is used. All that is used of
the second PLL chip is its dividers. The outputs of these dividers can be switched to the
FoLD output pin, which is then converted to a square wave by a further division of 2 by
U606A and U606B.
By using the second PLL’s dividers it is possible to divide the reference oscillator, and
the VCO output down to frequencies that can be handled by the Timer inputs of the
CPU, without causing excessive interrupt load to the CPU.
5.6.1
The Modulation PLL
U602 and the Modulation VCO (see Sheet 7) form the modulation PLL. U602 acts as
its own crystal oscillator for its reference oscillator. X600 is a 5ppm, 12MHz, crystal.
Its resonant point is adjusted by the bias applied to varactor D600.
The bias applied to varactor D600 is a combination of the potentials at two DAC
outputs (MOD_ADJ and MOD_ADJ_FINE), plus the modulating signal arriving at
MOD_IN (which is the same signal as MOD_OUT in Sheet 3).
The summing of these three voltages is performed by U607.
The Phase detector output of the PLL chip is then passed through the loop filter network
defined by C612, R618, C625, R617, C613, and C718 (see Sheet 7). L713 is used to
filter out any residual noise (outside of the audio bandwidth), including the phase
detector frequency, and/or any switch-mode noise from the dc voltage rails.
The loop filter signal is then fed as a control voltage to the Modulation VCO
(MOD_PLL_IN).
15
The output of the Modulation VCO is connected back to the PLL for phase detection via
signal path MOD_VCO_OUT.
The phase detector output is also buffered and attenuated for the analogue input of the
CPU. This is the function of U600, R622, and R625. In this way the CPU can monitor
the VCO bias to ensure that it is within specification (>0.5V, and < 4.5V).
The FoLD pin, of U602, can be used for many purposes. It can be connected to the
output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as
a user programmable output pin. In this circuit it is used as a LOCK-DETECT output
when the frequency is being changed, but otherwise it is connected internally to the
unused reference divider of U602, to deliver a 400Hz pulse train to FoLD.
U602 is set up with a phase detector frequency of 20kHz.
5.6.2
The Channel PLL
U604 and the Channel VCO (see Sheet 7) form the Channel PLL. U604 acts as its own
crystal oscillator for its reference oscillator. X601 is a 5ppm, 12MHz, crystal. Its
resonant point is adjusted by the bias applied to varactor D601.
The bias applied to varactor D601 is adjusted by the CHAN_ADJ DAC output.
The Phase detector output of U604 is then passed through the loop filter network
defined by C622, R620, C626, R619, C623, and C725 (see Sheet 7). L718 is used to
filter out any residual noise (outside of the audio bandwidth), including the phase
detector frequency, and/or any switch-mode noise from the dc voltage rails.
The loop filter signal is then fed as a control voltage to the Channel VCO
(CHAN_PLL_IN).
The output of the Channel VCO is connected back to the PLL for phase detection via
signal path CHAN_VCO_OUT.
The phase detector output is also buffered and attenuated for the analogue input of the
CPU. This is the function of U608, R623, and R624. In this way the CPU can monitor
the VCO bias to ensure that it is within specification (>0.5V, and < 4.5V).
The FoLD pin, of U604, can be used for many purposes. It can be connected to the
output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as
a user programmable output pin. In this circuit it is used as a LOCK-DETECT output
when the frequency is being changed, but otherwise it is connected internally to the
unused reference divider of U604, to deliver a 400Hz pulse train to FoLD.
U604 is set up with a phase detector frequency of 31.25kHz.
The signal CHAN_VCO_EN is an output from the CPU that is used to turn on (when
High) or turn off (when low) the Channel VCO.
5.6.3
The External Reference Divider
The external Reference Input (EXT_REF_IN) is buffered by an attenuator network
formed by R628,R633, and R630 in parallel with R635. This also forms a 50 ohm
termination network for the reference input.
R628 is a 1 watt resistor, and so, in theory levels as high as +30dBm can be accepted.
To be safe, though, the largest signal that is approved to be accepted is +26dBm.
Q600 is set up as a switching transistor, and with a sufficiently high input signal level (>
+5dBm), it will clock U605.
U605 is set up as a divide by 128 circuit, and its output is then divided by U606 by 25.
16
The two unused, divide by two, stages of U606 are then used to convert the 400Hz
FoLD pulse trains into 200Hz square waves for the Timer inputs of the CPU.
5.6.4
The DAC
U601 is a quad DAC. It is programmed by the CPU via the serial bus (SCLK and
MOSI). It is selected by the low active signal SIGGEN_ADSEL.
Three of its outputs are used to adjust the reference oscillators.
In the presence of an external reference oscillator, the software will automatically track
the channel VCO to the external clock.
The modulation reference oscillator is always tracked as closely as possible to the
Channel reference oscillator. Because of this need for very close tracking, two DAC
outputs are summed. In this way, the CPU is given coarse, as well as fine control.
The CPU can sense a phase difference of 136ns in 4 seconds, i.e. as little as 0.034ppm
between the two PLL reference oscillators. Each step of the MOD_ADJ_FINE DAC
output will move the frequency about 2% of this amount.
The other DAC output (BALANCE) is used to adjust the BALANCE VCA (see sheet
7).
The user programmable digital output of the DAC (MOD_VCO_EN) is used to enable
the modulation VCO (when High)
5.6.5
The VCOs and the RF Output
These are more closely described in 5.7, but it is worth noting that there are three
primary outputs of the VCOs. There is each VCO output itself, but also the signal
VCO_OUT. This is the difference frequency between them.
Generally the modulation VCO is set to oscillate at 320MHz. To get an output of
40MHz, the Channel VCO is set to 280MHz.
But if you wanted an output frequency of, for example, 40.00125MHz, then the
modulation VCO would change to 319.78125 MHz (i.e. it drops by 218.75kHz), and the
Channel VCO would become 279.78MHz (i.e. dropping by 220kHz).
By such small changes in the modulation VCO (maximum delta is +/- 240kHz), each
multiple of 1250Hz can be accommodated, without any need to ever change the two
phase detector frequencies.
5.7 Voltage Contr olled Oscillator s (Sheet 7)
JFETS Q704, and Q705 are the heart of two Colpitts oscillators.
The capacitor feedback divider for Q704 (modulation VCO) is defined by C732 and
C733, and this shapes the negative impedance looking into the drain of Q704.
In the Channel VCO, C740 is effectively in series with Cgs of Q705. These, then define
the negative impedance looking into the drain of Q705.
L716, in parallel with L726 forms the tank coil for the modulation oscillator, and the
resonant capacitance is defined by the series combination of C750 and the capacitance
across D701. L712 has +ve reactance and it acts to reduce the minimum effective
capacitance seen back through C750, thereby increasing the tuning range slightly.
Similarly, L719 is the tank coil for the channel oscillator, and the resonant capacitance
is defined by the series combination of C751 and the capacitance across D704. L717
has +ve reactance and it acts to reduce the minimum effective capacitance seen back
through C751, thereby increasing the tuning range slightly.
17
The VCO frequencies are controlled by the bias applied to D701 and D704 respectively,
which is set by signals MOD_PLL_IN and CHAN_PLL_IN. These signals are the
phase detector outputs from the Modulation PLL and the Channel VCO respectively
(see Sheet 6).
Diodes D700 and D703 are used to provide some AGC for the JFETs. These Schottky
diodes will increase the –ve bias on the gate of the JFETs (thereby decreasing the drain
current) if the oscillation level should increase, and similarly the gate bias will reduce if
the –ve peaks of the oscillation should reduce.
The Modulation bias is also adjusted by the modulation input (MOD_IN). This signal is
amplified by a VCA. The BALANCE DAC output is converted to a current by U707
and Q700, and that then is used to set the gain of the VCA. The output of the VCA is
then attenuated by R725/R729, and this bias is then applied to varactor D701. Note that
the modulation bias is in anti-phase to the PLL bias.
Each VCO has its own gyrator feed circuit (Q707 and Q702). This is done to remove
any possible noise on the voltage rails from modulating either VCO.
The drain current of each VCO can be switched off or on by MOSFETs Q701 and
Q703. Q701 is switched on when MOD_VCO_EN is high. MOD_VCO_EN is the user
programmable digital output from DAC U601 (see Sheet 6). Q703 is switched on when
the CPU output CHAN_VCO_EN (see Sheet 2) is high.
The output of each VCO is “sniffed”, by a high impedance attenuator. In the
modulation VCO, R737 in series with the 50 ohm input impedance of U702 forms this
attenuator. In the Channel VCO, R745, R736, and the input impedance of U706 form
one such attenuator, and R741 in series with the input impedance of U703 forms the
other. Note that there is a low pass filter in the front of U702, and U706 to reduce the
level of spurious signals generated by intermod in these two amplifiers,
U702 amplifies the modulation VCO signal, which is then amplified again by U701,
then filtered to reduce harmonics, before arriving at the LO input of MX700 at a level of
around +5 - +7dBm. The output of U702 also has a low pass filter to reduce the level of
harmonics arriving at the mixer.
The output of the MOD VCO is also attenuated by R733, and then re-amplified before
becoming MOD_VCO_OUT. MOD_VCO_OUT is then passed to the Modulation PLL
(U602, see Sheet 6).
U705’s primary role is to ensure that noise that becomes coupled by the PLL chip, back
onto its VCO input, does not couple back into the path to the mixer. If this isn’t done,
then the mixer’s LO input contains many harmonics of the reference oscillator.
U703 performs both an amplification role, and an isolation role similar to U703’s. Its
output (CHAN_VCO__OUT) is fed back to the Channel PLL (U604, see Sheet 6).
The output of U706 is attenuated by the network R714, R742, and R724, and it is
filtered to reduce harmonics as much as possible. This filtered VCO output is then
brought to the RF pin of the mixer at a level of about –19dBm.
The output of the mixer is then run through a low pass filter to remove frequencies other
than (Fmod - Fvco). U700 then amplifies this signal to a level of about –6 to –8dBm.
The external output signal of T/R_RELAY, which is asserted low whenever the exciter
is keyed up, is used to switch MOSFET Q706 off. When Q706 is off, amplifier U700 is
enabled. When T/R_RELAY is high, then U700 is deprived of bias current and
VCO_OUT is then completely disabled.
18
5.8 1W Br oadband HF/VHF Power Amplifier (Sheet 8)
The RF output of Sheet 7 (VCO_OUT) becomes the primary input to this circuit
(RF_IN).
This RF input is first amplified to a level of about +2 to +4dBm by U800, then it is
amplified by Q801 to about +20dBm (with full bias), and then it is amplified by Q804
and Q805 to +30dBm. The output stage gain is less above about 42MHz, so that the
peak output power falls to about +26dBm at 50MHz.
The effective gain of Q801 is controlled by adjusting the bias level (PWRCNTRL).
This can vary from 0.6V to nearly 6V, and is adjusted by a DAC output and a CPU
digital output, in Sheet 4.
The software monitors the forward power sense in the External Power Amplifier(PA) as
well as the Reverse Power, temperatures, drain currents etc. It does this via the serial
bus (formed by SCLK and MOSI) and the select pin for the ADC converter on the
External PA (PA_CS).
The software then automatically adjusts the PWRCNTRL bias to:
1)
Keep the forward power at the level defined by parameter PA_SET_FWD_PWR
(see 4.1), unless,
2)
If the reverse power is > PA_SET_FWD_PWR*REV_PWR_ALARM/100.0
then the forward power is reduced until the reverse power stops exceeding this
limit, or,
3)
The temperature of the PA output stage FETs exceeds 120C, in which case
forward power is reduced until this stops occurring.
5.9 Power Generation Section (Sheet 9)
There are three switch mode dc-dc converters in the board. These use monolithic
converters based on the National LM2595. Two of the converters are 12V converters
and one is a 5V converter.
The power in to the whole exciter is the voltage rail 28V.
U907 converts this down to 12V.
U908 is set up as an inverter, and uses the 12V rail to create –12V.
U909 converts the +12V rail to +5V for all the digital circuitry.
The +12V rail is used to power the on-board relay, as well as up to one extra off-board
relay. It is also dropped, via a linear regulator (U910) to produce the +10V rail, which
in turn is dropped by another linear regulator U911 to produce +5Q, which, in turn, is
dropped by a further linear regulator (U912) to produce +2.5V.
Similarly U913, U914, and U915 are linear regulators that produce –10V, -5V, and –
2.5V from the –12V output of U908.
+10, +5Q, and +2.5V, -10V, -5V, and –2.5V rails are used in the audio and RF sections.
D911 is a 4.096V (3%) reference diode. Its output is buffered by U906 which then
produces a reference voltage rail Vref, which is used by the CPU’s A/D converter, and
the DACs, and also in the voltage to current converters of the VCAs (see Sheet 4, and
Sheet 7).
19
6 FIELD ALIGNMENT PROCEDURE
6.1 Standar d Test Equipment
Some, or all of the following equipment will be required:
•
AF signal generator, 75 - 3000Hz frequency range, with output level set to 387mV
RMS and, if the microphone input is to be tested, 10mV rms output.
•
Power supply set to 28Vdc, with current >10A.
•
RF 50Ω load(s), 250W rated, return loss <-20dB, and total attenuation of 50dB
•
Reference Clock. At least +6dBm output.
The external reference frequency is limited to:
500kHz, or any multiple,
any multiple of 128KHz greater than or equal to 512kHz,
any multiple of 160KHz greater than or equal to 480kHz
In Rev 4 or earlier revision systems, the external reference clock is limited to 10MHz.
In Rev 5 or later systems, the external reference clock can be as high as 24 MHz, and
can have an output level as low as 0dBm. The accuracy should be at least 0.5ppm,
preferably 0.1ppm
•
RF Peak Deviation Meter
•
True RMS AC voltmeter, and a DC voltmeter.
•
RF Power Meter (accurate to 2%, i.e. 0.17dB)
•
Some means of measuring Reverse Power, and a known 3:1 mismatched load.
6.2 Invoking the Calibration Pr ocedur e Manually
From Version 4 of the firmware, and version 1.4 of WinTekHelp, the calibration
procedure can be performed through a Windows front end program. This is
documented in the WinTekHelp manual.
As well as the Windows based calibration procedure, the firmware still supports the
older command prompt method, which is described in this section.
The T50 has in-built firmware to perform calibration. This firmware requests the user
for information as to meter readings, and/or to attach or adjust an AF signal generator.
The firmware based calibration program can be accessed from a terminal, a terminal
emulator, or the WinTekHelp terminal emulator.
If the user selects the “Go to the Prompt Window” option from the main menu, they can
manually type commands to invoke the calibration procedure. When the exciter is
ready to accept commands it echoes the following prompt:
T50>
Via a terminal, or a terminal emulator, a user can type various commands in. The basic
command to start the calibration procedure is:
T50> cal calibration_type
Where “calibration_type” is one of:
a)
misc: Miscellaneous parameters are defined and calibrated
20
b)
c)
d)
e)
f)
6.2.1
dev: Maximum deviations are set (automatically forces a “cal line” and a “cal
tone”)
line: Line1, Line 2, Dir Aud (Tone), and microphone inputs are tested and
calibrated.
pwr: The External PA attached to this unit is calibrated.
ref: The reference oscillators are adjusted and calibrated
tone: The maximum tone deviations are calibrated
The “ Miscellaneous” Calibration Procedure
T50> cal misc
This procedure should not normally be invoked as part of any field maintenance.
The program will print out the Model Name and Serial Number of the exciter. If these
parameters haven’t already been defined (e.g. at an initial calibration, at the factory, the
service personnel will be prompted to enter these values).
Then it will ask the operator to enter the value of Vref (as measured at TP913, see 5.9).
Measure the voltage, at TP913 (Vref)
and type it on the command line...
Unless the reference diode D911 has been replaced, this should not be done. The user
should simply hit the Enter key to bypass this operation. If, though, D911 has been
replaced for some reason, then, the reference voltage can be measured either on TP913
or pin 4 of P3.
Then the exciter low battery alarm level will be asked for. If the current value is
acceptable, the User need only hit the Enter key on the keyboard. If another value is
preferred, then that value can be typed in.
For example:
The Exciter's Low Battery Alarm is 24V
If this is correct enter < RET> ,
else enter the new value: 26
In this example, the low Battery Alarm level is changed to 26V.
Then the user will be prompted for serial port baud rates, parities etc. At present only
No parity and No flow control are supported. The WinTekHelp software will expect
57600 BPS, and No Parity, and No Flow Control. Note well, that if you do change any
of these, the change will not take effect until you power down the exciter and then
power it up again. (As an alternative to power cycling the exciter, and if the cover is off
the exciter, you may simply press the momentary push-button switch S200 (see 5.2).
The next thing the calibration program tests is the state of the LINE pot. The program
will ask the user to adjust this pot. If the Potentiometer is below centre, it will ask the
user to adjust it up (i.e. adjust it clockwise). If it is above centre, it will ask the user to
adjust it down (i.e. adjust it counter clockwise). When the POT has been centred, or,
the User hits the Enter key, the program will terminate.
This last step is normally only done as part of a factory install, and it is done to ensure
that the POT is centred before being shipped to customers. For field maintenance
purposes, the step should be skipped in order to leave the LINE POT at the setting
formerly desired.
6.2.2
The “ Reference” Calibration Procedure
T50> cal ref
21
To compensate for crystal ageing and other component parameters that drift over time,
the following procedure should be performed approximately once per year.
If your exciter is fitted with the external reference option (an extra BNC connector on
the rear panel), the user can connect an external reference directly to the rear BNC
connector. If the exciter does not have this option, then the top cover of the exciter
should be removed and an external reference oscillator should be connected via a 50
ohm probe to J4 (just to the right of the DC voltage regulators and converters).
The external reference clock, should have a power level from +6 to +26dBm and any
frequency that meets the following criteria:
500kHz, or any multiple, or,
any multiple of 128KHz, greater than or equal to 512kHz, or,
any multiple of 160KHz, greater than or equal to 480kHz.
The frequency should be 10MHz or less in Rev 4 or older versions. In Rev 5, and later
versions the frequency can be as high as 24MHz, and at power levels as low as 0dBm.
No User input is required, except to hit the Enter key when the external reference is
connected. The firmware will automatically adjust both reference oscillators, and save
the new DAC adjustments in FLASH (as parameters) to be used to centre the oscillators
each time the unit powers up.
The user should see the following output. (Note that the temperatures, frequencies,
error values, serial number, etc, indicated are examples only)
Connect an external reference input or the clock output
from a GPS receiver to the GPS input.
Enter < RET> when this has been done.
External Reference is 10.0MHz
Ensure that the displayed reference frequency (10.0MHz in the above example) is the
same as the frequency of your oscillator.
Waiting for a GPS clock.
......
The system waits here for a GPS reference to be seen. At this stage, this method of
calibrating the clocks has not been validated by RFT Engineering, so do not attempt to
use this option.
Then the firmware continues.
Have not observed a GPS clock
System Frequency relative to external clock is 7372654.32
The crystal temperature is 32C.
Waiting up to 1 minute for clocks to stabilise.
......
The crystal temperature is 32 C
The channel ref error = 1 cnts or, 1.63 Hz
The mod ref error = 1 cnts or, 1.63Hz
The user may see the following error message.
The Model Name is T50_REV4
and the Serial Number is RT11500
Please take note of the Model, DAC values, serial number and
crystal temperature, and report this problem to RFT Engineering.
22
If a message, similar to this is seen, it indicates a potential fault condition. If the final
text indicates that the channel and mod reference errors are within specification (the last
text output), then the unit is able to be used, but nonetheless, it is advisable that an email be sent to RF Technology indicating the problem. Such a problem may be caused
by a crystal having aged to such an extent, that it is getting close to the region where it
may soon, no longer be adjusted, or that, with further degradation, the low frequency
performance may be compromised.
As no other calibration procedure requires the top cover to be removed, you should
replace the cover, should you have had to remove it for this procedure.
6.2.3
The “ Deviation” Calibration Procedure
T50> cal dev
This procedure should not normally be invoked as part of any field maintenance. The
only conceivable time that it might ever be used, would be if a non standard maximum
deviation was required.
Note that the nominal output power of the exciter’s output is 1W. Whilst the power
level is not set to the maximum level, the deviation meter should either have an input
power rating of at least +30dBm, or suitable attenuation is required between the exciter
and the deviation meter. Note that for this test the nominal RF output frequency is
37.5MHz.
The first stage begins with the following message:
This procedure sets the Balance and Max Deviation Levels
Connect an audio signal generator to the External Tone input
Set the output to be a sine wave, 3.87 V rms and 120Hz
Disconnect the RF connection to the PA
and connect a deviation meter to the exciter's BNC output,
and use a CRO to monitor the Audio output from the deviation meter.
The Channel VCO Bias is 2.5V
The Modulation VCO Bias is 2.3V.
Enter + or – to increase or decrease the Balance, until the
CRO signal is as symmetric as possible.
?
Here the user can hit the +, p, or P, keys to increase the Balance, or -, m, or M keys to
decrease it. In response, the firmware, which has opened up the maximum deviation
digital POT (U303) to maximum gain, will adjusted the Balance VCA accordingly.
This test applies a very high level to the External Tone Input which becomes “saturated”
by the limiter for the Tone input. The result is a square wave with a slight ring on the
edges. The ringing is caused by the elliptical filter used as a 3kHz low pass filter.
If the modulation balance is not working properly, the top edges of the resulting
modulated signal will be slewed.
Then the firmware will make the following request.
change the signal input to Line 1, and adjust the frequency till the
deviation peaks
When this has been done, the User needs to hit the Enter key, and the following will
appear again.
Enter + or - to increase or decrease the deviation,
and < RET> when the deviation is 5kHz
23
?
In response to the +, or – keys (or m, p, M, or P), the firmware adjusts the deviation
digital POT. The user should do this until the deviation is about 200Hz below the value
shown.
The firmware will now repeat this for the following standard deviations, 5.0kHz,
4.5kHz, 4.0kHz, 3.5kHz, 3.0kHz, 2.5kHz, 2.0kHz, and 1.5kHz.
6.2.4
The “ Tone Deviation” Calibration Procedure
T50> cal tone
This procedure should not normally be invoked as part of any field maintenance.
Note that if the deviations are calibrated, then this procedure will be automatically
invoked.
This procedure is similar to the maximum deviation procedure (See 6.5). The Line 1
and Line 2 audio paths are turned off for this procedure, as is the Direct Audio (TONE)
input. The only signal sent to the modulator is a tone of 107.2Hz.
The program starts off, with the following message:
This procedure sets the maximum tone deviations for a
Max Deviation of 5kHz. Note that the actual maximum
tone deviations automatically scale with the Max Deviation.
eg a 500Hz tone deviation would be a 250Hz tone deviation
when a 2.5kHz Max Deviation was chosen.
Disconnect the RF connection to the PA,
and connect a deviation meter to the exciter's BNC output.
The audio is being switched off, and 107.2Hz tone generated
Thence a procedure that is almost identical to that used for setting maximum deviations
is used to set these tone deviations. There is one significant difference, though, and that
is, as well as using + (or p, or P), and – (or m, or M) keys to step the deviation up or
down, one can also use the < key, or the > key. These last two keys will step down, or
up, the level of signal transmitted by U500, whereas the other keys will modify the
setting of the digital POT U503 (see 5.5).
This procedure is used to set tone deviations of 750Hz, 700Hz, 650Hz, 600Hz, 550Hz,
500Hz, etc down to 150Hz.
6.2.5
The “ Line” Calibration Procedure
T50> cal line
This procedure should not be used as part of any usual field maintenance, unless any
component has been replaced that might affect the gain of any of the audio inputs.
Note that if the deviations are calibrated, then this procedure will be automatically
invoked.
The program begins:
Calibrating Line 1 and Line 2 audio levels
Attach an audio signal generator to Line 1
Set the output to be a sine wave, 388mV rms and 1kHz
Disconnect the RF connection to the PA
and connect a deviation meter to the exciter's BNC output.
Enter + or - to increase or decrease the deviation,
and < RET> when the deviation is 3kHz.
?
24
This is the same mechanism that is used in 6.5 and 6.6. The user enters +, p, or P to
increase the Line 1 gain, to increase the deviation, or, -, m, or M to decrease the gain.
The user hits the Enter key when the desired deviation is set.
Now attach the audio signal generator to Line 2
Enter + or - to increase or decrease the deviation,
and < RET> when the deviation is 3kHz
?
Again the user enters +, p, or P to increase the Line 2 gain, or, -, m, or M to decrease the
gain. The user hits the Enter key when the desired deviation is set.
The firmware goes on to open the microphone audio path (note that the microphone
PTT switch does not need to be depressed for this). Note also that the application of a
10mV test input is a factory only test. An adequate test in field testing, would be to
speak into the microphone and see that the deviation meter responded accordingly.
Testing the microphone input.
Attach an audio signal generator to the microphone input.
Set the output to be a sine wave, 10mV rms and 1kHz.
Ensure that the deviation is between 2.7 and 3.3kHz
Enter < RET> when measurement complete.
Alert Engineering if there is a failure.
Then the Direct Audio input (with the low pass filter off) is tested.
Testing the Tone input.
Attach an audio signal generator to the Tone input.
Set the output to be a sine wave, 129mV rms, and 1kHz.
Enter + or - to increase or decrease the deviation,
and < RET> when the deviation is 1kHz
?
And then user then follows the same procedure as defined for setting the Line 1 and
Line 2 gains.
6.2.6
The “ Power” Calibration Procedure
T50> cal pwr
All Power Amplifiers are calibrated ex-factory. All the important parameters, such as
the forward and reverse power sense adjustment, and drain bias settings are not
dependent on the exciter, and thus any factory calibrated PA50 power amplifier can be
connected to, and work correctly with any T50 exciter. The frequency range of the
amplifier is defined by three jumper settings on the external PA, which the CPU can
detect. Thus the CPU knows (on power up) what frequencies are, or are not, possible to
be used with the PA.
The exciter may store some PA specific parameters, such as the Serial Number of the
PA, and also some offset values for the pre-amp drain current, and the output stage
drain current. These latter offsets improve the accuracy of the over current alarm
testing, (but are not strictly necessary). In order to set these parameters, it is advised
that this procedure be performed every time an exciter is used with a new External
Power Amplifier. Note that many of the stages can be skipped if they have been
performed before.
The program begins:
25
This procedure is used to calibrate an External Power Amplifier.
The existing PA's SERIAL NO is: 002356
Enter the new PA serial no:
Simply hit the Enter key here if the Serial Number is correct.
Take the lid off a PA, and set all three
bias Pots (R238,R239, and R240) fully clockwise.
Enter < RET> when done.
Now we will set the Bias currents in the PA.
Attach power to the PA.
Each mV read across TP100(+ ve lead), and TP101(-ve lead),
corresponds to 1mA of 1st stage Bias current.
For power control in the range 50 - 150W,
set the 1st stage bias to 35 - 40mA.
For power control in the range 20 - 60W, use a bias of 15 - 20mA.
Attach the millivoltmeter, and
adjust R238 for the bias required.
Unless one of the RF power transistors has been replaced, the user should simply skip
these last four stages by hitting the Enter key four times.
Attach the Power Amplifier to the Exciter,
and ensure the PA is powered up.
Attach the PA output to a reflectometer, the reflectometer to a 50dB
(nominal) attenuator, and the attenuator to a calibrated power
meter
Enter < RET> when this has been done
Adjust C209 in the Power Amplifier
until there is a minimum in the dc voltage measured at TP204
Enter < RET> when done.
Adjust the Forward Power Sense POT (R228) unti
tthe measured output power (adjusted for the attenuator and
reflectometer losses) is equal to the Preset Forward Power.
Enter < RET> when done.
Unless something has been modified in the power sense circuits, these last three stages
should be skipped by simply hitting the Enter key three times.
This next step allows the firmware to compute an offset in the output stage drain
current, so that the exciter’s ability to measure the output stage drain current is
significantly more accurate.
Measure the voltage across TP102(+ ve lead)
and TP103(-ve lead), and enter the value measured
This next step allows the firmware to compute an offset in the pre-amp stage drain
current, so that the exciter’s ability to measure the pre-amp stage drain current is
significantly more accurate.
Measure the voltage across TP100(+ ve lead)
and TP101(-ve lead), and enter the value measured
The next two stages can be skipped by simply hitting the Enter key twice.
Attach the reflectometer to an open circuit
Enter < RET> when this has been done
Adjust the Reverse Power Sense POT (R227) until
26
the displayed reverse power equals 50W.
Enter < RET> when this has been done.
This then completes all the calibration procedures.
7 SPECIFICATIONS
7.1 Over all Descr iption
The transmitter is a frequency synthesized, narrow band, HF/VHF, FM unit, used to
drive an external 120 watt amplifier. All necessary control and 600 Ω line interface
circuitry is included.
7.1.1
Channel Capacity
Although most applications are single channel, the T50 can be programmed for up to
256 channels, numbered 0-255. This allows a network administrator to program every
exciter, in every site, the same way. By setting each site up to select which of the 256
channels is appropriate, any exciter can be plugged into any position, in any site,
without the need to perform on-site re-programming. This can be convenient in
maintenance situations.
Channel information consists of two independent and complete sets of information,
which may differ or be the same. One set defines the parameters to be used, if the unit
is keyed up from PTT-in being “grounded”, and the other set defines the parameters to
be used if the unit is keyed up for any reason other than PTT-in being “grounded”.
The parameters that can be defined on a per channel basis are:
7.1.2
a)
The frequency
b)
The CTCSS tone (if any) to be generated, or, the DCS code (if any) to be
generated.
c)
The delay from the initiation of the exciter to RF output being generated
(Is specified in hundredths of a second, 0 – 999)
d)
The transmit tail; the length of time after the exciter is released before
transmission stops. (Is specified in seconds 0 – 999).
e)
The No Tone period; a length of time after the expiry of (d) in which
transmission continues, but with no tone being generated. (Is specified in
tenths of a second, 0 –999)
f)
Whether audio from Line 1, or Line 2, or both, (or neither!) is enabled,
and whether or not Pre-emphasis is required, or not, on each line, and
whether or not an extra gain pad (of 20dB) is required.
g)
What Nominal Tone Deviation, and Maximum Deviation should be used
(See Tables 7 and 8)
CTCSS
Full EIA subtone Capability is built into the modules. The CTCSS tone can be
programmed for each channel. This means that each channel number can represent a
unique RF and tone frequency combination.
7.1.3
DCS
From Rev. 4 hardware and Rev. 4 firmware, support for DCS codes is supported. DCS
code generation can be enabled on a per channel basis. If enabled, the 23 bit Golay
27
code containing the selected DCS code word will be generated continuously after the
exciter is keyed up.
7.1.4
Channel Programming
The channel information is stored in non-volatile memory and can be programmed via
the front panel connector using a PC, and/or RF Technology software.
7.1.5
Channel Selection
Channel selection is by eight channel select lines connected to the rear panel that
mounts on the rear DB25 female connector.
A BCD active high code applied to the lines selects the required channel. This can be
supplied by pre-wiring the rack connector so that each rack position is dedicated to a
fixed channel. Alternatively, thumb-wheel switch panels are available.
By redefining “illegal” BCD codes, users can also encode channels from 100 – 255.
7.1.6
Microprocessor
A microprocessor is used to control the synthesizer, tone squelch, PTT functions,
external reference monitoring, calibration, fault monitoring and reporting, output power
level control, volume adjustment, line selection, option setting, and facilitate channel
frequency programming.
7.2 Physical Configur ation
The transmitter is designed to fit in a 19 inch rack mounted sub-frame. The installed
height is 4 RU (178 mm) and the depth is 350 mm. The transmitter is 63.5 mm or two
Eclipse modules wide.
7.3 Fr ont Panel Contr ols, Indicator s, and Test Points
7.3.1
Controls
Transmitter Key - Momentary Contact Push Button
Line Input Level - screwdriver adjust multi-turn pot
7.3.2
Indicators
Power ON - Green LED
Tx Indicator - Yellow LED
Fault Indicator - Flashing Red LED
7.3.3
Test Points
There are no front panel test points. All important test points are monitored by the
firmware.
7.4 Electr ical Specifications
7.4.1
Power Requirements
Operating Voltage - 16 to 32 Vdc
Current Drain – 0.33A Maximum, typically 0.32A Standby
Polarity - Negative Ground
28
7.4.2
Frequency Range and Channel Spacing
The T50, as a single model, covers the full band, and all channel spacing.
Frequency
25 kHz
20kHz 15kHz 12.5 kHz
10 kHz
7.5 kHz
6.25 kHz
25 - 50 MHz
T50
T50
T50
T50
T50
7.4.3
T50
T50
Frequency Synthesizer Step Size
The specified frequency can be any multiple of 1250Hz.
7.4.4
Frequency Stability
±5 ppm over 0 to +60 C, standard
±12 ppm over -30 to +60 C.
7.4.5
Number of Channels
256, numbered 00 - 255
7.4.6
Output power
The T50 needs an external PA50 power amplifier.
The output power is factory set to 100W by default, the reverse power level is set to
fold back the output power when the PA50 sees a load with VSWR of 3:1 or higher (i.e.
when the reverse power is 25% or more of the forward power).
7.4.7
Transmit Duty Cycle
100%
7.4.8
Spurious and Harmonics
Less than 0.25µW, when connected to a PA50 operating at an output power level of
100W.
7.4.9
Carrier and Modulation Attack Time
Less than 36ms (Rev 3 and Rev 4).
Less than 20ms (Rev 5 or higher).
7.4.10
Modulation
Type - Two point direct FM with optional pre-emphasis
Frequency Response - ±1 dB of the selected characteristic from 300-3000Hz
Maximum Deviation - Maximum deviation set on a per channel basis to 1.5, 2.0, 2.5,
3.0, 3.5, 4.0, 4.5, or 5.0 kHz.
7.4.11
Distortion
Modulation distortion is less than 3% at 1 kHz and 60% of rated system deviation.
7.4.12
Residual Modulation and Noise
The residual modulation and noise in the range 300 - 3000 Hz is typically less than 50dB with 5kHz maximum deviation (i.e. a test level of 3kHz).
7.4.13
600Ω Line Input Sensitivity
Adjustable from -32 to +12 dBm for rated deviation on two symmetric, independent,
transformer coupled Line inputs.
29
7.4.14
Test Microphone Input
200Ω dynamic, with PTT
7.4.15
External Tone Input
Compatible with all RF Technology receivers. Each unit is factory configured to give
20% of maximum deviation for an external tone input of 129mV.
7.4.16
T/R Relay Driver
An open drain MOSFET output is provided to operate an antenna change over relay or
solid state switch. The transistor can sink up to 250mA. A 1W flywheel diode connects
to the 12V rail to prevent damage to the FET from inductive kick from a relay coil.
7.4.17
Channel Select Input/Output
Coding - 8 lines, BCD coded 00 – 99; illegal BCD codes used to encode channels
100 – 255.
If the MSN (Most Significant Nibble) is greater than 9, then the channel number is
defined by the formula:
16*MSN + LSN;
where the LSN is the Least Significant Nibble.
If the MSN is less than 9, but the LSN is greater than 9, then the channel number is
defined by the formula:
10*LSN+MSN;
Logic Input Levels - High for <1.5V, Low for >3.5V
Internal pull up resistors select channel 00 when all inputs are O/C.
7.4.18
DC Remote Keying
An opto-coupler input is provided to enable dc loop keying over balanced lines or local
connections. The circuit can be connected to operate through the 600Ω line.
7.4.19
PTT in
An external input that when “grounded” with at least 1mA of current, will cause the
exciter to key up. The current is drawn from the PTT in input which attempts to “pull
up” anything that “grounds” it. It can be “grounded” with a short to 0V, or any
resistance up to 3.9k ohm. If the resistance of the “ground connection” is less than 2.2k
ohms, then up to three diodes in series can be part of the grounding path. This allows
systems installers to use quite complex diode logic to enable or disable exciters.
It would normally be “grounded” by the COS output of a receiver.
7.4.20
Programmable No-Tone Period
A No-Tone period can be appended to the end of each transmission to aid in eliminating
squelch tail noise which may be heard in mobiles with slow turn off decoders. The NoTone period can be set from 0-99.9 seconds in 0.1 second increments.
7.4.21
Firmware Timers
The controller firmware includes some programmable timer functions.
Repeater Hang Time(Transmit Tail) - A short delay or ``Hang Time'' can be
programmed to be added to the end of transmissions. This is usually used in talk
through repeater applications to prevent the repeater from dropping out between mobile
30
transmissions. The Hang Time can be individually set on each channel for 0 - 999
seconds.
Time Out Timer - A time-out or transmission time limit can be programmed to
automatically turn the transmitter off. The time limit can be set from 0-10million
seconds. The timer is automatically reset when the PTT input is released. Zero seconds
disables the timer, and allows continuous transmission.
7.4.22
CTCSS
CTCSS tones can be provided by an internal encoder or by an external source connected
to the external tone input. The internal CTCSS encoding provides programmable
encoding of any tone, accurate to 0.1Hz, including all EIA tones, from 67.0Hz to
257Hz.
7.4.23
DCS codes
DCS codes can be generated. The 9 bit DCS codes can be specified as a 3 digit octal
number and individual codes can be assigned to each channel. The exciter computes the
23 bit golay code for each DCS code, which is then continuously transmitted as NRZ
data at a bit rate of 134.4 bits per second when the exciter has keyed up. This feature is
only available from Rev. 4 units or later revisions.
7.4.24
CWID
CWID messages are transmitted as Morse Code streams. The transmit rate is a nominal
20 words per minute. Each “dot” is a burst of 1028Hz tone at a deviation level of
1.5kHz for 60ms. Each “dash” is the same tone, at the same level for 180ms.
7.5 Connector s
7.5.1
RF Output Connector
BNC connector on the module rear panel.
7.5.2
Power & I/O Connector
25-pin “D” Female Mounted at the top of the rear panel
7.5.3
External Reference Connector (optional)
BNC connector mounted in the middle of the rear panel connector.
31
A
Engineering Diagrams
There is only one printed circuit board covering all models of the T50. There is only
one option for this product, which is the external reference clock option. That option
adds a rear connector, and a small length of coaxial cable and a fixed coaxial cable
mount to the parts list.
Unlike other products in the Eclipse range, CTCSS is no longer an option. All units
have the ability to transmit CTCSS tones, and from Rev. 4, DCS codes.
A.1
Block Diagr am
Figure 1 shows the block signal flow diagram.
A.2
Cir cuit Diagr ams
Figure 2 shows the detailed circuit diagram with component numbers and values for the
main (exciter) PCB. Figure 3 shows the detailed circuit diagram with component
numbers and values for the higher-power PA variation. Figure 4 shows the detailed
circuit diagram with component numbers and values for the lower-power PA variation.
A.3
Component Over lay Diagr ams
Figure 5 shows the PCB overlay guide with component positions for the main (exciter)
PCB. Figure 6 shows the detailed circuit diagram with component numbers and values
for the higher-power PA variation. Figure 7 shows the detailed circuit diagram with
component numbers and values for the lower power PA variation.
32
B T50 Parts List (Rev 4)
Ref
Descr iption
Par t #
C100
C101
C102
C103
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
C214
C215
C216
C217
C219
C220
C221
C222
C224
C225
C226
C227
C300
C301
C302
C304
C305
C306
C307
C308
C309
C310
C311
C312
C400
C401
C402
C403
C404
C405
C406
C407
C408
C409
C410
C411
C412
C413
C414
C415
C416
C417
C418
C419
C420
C421
Four EMI filters in a 1206 package, 100pF
Four EMI filters in a 1206 package, 100pF
Four EMI filters in a 1206 package, 100pF
Four EMI filters in a 1206 package, 100pF
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
3u3F SMD, Electrolytic cap, A body, 10%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
22uF Electrolytic Capacitor, 35V, Bipolar
22uF Electrolytic Capacitor, 35V, Bipolar
2n2F Cer. Cap, NPO, 1206, 5%
3u3F SMD, Electrolytic cap, A body, 10%
10nF Cer. Cap, NPO, 1206, 5%
120pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
15uF SMD, low ESR Electrolytic cap, C body
10nF Cer. Cap, X7R, 0603, 10%
3n3F Cer. Cap, NPO, 1206, 5%
3n3F Cer. Cap, NPO, 1206, 5%
3n3F Cer. Cap, NPO, 1206, 5%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
1nF, 25V, X7R, 0603
34/NFA3/1100
34/NFA3/1100
34/NFA3/1100
34/NFA3/1100
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63X1/010N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
42/STA1/03U3
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
41/BP01/022U
41/BP01/022U
46/26N1/02N2
42/STA1/03U3
46/26N1/010N
46/63N1/120P
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
45/X7R1/1U16
41/SELC/015U
46/63X1/010N
46/26N1/03N3
46/26N1/03N3
46/26N1/03N3
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63X1/001N
33
C422
C423
C425
C426
C427
C428
C500
C501
C502
C503
C506
C507
C508
C509
C510
C511
C512
C513
C514
C515
C516
C600
C601
C602
C603
C604
C605
C606
C607
C608
C609
C610
C611
C612
C613
C614
C615
C616
C617
C619
C620
C621
C622
C623
C624
C625
C626
C627
C628
C629
C630
C631
C634
C635
C636
C637
C638
C639
C640
C641
C642
C643
C644
C645
C646
C649
C650
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
Ceramic Capacitor, 16V, 1uF, X7R, 1206
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
22pF Cer. Cap, NPO, 0603, 5%
22pF Cer. Cap, NPO, 0603, 5%
Ceramic Capacitor, 16V, 1uF, X7R
100nF, 25V, Y5V, decoupler, 0603
100pF Cer. Cap, NPO, 0603, 5%
100pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
15uF SMD, low ESR Electrolytic cap, C body
15uF SMD, low ESR Electrolytic cap, C body
Ceramic Capacitor, 16V, 22nF, X7R,10%
100nF, 50V, NPO, TH, 5mm
1n2F Cer. Cap, NPO, 1206, 5%
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
Ceramic Capacitor, 16V, 1uF, X7R, 1206
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
Ceramic Capacitor, 16V, 1uF, X7R, 1206
10nF Cer. Cap, X7R, 0603, 10%
470pF Cer. Cap, NPO, 0603, 5%
1nF Cer. Cap, X7R, 0603, 10%
470nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 220nF, X7R, 10%
15pF Cer. Cap, NPO, 0603, 5%
3p3F Cer. Cap, NPO, 0603, 5%
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
33pF Cer. Cap, NPO, 0603, 5%
Ceramic Capacitor, 16V, 1uF, X7R, 1206
470nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 220nF, X7R, 10%
Ceramic Capacitor, 16V, 1uF, X7R, 1206
3u3F SMD, Electrolytic cap, A body, 10%
3u3F SMD, Electrolytic cap, A body, 10%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
Ceramic Capacitor, 16V, 1uF, X7R, 1206
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
8p2F Cer. Cap, NPO, 0603, 5%
10nF Cer. Cap, X7R, 0603, 10%
56pF Cer. Cap, NPO, 0603, 5%
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
8p2F Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
100pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
Ceramic Capacitor, 16V, 1uF, X7R, 1206
10pF Cer. Cap, NPO, 0603, 5%
10pF Cer. Cap, NPO, 0603, 5%
34
46/63Y1/100N
45/X7R1/1U16
45/X7R1/1U16
46/63Y1/100N
46/63Y1/100N
45/X7R1/1U16
46/63N1/022P
46/63N1/022P
45/X7R1/1U16
46/63Y1/100N
46/63N1/100P
46/63N1/100P
46/63Y1/100N
45/X7R1/1U16
46/63Y1/100N
46/63Y1/100N
41/SELC/015U
41/SELC/015U
45/X7R1/022N
47/2007/100N
46/26N1/01N2
46/63X1/010N
46/63Y1/100N
46/63X1/010N
46/63X1/010N
45/X7R1/1U16
46/63X1/010N
46/63Y1/100N
45/X7R1/1U16
45/X7R1/1U16
46/63X1/010N
46/63N1/470P
46/63X1/001N
46/63Y1/470N
45/X7R1/220N
46/63N1/015P
46/63N1/03P3
46/63X1/010N
46/63Y1/100N
45/X7R1/1U16
46/63N1/033P
45/X7R1/1U16
46/63Y1/470N
45/X7R1/220N
45/X7R1/1U16
42/STA1/03U3
42/STA1/03U3
46/63Y1/100N
46/63Y1/100N
45/X7R1/1U16
45/X7R1/1U16
46/63X1/010N
46/63X1/010N
46/63N1/08P2
46/63X1/010N
46/63N1/056P
46/63X1/010N
46/63Y1/100N
46/63N1/08P2
46/63Y1/100N
46/63N1/100P
46/63Y1/100N
46/63Y1/100N
45/X7R1/1U16
45/X7R1/1U16
46/63N1/010P
46/63N1/010P
C651
C652
C700
C701
C702
C703
C704
C705
C706
C707
C708
C709
C710
C711
C712
C713
C714
C715
C716
C718
C719
C720
C721
C722
C723
C724
C725
C726
C727
C728
C729
C730
C731
C732
C733
C734
C735
C736
C737
C738
C739
C740
C742
C743
C744
C745
C746
C747
C748
C749
C750
C751
C752
C753
C754
C755
C756
C757
C758
C759
C760
C761
C762
C763
C764
C765
C766
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
220pF Cer. Cap, NPO, 0603, 5%
220pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
220pF Cer. Cap, NPO, 0603, 5%
220pF Cer. Cap, NPO, 0603, 5%
220pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
3u3F SMD, Electrolytic cap, A body, 10%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
220pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, X7R, 1206
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
3u3F SMD, Electrolytic cap, A body, 10%
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
12pF Cer. Cap, NPO, 0603, 5%
12pF Cer. Cap, NPO, 0603, 5%
12pF Cer. Cap, NPO, 0603, 5%
15pF Cer. Cap, NPO, 0603, 5%
10nF Cer. Cap, X7R, 0603, 10%
15pF Cer. Cap, NPO, 0603, 5%
5p6F Cer. Cap, NPO, 0603, 5%
3p3F Cer. Cap, NPO, 0603, 5%
12pF Cer. Cap, NPO, 0603, 5%
12pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
4p7F Cer. Cap, NPO, 0603, 5%
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
12pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
15pF Cer. Cap, NPO, 0603, 5%
33pF Cer. Cap, NPO, 0603, 5%
12pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
22pF Cer. Cap, NPO, 0603, 5%
12pF Cer. Cap, NPO, 0603, 5%
47pF Cer. Cap, NPO, 0603, 5%
47pF Cer. Cap, NPO, 0603, 5%
22pF Cer. Cap, NPO, 0603, 5%
15uF SMD, low ESR Electrolytic cap, C body
22pF Cer. Cap, NPO, 0603, 5%
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
6p8F Cer. Cap, NPO, 0603, 5%
68pF Cer. Cap, NPO, 0603, 5%
10pF Cer. Cap, NPO, 0603, 5%
35
46/63Y1/100N
46/63X1/010N
46/63Y1/100N
46/63X1/010N
46/63X1/010N
46/63Y1/100N
46/63N1/220P
46/63N1/220P
46/63Y1/100N
46/63N1/220P
46/63N1/220P
46/63N1/220P
46/63Y1/100N
46/63X1/010N
42/STA1/03U3
46/63Y1/100N
46/63X1/010N
46/63Y1/100N
46/63N1/220P
46/63Y1/100N
45/X7R1/1U16
46/63X1/010N
46/63Y1/100N
46/63Y1/100N
42/STA1/03U3
46/63X1/010N
46/63Y1/100N
46/63N1/012P
46/63N1/012P
46/63N1/012P
46/63N1/015P
46/63X1/010N
46/63N1/015P
46/63N1/05P6
46/63N1/03P3
46/63N1/012P
46/63N1/012P
46/63Y1/100N
46/63X1/010N
46/63X1/010N
46/63X1/010N
46/63N1/04P7
46/63X1/010N
46/63X1/010N
46/63N1/012P
46/63Y1/100N
46/63X1/010N
46/63X1/010N
46/63X1/010N
46/63X1/010N
46/63N1/015P
46/63N1/033P
46/63N1/012P
46/63Y1/100N
46/63Y1/100N
46/63N1/022P
46/63N1/012P
46/63N1/047P
46/63N1/047P
46/63N1/022P
41/SELC/015U
46/63N1/022P
46/63X1/010N
46/63X1/010N
46/63N1/06P8
46/63N1/068P
46/63N1/010P
C767
C768
C769
C770
C771
C772
C773
C775
C776
C801
C802
C803
C804
C805
C806
C807
C810
C811
C820
C821
C822
C823
C824
C825
C826
C827
C828
C829
C830
C901
C902
C903
C904
C915
C920
C923
C924
C925
C926
C927
C928
C929
C930
C931
C932
C933
C934
C935
C936
C937
C938
C939
C940
C941
C942
C943
C944
C945
D102
D103
D104
D200
D202
D203
D300
D301
D302
12pF Cer. Cap, NPO, 0603, 5%
15pF Cer. Cap, NPO, 0603, 5%
68pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
Ceramic Capacitor, 16V, 1uF, Y5V
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF Cer. Cap, X7R, 1206, 10%
1n2F Cer. Cap, X7R, 0603, 10%
1nF Cer. Cap, NPO, 0603, 5%
68pF Cer. Cap, NPO, 0603, 5%
470pF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
10nF Cer. Cap, X7R, 0603, 10%
100nF Cer. Cap, X7R, 1206, 10%
100uF Electrolytic Capacitor, 35V
470pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
10nF Cer. Cap, X7R, 0603, 10%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
220pF Cer. Cap, NPO, 0603, 5%
3u3F SMD, Electrolytic cap, A body, 10%
10 uF Electrolytic capacitor
150pF Cer. Cap, NPO, 0603, 5%
100nF, 25V, Y5V, decoupler, 0603
68pF Cer. Cap, NPO, 0603, 5%
100uF SMD, low ESR Electrolytic cap, D body
470uF Electrolytic Capacitor, Low ESR, 35V
33uF SMD, low ESR Electrolytic cap, C body
3u3F SMD, Electrolytic cap, A body, 10%
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
100nF, 25V, Y5V, decoupler, 0603
470uF Electrolytic Capacitor, Low ESR, 35V
33uF SMD, low ESR Electrolytic cap, C body
100uF SMD, low ESR Electrolytic cap, D body
100uF SMD, low ESR Electrolytic cap, D body
100uF SMD, low ESR Electrolytic cap, D body
33uF SMD, low ESR Electrolytic cap, C body
33uF SMD, low ESR Electrolytic cap, C body
33uF SMD, low ESR Electrolytic cap, C body
33uF SMD, low ESR Electrolytic cap, C body
33uF SMD, low ESR Electrolytic cap, C body
33uF SMD, low ESR Electrolytic cap, C body
Radially mounted LED
Radially mounted LED
Radially mounted LED
Dual Series Diode
Gen. Purpose 1N4004 diode in SMD pkg
Zener Diode
Bi-directional Transil
Bidirectional Transil
Bidirectional Transil
36
46/63N1/012P
46/63N1/015P
46/63N1/068P
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
45/Y5X7/1U16
46/63Y1/100N
46/63Y1/100N
46/3310/100N
46/63X1/01N2
46/63N1/01N0
46/63N1/068P
46/63X1/470P
46/63X1/010N
46/63X1/010N
46/3310/100N
41/2001/100U
46/63N1/470P
46/63Y1/100N
46/63X1/010N
46/63Y1/100N
46/63Y1/100N
46/63N1/220P
42/STA1/03U3
41/2001/010U
46/63N1/150P
46/63Y1/100N
46/63N1/068P
41/SELD/100U
41/200L/470U
41/SELC/033U
42/STA1/03U3
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
46/63Y1/100N
41/200L/470U
41/SELC/033U
41/SELD/100U
41/SELD/100U
41/SELD/100U
41/SELC/033U
41/SELC/033U
41/SELC/033U
41/SELC/033U
41/SELC/033U
41/SELC/033U
21/1010/LEDR
21/1010/LEDY
21/1010/LEDG
21/3010/AV99
24/SMA1/4004
21/1040/C3V3
24/TRSL/012V
24/TRSL/012V
24/TRSL/012V
D303
D304
D305
D306
D307
D400
D401
D402
D403
D500
D501
D502
D503
D600
D601
D700
D701
D703
D704
D800
D906
D907
D908
D909
D910
D911
F300
F301
F302
J1
JP12
JP2
JP3
JP4
L100
L101
L102
L104
L200
L202
L203
L204
L205
L500
L600
L700
L701
L702
L703
L704
L705
L706
L708
L709
L710
L711
L712
L713
L714
L715
L716
L717
L719
L720
L721
L722
L723
Dual Series Diode
Dual Series Diode
Dual Series Diode
Gen. Purpose 1N4004 diode in SMD pkg
Dual Schottky, Comm. Cathode, Diode
Dual Series Diode
Dual Series Diode
Dual Series Diode
Dual Series Diode
Dual Series Diode
Dual Series Diode
Dual Series Diode
Dual Series Diode
Varactor
Varactor
Schottky diode
Varactor
Schottky diode
Varactor
Dual Schottky, Comm. Cathode, Diode
Power Fast Schottky diode
Power Fast Schottky diode
Power Fast Schottky diode
Power Fast Schottky diode
Gen. Purpose 1N4004 diode in SMD pkg
4.096V Reference Diode
SMD (1206 pkg), 125mA fuse
SMD (1206 pkg), 125mA fuse
SMD (1206 pkg), 125mA fuse
BNC Connector
4 Pin SIL Header
14 Pin SIL Header
10 pin DIL Header
10 pin DIL Header
Ferrite, 1206 pkg, 120 ohm, 3A
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
220uH Choke
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
27nH Inductor
33nH Inductor
27nH Inductor
27nH Inductor
47nH Inductor
27nH Inductor
330nH Inductor
330nH Inductor
330nH Inductor
330nH Inductor
330nH Inductor
220nH Inductor
1206 47R resistor
330nH Inductor
330nH Inductor
Inductor - Air Core, 12.5nH
100nH Inductor
Inductor - Air Core, 18.5nH
24nH Inductor
24nH Inductor
24nH Inductor
330nH Inductor
37
21/3010/AV99
21/3010/AV99
21/3010/AV99
24/SMA1/4004
24/3BAT/54C1
21/3010/AV99
21/3010/AV99
21/3010/AV99
21/3010/AV99
21/3010/AV99
21/3010/AV99
21/3010/AV99
21/3010/AV99
21/3060/V109
21/3060/V109
21/3030/0017
21/3060/V109
21/3030/0017
21/3060/V109
24/3BAT/54C1
24/BRM1/40T3
24/BRM1/40T3
24/BRM1/40T3
24/BRM1/40T3
24/SMA1/4004
29/VREF/0001
39/1206/A125
39/1206/A125
39/1206/A125
35/5BNC/RA01
35/2501/0004
35/2501/0014
35/7026/0010
35/7026/0010
37/P034/0001
37/P033/0001
37/P033/0001
37/P033/0001
37/3320/P103
37/P033/0001
37/P033/0001
37/P033/0001
37/P033/0001
37/P033/0001
37/P033/0001
37/8551/027N
37/8551/033N
37/8551/027N
37/8551/027N
37/8551/047N
37/8551/027N
37/3320/330N
37/3320/330N
37/3320/330N
37/3320/330N
37/3320/330N
37/8551/220N
51/3380/047R
37/3320/330N
37/3320/330N
37/AC51/12N5
37/8551/100N
37/AC51/18N5
37/6351/024N
37/6351/024N
37/6351/024N
37/3320/330N
L724
L725
L726
L800
L801
L803
L804
L807
L808
L809
L810
L811
L812
L813
L901
L902
L903
L904
L905
L906
L907
L908
L909
LC700
LC701
LC702
M1
M1C
M2
MX700
P1
P3
Q200
Q201
Q202
Q203
Q204
Q205
Q206
Q300
Q301
Q302
Q400
Q401
Q500
Q501
Q600
Q700
Q701
Q702
Q703
Q704
Q705
Q706
Q707
Q801
Q804
Q805
R100
R101
R102
R103
R104
R105
R201
R202
R203
330nH Inductor
3u3H Choke
33nH Inductor
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 600 ohm, 200mA
Inductor - Air Core, 538nH
Inductor - Air Core, 538nH
220uH Choke
3u3H Choke
180nH Inductor
1uH Choke
3u3H Choke
150nH Inductor
150nH Inductor
Ferrite, 1206 pkg, 600 ohm, 200mA
SMD High Current, Shielded, 330uH Choke
SMD High Current, Shielded, 470uH Choke
SMD High Current, Shielded, 330uH Choke
Ferrite, 1206 pkg, 600 ohm, 200mA
Ferrite, 1206 pkg, 120 ohm, 3A
Ferrite, 1206 pkg, 120 ohm, 3A
Ferrite, 1206 pkg, 120 ohm, 3A
Ferrite, 1206 pkg, 120 ohm, 3A
70MHz SMD Filter, 0805 pkg
70MHz SMD Filter, 0805 pkg
70MHz SMD Filter, 0805 pkg
Tinned BeCu, used as RF screen.
RF Screen Cover (Small)
Conductive Foam Inserts
+7dBm0 Mixer, Surface Mount
DB9 Female with filtered pins
DB25 Female with filtered pins
Gen. Purpose NPN transistor in SOT-23
N channel, Enhancement Mode MOSFET
N Channel Junction FET(low Freq)
NPN Switching transistor in SOT-23
NPN Switching transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose NPN transistor in SOT-23
N channel, Enhancement Mode MOSFET
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
Gen. Purpose NPN transistor in SOT-23
Gen. Purpose PNP transistor in SOT-23
N channel, Enhancement Mode MOSFET
Gen. Purpose NPN transistor in SOT-23
N channel, Enhancement Mode MOSFET
N Channel Junction FET(UHF)
N Channel Junction FET(UHF)
N channel, Enhancement Mode MOSFET
Gen. Purpose NPN transistor in SOT-23
SOD-89A RF Transistor(1W)
SOD-89A RF Transistor(1W)
SOD-89A RF Transistor(1W)
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
1206 180R resistor
1206 270R resistor
0805, 1%, 4K7 resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
38
37/3320/330N
37/3320/P101
37/8551/082N
37/P033/0001
37/P033/0001
37/AC52/558N
37/AC52/558N
37/3320/P103
37/3320/P101
37/8551/180N
37/3320/P200
37/3320/P101
37/3320/150N
37/3320/150N
37/P033/0001
37/MSP1/330U
37/MSP1/470U
37/MSP1/330U
37/P033/0001
37/P034/0001
37/P034/0001
37/P034/0001
37/P034/0001
37/85LC/0135
37/85LC/0135
37/85LC/0135
94/BECU/24XH
80/9209/0001
83/0001/0000
37/MIXR/P028
35/5012/009F
35/5012/025F
27/3020/3904
27/30B5/5138
27/3020/5484
27/3020/2369
27/3020/2369
27/3010/3906
27/3020/3904
27/30B5/5138
27/3010/3906
27/3010/3906
27/3010/3906
27/3010/3906
27/3010/3906
27/3010/3906
27/3020/3904
27/3010/3906
27/30B5/5138
27/3020/3904
27/30B5/5138
27/3030/J309
27/3030/J309
27/30B5/5138
27/3020/3904
27/300B/FQ17
27/300B/FQ17
27/300B/FQ17
51/8511/04K7
51/8511/04K7
51/8511/04K7
51/3380/0180
51/3380/0270
51/8511/04K7
51/8511/010K
51/8511/010K
51/8511/010K
R204
R205
R206
R207
R208
R209
R210
R211
R212
R213
R214
R215
R216
R217
R218
R219
R220
R221
R222
R223
R224
R225
R226
R227
R228
R229
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R240
R241
R242
R243
R244
R245
R300
R301
R302
R303
R304
R305
R306
R307
R308
R309
R310
R311
R312
R313
R314
R315
R316
R317
R318
R319
R320
R321
R322
R323
R324
0805, 1%, 10K resistor
0805, 1%, 2K2 resistor
0805, 1%, 2K2 resistor
0805, 1%, 68K resistor
0805, 1%, 22K resistor
0805, 1%, 330R resistor
0805, 1%, 10K resistor
0805, 1%, 220R resistor
0805, 1%, 220R resistor
0805, 1%, 1M resistor
1206 180R resistor
0805, 1%, 120R resistor
0805, 1%, 1K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 560R resistor
0805, 1%, 1K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
1206 180R resistor
0805, 1%, 56R resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 120R resistor
0805, 1%, 120R resistor
0805, 1%, 560R resistor
0805, 1%, 22K resistor
0805, 1%, 1K resistor
0805, 1%, 4K7 resistor
0805, 1%, 22K resistor
0805, 1%, 47K resistor
0805, 1%, 1K resistor
0805, 1%, 1K resistor
0805, 1%, 10K resistor
0805, 1%, 47R resistor
0805, 1%, 47K resistor
0805, 1%, 220R resistor
0805, 1%, 10R resistor
0805, 1%, 10K resistor
0805, 1%, 27R resistor
0805, 1%, 27R resistor
0805, 1%, 27R resistor
0805, 1%, 27R resistor
0805, 1%, 330R resistor
0805, 1%, 330R resistor
0805, 1%, 10R resistor
0805, 1%, 4K7 resistor
0805, 1%, 2K2 resistor
0805, 1%, 560R resistor
0805, 1%, 560R resistor
0805, 1%, 22K resistor
0805, 1%, 22K resistor
0805, 1%, 22K resistor
0805, 1%, 1K resistor
0805, 1%, 22K resistor
0805, 1%, 1K resistor
0805, 1%, 1K resistor
0805, 1%, 120K resistor
0805, 1%, 120K resistor
0805, 1%, 120K resistor
0805, 1%, 68K resistor
0805, 1%, 68K resistor
0805, 1%, 68K resistor
0805, 1%, 1K resistor
39
51/8511/010K
51/8511/02K2
51/8511/02K2
51/8511/068K
51/8511/022K
51/8511/330R
51/8511/010K
51/8511/220R
51/8511/220R
51/8511/01M0
51/3380/0180
51/8511/120R
51/8511/01K0
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/560R
51/8511/01K0
51/8511/010K
51/8511/010K
51/8511/010K
51/3380/0180
51/8511/056R
51/8511/010K
51/8511/010K
51/8511/120R
51/8511/120R
51/8511/560R
51/8511/022K
51/8511/01K0
51/8511/04K7
51/8511/022K
51/8511/047K
51/8511/01K0
51/8511/01K0
51/8511/010K
51/8511/047R
51/8511/047K
51/8511/220R
51/8511/010R
51/8511/010K
51/8511/027R
51/8511/027R
51/8511/027R
51/8511/027R
51/8511/330R
51/8511/330R
51/8511/010R
51/8511/04K7
51/8511/02K2
51/8511/560R
51/8511/560R
51/8511/022K
51/8511/022K
51/8511/022K
51/8511/010K
51/8511/022K
51/8511/010K
51/8511/01K0
51/8511/120K
51/8511/120K
51/8511/120K
51/8511/068K
51/8511/068K
51/8511/068K
51/8511/01K0
R325
R326
R327
R328
R329
R330
R331
R332
R333
R335
R336
R337
R400
R401
R402
R403
R404
R405
R406
R407
R408
R409
R410
R411
R412
R413
R414
R415
R416
R417
R418
R419
R420
R421
R422
R423
R424
R425
R426
R427
R428
R429
R430
R433
R434
R435
R436
R437
R438
R439
R440
R442
R443
R444
R445
R446
R447
R448
R449
R450
R451
R453
R454
R455
R456
R457
R458
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 68K resistor
0805, 1%, 1K resistor
0805, 1%, 22K resistor
0805, 1%, 22K resistor
0805, 1%, 1K8 resistor
0805, 1%, 330R resistor
0805, 1%, 270R resistor
0805, 1%, 22K resistor
0805, 1%, 22K resistor
0805, 1%, 12K resistor
0805, 1%, 5K6 resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 5K6 resistor
0805, 1%, 56K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 10K resistor
0805, 1%, 1K resistor
0805, 1%, 560R resistor
0805, 1%, 560R resistor
0805, 1%, 560R resistor
0805, 1%, 560R resistor
0805, 1%, 2K2 resistor
0805, 1%, 22K resistor
0805, 1%, 120K resistor
0805, 1%, 22K resistor
0805, 1%, 120K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 22K resistor
0805, 1%, 22K resistor
0805, 1%, 47K resistor
0805, 1%, 22K resistor
0805, 1%, 22K resistor
0805, 1%, 47K resistor
0805, 1%, 270K resistor
0805, 1%, 4K7 resistor
0805, 1%, 1K resistor
0805, 1%, 4K7 resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
0805, 1%, 47K resistor
0805, 1%, 100K resistor
0805, 1%, 47K resistor
0805, 1%, 270K resistor
0805, 1%, 220R resistor
0805, 1%, 56K resistor
0805, 1%, 47K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 47K resistor
0805, 1%, 22K resistor
0805, 1%, 4K7 resistor
40
51/8511/047K
51/8511/047K
51/8511/047K
51/8511/010K
51/8511/010K
51/8511/047K
51/8511/047K
51/8511/068K
51/8511/01K0
51/8511/022K
51/8511/022K
51/8511/01K8
51/8511/330R
51/8511/270R
51/8511/022K
51/8511/022K
51/8511/012K
51/8511/05K6
51/8511/010K
51/8511/010K
51/8511/05K6
51/8511/056K
51/8511/047K
51/8511/047K
51/8511/010K
51/8511/01K0
51/8511/560R
51/8511/560R
51/8511/560R
51/8511/560R
51/8511/02K2
51/8511/022K
51/8511/120K
51/8511/022K
51/8511/120K
51/8511/010K
51/8511/010K
51/8511/022K
51/8511/022K
51/8511/047K
51/8511/022K
51/8511/022K
51/8511/047K
51/8511/270K
51/8511/04K7
51/8511/01K0
51/8511/04K7
51/8511/047K
51/8511/047K
51/8511/04K7
51/8511/04K7
51/8511/04K7
51/8511/04K7
51/8511/04K7
51/8511/047K
51/8511/100K
51/8511/047K
51/8511/270K
51/8511/220R
51/8511/56K
51/8511/047K
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/047K
51/8511/022K
51/8511/04K7
R459
R460
R461
R462
R463
R464
R465
R466
R467
R500
R501
R502
R503
R504
R505
R506
R507
R508
R509
R510
R511
R512
R513
R514
R515
R516
R517
R518
R519
R520
R521
R522
R523
R525
R526
R527
R528
R529
R530
R531
R532
R533
R534
R535
R536
R537
R602
R603
R604
R605
R606
R607
R608
R609
R610
R611
R612
R613
R614
R615
R616
R617
R618
R620
R622
R623
R624
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
0805, 1%, 56K resistor
0805, 1%, 22K resistor
0805, 1%, 56K resistor
0805, 1%, 270K resistor
0805, 1%, 22K resistor
0805, 1%, 2K2 resistor
0805, 1%, 4K7 resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 22K resistor
0805, 1%,1K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 1M resistor
0805, 0.5%, 50ppm,15K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 15K resistor
0805, 1%, 330K resistor
0805, 1%, 680R resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 270K resistor
0805, 1%, 1K resistor
0805, 1%, 10K resistor
0805, 1%, 2K2 resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 0.5%, 50ppm,15K resistor
0805, 1%, 5K6 resistor
0805, 1%, 100K resistor
0805, 1%, 10K resistor
0805, 1%, 100K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 15K resistor
0805, 1%, 5K6 resistor
0805, 1%, 5K6 resistor
0805, 1%, 2K2 resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%, 47R resistor
0805, 1%, 47R resistor
0805, 1%, 47R resistor
0805, 1%, 47R resistor
0805, 1%, 1K resistor
0805, 1%, 1K resistor
0805, 1%, 1K2 resistor
0805, 1%, 5K6 resistor
0805, 1%, 5K6 resistor
0805, 1%, 22K resistor
41
51/8511/04K7
51/8511/04K7
51/8511/056K
51/8511/022K
51/8511/056K
51/8511/270K
51/8511/022K
51/8511/02K2
51/8511/04K7
51/8511/047K
51/8511/047K
51/8511/047K
51/8511/022K
51/8511/01K0
51/8511/010K
51/8511/010K
51/8511/01M0
51/85P1/015K
51/85P1/015K
51/85P1/015K
51/85P1/015K
51/8511/010K
51/8511/010K
51/8511/015K
51/8511/330K
51/8511/680R
51/8511/047K
51/8511/047K
51/8511/047K
51/8511/047K
51/8511/047K
51/8511/270K
51/8511/01K0
51/8511/010K
51/8511/02K2
51/8511/047K
51/8511/047K
51/8511/047K
51/85P1/015K
51/85P1/015K
51/85P1/015K
51/85P1/015K
51/8511/05K6
51/8511/100K
51/8511/10K
51/8511/100K
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/015K
51/8511/05K6
51/8511/05K6
51/8511/02K2
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/047R
51/8511/047R
51/8511/047R
51/8511/047R
51/8511/01K0
51/8511/01K0
51/8511/1K2
51/8511/05K6
51/8511/05K6
51/8511/022K
R625
R626
R627
R628
R629
R630
R631
R632
R633
R634
R635
R636
R637
R638
R639
R640
R646
R647
R648
R649
R650
R700
R701
R702
R703
R704
R705
R706
R707
R708
R709
R710
R711
R712
R713
R714
R715
R716
R717
R718
R719
R720
R721
R722
R723
R724
R725
R726
R727
R729
R730
R731
R732
R733
R734
R735
R736
R737
R738
R739
R740
R741
R742
R743
R745
R801
R802
0805, 1%, 22K resistor
0805, 1%, 2K2 resistor
1218, 5%, 150R, 1W, SMD resistor
1218, 5%, 150R, 1W, SMD resistor
0805, 1%, 270K resistor
1206, 1%, 120R resistor
0805, 1%, 47R resistor
0805, 1%, 47R resistor
1218, 5%, 150R, 1W, SMD resistor
1206, 1%, 120R resistor
0805, 1%, 560R resistor
0805, 1%, 220R resistor
0805, 1%, 5K6 resistor
0805, 1%, 5K6 resistor
0805, 1%, 10K resistor
1218, 5%, 150R, 1W, SMD resistor
0805, 1%, 4K7 resistor
0805, 1%, 10K resistor
0805, 1%, 4K7 resistor
0805, 1%, 10K resistor
0805, 1%, 5K6 resistor
0805, 1%, 120R resistor
0805, 1%, 100R resistor
0805, 1%, 100R resistor
0805, 1%, 100R resistor
0805, 1%, 100R resistor
0805, 1%, 100R resistor
0805, 1%, 220R resistor
0805, 1%, 100R resistor
0805, 1%, 4K7 resistor
0805, 1%, 10K resistor
0805, 1%, 2K2 resistor
0805, 1%, 10R resistor
0805, 1%, 56R resistor
0805, 1%, 10K resistor
0805, 1%, 56R resistor
0805, 1%, 10K resistor
0805, 1%, 47R resistor
0805, 1%, 10K resistor
0805, 1%, 100R resistor
0805, 1%, 10K resistor
0805, 1%, 100K resistor
0805, 1%, 330R resistor
0805, 1%, 22K resistor
0805, 1%, 10K resistor
0805, 1%, 56R resistor
0805, 1%, 5K6 resistor
0805, 1%, 47R resistor
0805, 1%, 22K resistor
0805, 1%, 10R resistor
0805, 1%, 100R resistor
0805, 1%, 560R resistor
0805, 1%, 22K resistor
0805, 1%, 1K resistor
0805, 1%, 4K7 resistor
0805, 1%, 22K resistor
0805, 1%, 56R resistor
0805, 1%, 330R resistor
0805, 1%, 100R resistor
0805, 1%, 10K resistor
0805, 1%, 100R resistor
0805, 1%, 1K resistor
0805, 1%, 220R resistor
0805, 1%, 560R resistor
0805, 1%, 330R resistor
0805, 1%, 12K resistor
0805, 1%, 100R resistor
42
51/8511/022K
51/8511/02K2
51/2851/0150
51/2851/0150
51/8511/270K
51/3380/120R
51/8511/047R
51/8511/047R
51/2851/0150
51/3380/120R
51/8511/560R
51/8511/220R
51/8511/05K6
51/8511/05K6
51/8511/010K
51/2851/0150
51/8511/04K7
51/8511/010K
51/8511/04K7
51/8511/010K
51/8511/05K6
51/8511/120R
51/8511/047R
51/8511/120R
51/8511/120R
51/8511/120R
51/8511/220R
51/8511/220R
51/8511/220R
51/8511/04K7
51/8511/010K
51/8511/02K2
51/8511/010R
51/8511/056R
51/8511/010K
51/8511/056R
51/8511/010K
51/8511/047R
51/8511/010K
51/8511/120R
51/8511/010K
51/8511/100K
51/8511/330R
51/8511/022K
51/8511/010K
51/8511/056R
51/8511/05K6
51/8511/047R
51/8511/022K
51/8511/010R
51/8511/100R
51/8511/560R
51/8511/022K
51/8511/01K0
51/8511/04K7
51/8511/022K
51/8511/056R
51/8511/330R
51/8511/100R
51/8511/010K
51/8511/100R
51/8511/01K0
51/8511/220R
51/8511/560R
51/8511/330R
51/8511/012K
51/8511/100R
R803
R804
R805
R806
R808
R809
R810
R811
R812
R813
R814
R815
R816
R819
R823
R918
R919
R920
R921
R922
R923
R924
R925
R926
R927
R928
R929
R930
R931
R932
R933
R934
R935
R936
RL300
RV100
S200
SW1
T300
T301
U201
U202
U203
U204
U205
U207
U208
U212
U300
U301
U302
U303
U400
U401
U402
U403
U404
U405
U406
U407
U500
U502
U503
U600
U601
U602
U603
1218, 5%, 150R, 1W, SMD resistor
1206 10R resistor
1206 10R resistor
1218, 5%, 150R, 1W, SMD resistor
0805, 1%, 10R resistor
0805, 1%, 27R resistor
0805, 1%, 10R resistor
0805, 1%, 27R resistor
0805, 1%, 100R resistor
1218, 5%, 150R, 1W, SMD resistor
0805, 1%, 10R resistor
0805, 1%, 1K resistor
0805, 1%, 10K resistor
7W Axial 68R resistor
0805, 1%, 4K7 resistor
0805, 1%, 47K resistor
0805, 1%, 47K resistor
0805, 1%, 1K resistor
0805, 1%, 560R resistor
0805, 1%, 220R resistor
0805, 1%, 1K resistor
0805, 1%, 680R resistor
0805, 1%, 220R resistor
0805, 1%, 2K2 resistor
0805, 1%, 220R resistor
0805, 1%, 220R resistor
0805, 1%, 220R resistor
0805, 1%, 220R resistor
0805, 1%, 220R resistor
0805, 1%, 220R resistor
0805, 1%, 560R resistor
0805, 1%, 560R resistor
0805, 1%, 120R resistor
0805, 1%, 120R resistor
12V Telecommunications DPDT Relay
100K, 11 turn, linear Pot.
4mm SMD PB switch
Omron-6x6-RA switch
High Isolation Audio Transformer
High Isolation Audio Transformer
Quad CMOS RS232 Driver SMD (SO-14)
Quad CMOS RS232 Driver SMD (SO-14)
Under-voltage sensor and Reset Generator
Motorola Embedded 8/16 bit microcontroller
One of 8 Selector
4 Megabyte TSOP (Std.) 5V (only) Flash
1,2,4 Megabit RAM in SOP package
Hi Speed, TTL compatible, opto-isolator
Opto-isolator with Darlington Output
Quad SPST Analog Switch - low Rds On
Low Power Quad Operational Amplifier
32 position digital pot.
Low Power Quad Operational Amplifier
8-bit Shift reg. with output latch
Transconductance Amplifier
Quad SPST Analog Switch - low Rds On
Quad SPST Analog Switch - low Rds On
Low Power Quad Operational Amplifier
Voltage Output, Quad 8 bit DAC
Low Power Quad Operational Amplifier
CTCSS and DCS encoder/decoder
Low Power Quad Operational Amplifier
32 position digital pot.
Gen. Purp. R2R Op. Amp.
Voltage Output, Quad 8 bit DAC
Dual PLL
Temperature Sensor
43
51/2851/0150
51/3380/0010
51/3380/0010
51/2851/0150
51/8511/010R
51/8511/027R
51/8511/010R
51/8511/027R
51/8511/100R
51/2851/0150
51/8511/010R
51/8511/01K0
51/8511/010K
55/5W51/068R
51/8511/04K7
51/8511/047K
51/8511/047K
51/8511/01K0
51/8511/560R
51/8511/220R
51/8511/01K0
51/8511/680R
51/8511/220R
51/8511/02K2
51/8511/220R
51/8511/220R
51/8511/220R
51/8511/220R
51/8511/220R
51/8511/220R
51/8511/560R
51/8511/560R
51/8511/120R
51/8511/120R
96/2000/012V
53/THH1/100K
31/SMPB/0001
31/0005/E121
37/2040/5065
37/2040/5065
29/14C8/9A01
29/14C8/8001
29/MC33/064D
29/68HC/12A0
29/2030/C138
29/P006/0001
29/SRAM/P013
26/N137/0001
25/1010/4N33
29/00DG/411C
29/000L/M224
29/MAX5/161L
29/000L/M224
29/2030/C595
29/0LM1/3700
29/00DG/411C
29/00DG/411C
29/000L/M224
29/00MA/X534
29/000L/M224
29/00FX/805L
29/000L/M224
29/MAX5/161L
29/1M55/P021
29/00MA/X534
29/LMX2/335L
29/0001/LM61
U604
Dual PLL
U605
Dual, Ripple Carry, 4 bit binary counter
U606
Dual 4 bit, ripple carry, decade counters
U607
Gen. Purp. R2R Op. Amp.
U608
Gen. Purp. R2R Op. Amp.
U700
MMIC Amplifier
U701
MMIC Amplifier
U702
MMIC Amplifier
U703
MMIC Amplifier
U704
Transconductance Amplifier
U705
MMIC Amplifier
U706
MMIC Amplifier
U707
Gen. Purp. R2R Op. Amp.
U800
MMIC Amplifier
U906
Gen. Purp. R2R Op. Amp.
U907
Simple (Buck) Switcher, 5V, 1A output
U908
Simple (Buck) Switcher, 5V, 1A output
U909
Simple (Buck) Switcher, 5V, 1A output
U910
LDO Adjustable Positive Voltage Regulator
U911 Positive Adjustable Voltage Reg. in SO8 package
U912 Positive Adjustable Voltage Reg. in SO8 package
U913
Negative Adjustable Voltage Reg. in SO8
U914
Negative Adjustable Voltage Reg. in SO8
U915
Negative Adjustable Voltage Reg. in SO8
X200
14.7456 MHz Crystal, 30ppm, SMD
X500
4.0 MHz Crystal
X600
12.0 MHz Crystal, 5ppm, SMD
X601
12.0 MHz Crystal, 5ppm, SMD
44
29/LMX2/335L
29/2030/C393
29/2030/C390
29/1M55/P021
29/1M55/P021
24/3010/VAM6
24/3010/211L
24/3010/211L
24/3010/211L
29/0LM1/3700
24/3010/211L
24/3010/211L
29/1M55/P021
24/3010/211L
29/1M55/P021
29/REG1/0N12
29/REG1/0N12
29/REG2/00N5
29/00LM/1117
29/000L/M317
29/000L/M317
29/000L/M337
29/000L/M337
29/000L/M337
33/14M7/0001
32/2049/04M0
33/12M0/0001
33/12M0/0001
C T50 Parts List (Rev 3)
The following table highlights those components in Rev. 3 exciters, that differ from the
parts in Rev. 4. The values indicated are the values used in Rev.3
Ref
Descr iption
Par t #
C212
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C420
NF
C421
NF
C502
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C512
NF
C513 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16
C611
10nF Cer. Cap, X7R, 0603, 10%
46/63X1/010N
C612
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C622
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C645
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C646
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C719
100nF, 25V, Y5V, decoupler, 0603
46/63Y1/100N
C726
3p9F Cer. Cap, NPO, 0603, 5%
46/63N1/03P9
C727
15pF Cer. Cap, NPO, 0603, 5%
46/63N1/015P
C728
15pF Cer. Cap, NPO, 0603, 5%
46/63N1/015P
C729
1p8F Cer. Cap, NPO, 0603, 5%
46/63N1/01P8
C731
NF
C734
3p9F Cer. Cap, NPO, 0603, 5%
46/63N1/03P9
C735
2p2F Cer. Cap, NPO, 0603, 5%
46/63N1/02P2
C744
NF
C752
NF
C755
47pF Cer. Cap, NPO, 0603, 5%
46/63N1/047P
C756
4p7F Cer. Cap, NPO, 0603, 5%
46/63N1/04P7
C757
120pF Cer. Cap, NPO, 0603, 5%
46/63N1/120P
C758
120pF Cer. Cap, NPO, 0603, 5%
46/63N1/120P
C759
47pF Cer. Cap, NPO, 0603, 5%
46/63N1/047P
C760
NF
C765
47pF Cer. Cap, NPO, 0603, 5%
46/63N1/047P
C766
NF
C767
NF
C768
NF
C769
NF
C804
18pF Cer. Cap, NPO, 0603, 5%
46/63N1/018P
C808
1p8F Cer. Cap, NPO, 0603, 5%
46/63N1/01P8
C809
NF
C812
1p8F Cer. Cap, NPO, 0603, 5%
46/63N1/01P8
C813
100pF Cer. Cap, NPO, 0603, 5%
46/63N1/100P
C815
56pF Cer. Cap, NPO, 0603, 5%
46/63N1/056P
C816
33pF Cer. Cap, NPO, 0603, 5%
46/63N1/033P
C818
10pF Cer. Cap, NPO, 0603, 5%
46/63N1/010P
C819
68pF Cer. Cap, NPO, 0603, 5%
46/63N1/01P8
C828
47pF Cer. Cap, NPO, 0603, 5%
46/63N1/047P
C830
NF
D503
NF
J4
NF
JP4
NF
L701
39nH Inductor
37/8551/039N
L703
NF
L704
NF
L705
NF
L713
220uH Choke
37/3320/P103
L720
220nH Inductor
37/3320/220N
L721
270nH Inductor
37/3320/270N
L722
220nH Inductor
37/3320/220N
L726
82nH Inductor
37/8551/082N
L805
120nH, air core
37/AC52/120N
L806
169nH, air core
37/MAXI/169N
L812
270nH Inductor
37/3320/270N
L813
NF
LC700
NF
45
LC701
LC702
Q402
R313
R314
R315
R316
R332
R333
R337
R404
R446
R448
R451
R452
R464
R514
R515
R522
R534
R535
R536
R537
R600
R602
R603
R604
R605
R609
R610
R612
R617
R619
R620
R621
R626
R627
R628
R633
R634
R640
R701
R702
R703
R705
R711
R712
R713
R714
R721
R725
R733
R736
R737
R738
R740
R741
R742
R745
R801
R803
R806
R807
R813
R814
R815
NF
NF
Gen. Purpose PNP transistor in SOT-23
0805, 1%, 120K resistor
0805, 1%, 22K resistor
0805, 1%, 100K resistor
0805, 1%, 22K resistor
0805, 1%, 180K resistor
0805, 1%, 1K resistor
NF
0805, 1%, 10K resistor
0805, 1%, 10K resistor
0805, 1%,10K resistor
0805, 1%, 47K resistor
0805, 1%,10K resistor
0805, 1%, 330K resistor
0805, 1%, 22K resistor
NF
0805, 1%, 68K resistor
NF
NF
NF
NF
0805, 1%, 4K7 resistor
0805, 1%, 27K resistor
0805, 1%, 27K resistor
0805, 1%, 100K resistor
0805, 1%, 18K resistor
0805, 1%, 22K resistor
0805, 1%, 47K resistor
0805, 1%, 100K resistor
0805, 1%, 560R resistor
0805, 1%, 680R resistor
0805, 1%, 680R resistor
0805, 1%, 4K7 resistor
0805, 1%, 4K7 resistor
NF
1218, 5%, 68R, 1W, SMD resistor
1206, 1%, 120R resistor
1206, 1%, 120R resistor
NF
0805, 1%, 47R resistor
0805, 1%, 120R resistor
0805, 1%, 120R resistor
0805, 1%, 220R resistor
0805, 1%, 56R resistor
NF
0805, 1%, 100K resistor
0805, 1%, 120R resistor
NF
0805, 1%, 22K resistor
0805, 1%, 330R resistor
0805, 1%, 220R resistor
0805, 1%, 1K resistor
0805, 1%, 220R resistor
0805, 1%, 120R resistor
0805, 1%, 4K7 resistor
0805, 1%, 180R resistor
0805, 1%, 220R resistor
0805, 1%, 22K resistor
1218, 5%, 100R, 1W, SMD resistor
1218, 5%, 100R, 1W, SMD resistor
1218, 5%, 100R, 1W, SMD resistor
1218, 5%, 100R, 1W, SMD resistor
NF
NF
46
27/3010/3906
51/8511/120K
51/8511/022K
51/8511/100K
51/8511/022K
51/8511/180K
51/8511/01K0
51/8511/010K
51/8511/010K
51/8511/010K
51/8511/047K
51/8511/010K
51/8511/330K
51/8511/022K
51/8511/068K
51/8511/04K7
51/8511/027K
51/8511/027K
51/8511/100K
51/8511/018K
51/8511/022K
51/8511/047K
51/8511/100K
51/8511/560R
51/8511/680R
51/8511/680R
51/8511/04K7
51/8511/04K7
51/2851/0068
51/3380/120R
51/8511/120R
51/8511/047R
51/8511/120R
51/8511/120R
51/8511/220R
51/8511/056R
51/8511/100K
51/8511/120R
51/8511/022K
51/8511/330R
51/8511/220R
51/8511/01K0
51/8511/220R
51/8511/120R
51/8511/04K7
51/8511/180R
51/8511/220R
51/8511/022K
51/2851/0100
51/2851/0100
51/2851/0100
51/2851/0100
D EIA CTCSS TONES
Fr equency
No Tone
EIA Number
67.0
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
162.2
167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3
A1
B1
C1
A2
C2
B2
C3
A3
C4
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
47
GPS-
GPS+
External
Reference
Input
Line2-
Line2+
Line2-
Line2+
Tone-
Tone+
uP
uP
Summing
Amplifier
uP
uP
uP
Line 1
Deviation
Control
VCA
GPS
uP
uP
External Ref. Div.
uP
uP
VCA
Microphone input
High Speed Coupler
3200
Loop Detect
+12V
Loop/Volts
Select
T301
T300
Balanced Differential Line 2
Amplifier
Deviation
uP
Control
CTCSS
Generator
Pre-emphasis
Flat
Pre-emphasis
Flat
Pre-emphasis
Low Pass
Filter (250Hz)
uP
uP
uP
uP
uP
uP
Buffer
Limiter
uP
uP
Summing
Amplifier
VCO
VCO
Reference
Oscillator
Buffer
uP
Balance
Temp.
uP
uP
Lock Detect and
Reference Osc. Detect
uP
RF
Amplifier
RF
Amplifier
Varactor
Bias
uP
Low Pass
Filter (55MHz)
RF
Amplifier
uP
RF
Amplifier
A4
File:
Originator:
Sheet 1
of
1
Revision: A
D:\Protel Files\Copies from Crocodile\t50_4.ddb - Issue4\BLOCK_DIAGRAM.Sch
Rev. Release Date:
10:28:51
Number: 05/9
Print Date: 8-Apr-2003
Size:
Line Level In
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
RF Technology Pty Ltd
RF
Output
Line
Potentiometer
Vref
Voltage Controlled
Low Pass
RF
Filter (55MHz)
Amplifier
uP
uP
uP: Microprocessor Input or Output
VCO: Voltage Controlled Oscillator
VCA: Voltage Controlled Amplifier
PLL: Phase Locked Loop
Title Block Flow Diagram of Audio and RF signals in 9154(T50)
Low Pass
Filter (300MHz)
Low Pass
Filter (350MHz)
uP
Lock Detect and
Reference Osc. Detect
VCA
Passive
Mixer
Amplifier
6dB gain
Maximum Deviation
Line Level Sense
Setting
uP
Digital
Potentiometer
uP
Low Pass
Filter (3kHz)
Varactor
Bias
Temp. Sensor
Channel PLL
Centre Frequency
uP
Adjustment
Set Synthesiser
Dividers
RF
Amplifier
RF
Amplifier
Reference
Oscillator
Peak
Detector
Summing
Amplifier
Modulation PLL
Modulation
Limiter
Centre Frequency
Adjustment
Set Synthesiser
Dividers
uP
Amplifier
20dB gain
uP
Maximum Tone Deviation
Setting
and
Dir. Aud. (Tone IN) Deviation
Control
uP
Digital
Potentiometer
Buffer
A
B
C
1
DB25
J1
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
2
+5V
Vref
CH_EN
+12V
PTT_IN
T/R_RELAY
LINE2+
LINE2TONE+
TONELINEGPS+
GPSLINE+
+28V
GND
180R
R24
GND
D14
GND
180R
R25
180R
R23
GND
R26
3
MOSI
SCLK
PA_CS
CS2
Q1
BSS138
BZX84C5V6
D13
180R
BAV99
R22
180R
R21
180R
BAV99
5V_PROT
D12
5V_PROT
GND
BAV99
D11
5V_PROT
180R
47K
R1
D9
BAW56
47K
R2
4
15
2
9
7
1
C1
100nF
C
C
Q
Q
PL
R19
22R
I7
I6
I5
I4
I3
I2
I1
I0
SI
U1
6
5
4
3
14
13
12
11
10
74HC165
+5V
16
VCC
BAV99
5
100K
100K
100K
100K
100K
100K
100K
100K
6
ECO No.
R17
R15
R13
R11
R12
R18
R16
R14
47K
47K
47K
47K
47K
CH80
CH40
CH20
CH10
CH8
CH4
CH2
CH1
7
10
1
A3
File:
Originator:
Sheet 1
7
F:\Obsoleted Files\Old Files Backup\916x.ddb - T50_R50_rear_panel.Sch
Rev. Release Date:
09:56:54
Number: 05/9160 R7
Print Date: 16-Aug-2002
Size:
GND
Description of Change
5X2 Header
2
3
4
5
6
7
8
9
of
1
Revision: 1
Title Rear Panel Board for 9154 (T50) and 9155 (R50)
Rev No.
47K
47K
47K
R10
R9
R8
R7
R6
R5
R4
FIDUCIAL
FD2
FIDUCIAL
FD1
R3
5V_PROT
D1
BAV99
R20
D2
BAV99
GND
8
6
D3
BAV99
D10
5
D4
BAV99
5V_PROT
4
D5
BAV99
3
D6
BAV99
2
D7
BAV99
D
1
D8
BAV99
JUMPER
JUMPER
JUMPER
JUMPER
8
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
RF Technology Pty Ltd
LK4
LK3
LK2
LK1
8
A
B
C
D
1
2
3
4
5
6
7
8
FILTER_OFF
+5TONE
1uF
24
C509
18
D
R507
1M
22pF
C500
7
3
5
6
8
SCLK
MOSI
SCLK
MOSI
C502
TONE_INT
C513
9
TONE_OUT
CTCSS_OUT
RX_SUB_IN
RX_SUB_OUT
100nF
14
13
15
R514
1uF
10K
TP500
TONE+CTCSS
RX_IN+
RX_INRX_OUT
COMP+
COMPCOMP_OUT
10
2
DG411
11
AUDIO_OUT
2
U502A
1
WAKE
3
LM224
R518
R519
47K
47K
47K
C514
22nF (X7R - 10%)
C515
100nF
(NPO)
10
U502C
8
C516
9
LM224
1n2F (NPO)
GND
FX805
12
C
R517
R527
47K
R516
680R
23
3
22K
AUDIO_IN
100nF
U301A
R503
22
NO_TONE
20
19
21
C503
4
IRQ
CS
ADDR
SCLK
Din
Dout
16
17
C
VCC
XTAL/CLK
22pF
CTCSS_SEL
+5V
R512
10K
X500
4MHz
2
CTCSS_SEL
100nF
GND
GND
GND
XTAL
Vbias
1
D
BLM31A601
U500
C508
C501
+5V
L500
1
FILTER_OFF
GND
-10V
GND
GND
R528
47K
+10V
+10V
R522
68K
7K5
C507
100pF
-10V
R531
R509
7K5
7K5
D501
BAV99
6
TP501
TONE_IN
U502B
U301D
7
15
14
5
TONEP+
LM224
+10V
R533
7K5
R511
7K5
+5V
DG411
R502
47K
-10V
R504
GND
D502
TONE_OUT
D503
6
C511
100nF
560R
TONE_OUT
2K2
LM224
GND
+2.5V
5
4
MMBT3906
R505
BAV99
R525
U503
10K
2
R524
NF
INC
U/D
R529
47K
R534
NF
BAV99
GND
GND
B
1
-10V
GND
Q500
10K
MAX5161L
R520
47K
R513
10K
R526
13
GND
11
C506
100pF
R523
1K
+2.5V
GND
B
7K5
R532
-10V
3
GND R501
47K
7K5
16
7K5
100nF
VDD
U502E
LM224
TONEPR500
47K
12
14
R510
V+
BAV99
R508
C510
V-
R530
4
U502D
R530, R531, R508, R509, R532, R533, R510, AND R511
Should be 0.25%, 50ppm TC or better
D500
-2.5V
-10V
-2.5V
EXT_TONE_SEL
+2.5V
TONE_DEV_INC
R506
Q501
TONE_DEV_U/D
10K
MMBT3906
R521
47K
-2.5V
A
A
Rev No.
ECO No.
Description of Change
Title Tone Generation Section
Size:
A3
Number:
Print Date: 20-Feb-2002
Rev. Release Date:
File:
1
2
3
4
5
6
9154
23:41:52
Revision:
Sheet 5
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - tonetx.sch
7
8
2
3
4
+5Q
MOD_IN
MOD_IN
R605
R609
27K
10K
5
6
7
+5Q
R631
+5Q
47R
C630
C631
1uF
10nF
R616
47R
U600
4
+5Q
X600
10nF
7
C614
C615
33pF
10nF
R632
+5Q
C607
1uF
10nF
8p2F
C635
C637
8p2F
56pF
10nF
12M
7
GND
SCLK
MOSI
R610
47K
MOD_ADJ_FINE
2
10nF
LE
CLK
DATA
C622
C650
Vp1
5
8
FoLD
7
6
Vref
VCC
CLR
LDAC
9
10
11
CS
SCLK
Din
Dout
UPO
4
NF
3u3F
GND
R600
4K7
**
GND
Fo_CHAN
R646
CHAN_PLL_SENSE
C646
L718
220uH
CHAN_PLL_IN
C623
MOD_VCO_EN
*
220nF
MOD_VCO_EN
GND
CHAN_VCO_EN
+5Q
* C613 AND C623 CAN BE X7R(10%)
** C625 and C626 should be 10% Tantalums
Case Size A
U603
14
T/R_RELAY
Vo
+5V
MOD_PLL_IN
GND
B
LM61
GND
12
MAX534
3
L600
BLM31A601
T/R_RELAY
U400A
16
14
C644
2
R633
R634
120R
120R
EXT_REF_IN
100nF
GND
QA
1A QB
R QC
QD
3
4
5
6
R630
120R
100nF
GND
74HC390
GndVcc
U605C
10K
U606C
A
11
10
9
8
1
4
2
1A QA
1B QB
QC
R QD
3
5
6
7
15
12
14
Divide by 25
1A QA
1B QB
QC
R QD
3
4
ECO No.
Description of Change
Title Frequency Synthesiser
U606B
Fo_CHAN
74HC390
GND
Rev No.
Fo_MOD_2
13
11
10
9
Fo_CHAN_2
Fo_CHAN_2
Size:
EXT_REF_DIV
A3
Number:
Print Date: 20-Feb-2002
74HC390
Rev. Release Date:
GND
File:
2
5K6
GND
Fo_MOD_2
74HC393
U605B
1
R639
GND
Fo_MOD
13
12
R638
VCO_OUT
U606A
QA
1A QB
R QC
QD
TEMP
C651
VCO_OUT
74HC393
MMBT3904
R628
68R
TEMP
LM224
8
1
2
7
C642
100pF
GND
U605A
Q600
C641
A
R636
220R
GndVcc
Divide by 128
R635
560R
1
3
Vt
100nF
74HC393
100nF
2
Placed near X601
GND
C606
CHAN_PLL_SENSE
R647
10K
100nF
CHAN_VCO_OUT
MOD_VCO_OUT
BALANCE
CHAN_VCO_EN
2
C626 +
+5V
GND
CHAN_ADJ
BALANCE
8
4
GND
C647
GND
100nF
2
1
16
15
OUTA
OUTB
OUTC
OUTD
AGND
SIGGEN_ADSEL
SCLK
MOSI
PDE
100nF
-5V
4K7
2PORT_MOD
C
10pF
C652
U604
LMX2335L
CHAN_BIAS
R624
22K
R620
680R
100nF
GND
3
13
RESET
5
DGND
GND
C627
680R
12
CHAN_BIAS
5K6
R619
PDOUT_CHAN
VCO Section
vco.sch
MOD_IN
R623
3
14
Fin1
C648
U601
U608
4
3
Fin2
100nF
GND
SIGGEN_ADSEL
SCLK
MOSI
C616
1uF
10nF
5K6
Vref
100nF
GND
+5Q
TS971LT
DO1
Xout
C639
C617
100nF
10pF
R650
+5Q
B
C608
R649
10K
1
DO2
MOD_ADJ
5K6
RESET
11
9
10
Xin
VCC2
6
X601
CHAN_PLL_SEL
270K
R606
16
1uF
GND
C640
D601
R629
C649
10nF
MOD_PLL_SENSE
C645
C600
1
C619
GND
MMBV109 C636
10nF
C638
CHAN_PLL_SEL
U602
LMX2335L
MOD_PLL_SENSE
4K7
C634 +5Q
GND
1uF
GND
R648
GND
10nF
C629
C
R621
4K7
Fo_MOD
GND
C603
100K
NF
GND
8
+5Q
47R
R612
-5V
5
47R
R614
3u3F
12
R615
47R
VCC1
MOD_PLL_SEL
15
16
GND
MOD_PLL_SEL
**
+5V
100nF
FoLD
C618
GND
2
-5V
Fin1
+
D
5
1uF
LE
CLK
DATA
C612
R625
22K
1
GND
15pF
SCLK
MOSI
Fin2
C625
MOD_BIAS
100nF
-5V
2
R604
100K
100nF
C605 15pF
Xout
4
R607
5K6
C624
11
9
10
PDOUT_MOD
14
Vp1
C643
C620
GND
12M
C628
C613
*
220nF
GND
DO2
D600
220uH
V+
MMBV109
GND
L713
1K
MOD_BIAS
5K6
TS971LT
R617
R618
1K
3
DO1
Vp2
-5V
R637
5K6
Xin
Vp2
6
GND
2K2
GND
470pF
GND
GND
1
C611
R611
2
Vref
10nF
GND
13
TS971LT
100nF
1uF
10nF
27K
C610
15
27K
C609
1uF
13
3
C621
VCC1
1
2K2
C601
3
+5Q C604
47R C602
R603
GND
VCC2
5
D
R602
GND
R613
U607
4
R622
1
+5Q
R608
8
5
1
5
6
9154
23:40:44
Revision:
Sheet 6
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - siggen.sch
7
8
1
2
3
4
5
6
7
8
TP908
+5Q
12V
12V
Max output current is 1A
2
Vin
5
EN
C902 +
4
FB
GND
GND
BLM31P121SG
TP910
12V
L902
L901
33uH
1
Vout
DS5022P-224
3
+ C938
+ C903
C923
100uF
33uF
100nF
1
D907
3
6
470uF
MBRM140T3
U910
LM1117DTX-ADJ
4
Vin Vo
2
Vo
ADJ
U911
LM317LM
+10V
1
Vin
C926
+ C940
R925
220R
100nF
5
NC
33uF
Vout
Vout
Vout
Vout
NC
2
3
7
6
8
1
C931
C942
+
R927
220R
Vin
5
NC
+2.5V
Vout
Vout
Vout
Vout
NC
2
3
7
6
8
+2.5V
C944
+
33uF
R929
220R
100nF
33uF
4
GND
U912
LM317LM
+5Q
4
Tantalum, ESR <= 0.3 ohms
TP916
+2.5V
+10V
GND
GND
D
+5Q
TP909
L909
28V
+10V
ADJ
U907
LM2595S-12
ADJ
D
+10V
GND
GND
GND
R920
1K
R933
560R
C924
C932
C930
R930
220R
100nF
100nF
100nF
R935
120R
R921
560R
GND
12V
GND
D906
U908
LM2595S-12
C
-10V
-10V
-5V
TP914
-5V
-10V
DS5022P-334
100uF
-12V
L905
220uH
Tantalum, ESR <= 0.3 ohms
C901
U913
LM337LM
2
3
7
6
5
C920
100uF
-Vin
-Vin
-Vin
-Vin
NC
U914
LM337LM
-10V
-Vout
1
2
3
7
6
5
C941
NC
C927
8
R922
220R
33uF
-Vout
1
C943
NC
C933
8
R928
220R
2
3
7
6
5
100nF
33uF
-Vin
-Vin
-Vin
-Vin
NC
4
100nF
4
100nF
-Vin
-Vin
-Vin
-Vin
NC
U915
LM337LM
GND
-2.5V
-Vout
-2.5V
1
-2.5V
C945
NC
8
R931
220R
33uF
4
MBRM140T3
TP917
D910
GND
SM4004
+ C937
D908
ADJ
Vout
TP911
L903
1
ADJ
GND
GND
EN
R919
47K
4
3
6
47K
5
FB
+
100nF
Vin
+
C935 +
Low Impedance Type
35V, 10mm dia
470uF
R918
+
2
C915
-5V
ADJ
MBRM140T3
+
C
GND
GND
GND
GND
GND
R923
1K
R934
560R
C934
R932
220R
100nF
C925
C928
R924
560R
100nF
R936
120R
100nF
GND
TP913
Vref
B
B
GND
U909
LM2595S-5
Output Current is 750mA (max)
EN
FB
Tantalum, ESR <= 0.3 ohms
GND
TP915
5
+5V
L904
+5V
DS5022P-224
+10V
4
L906
100uF
+5D1
2K2
GND
Vref
3
GND
TS971LT
D911
C929
BLM31P121SG
Tantalum, ESR <= 0.3 ohms
Vref
1
R926
+ C939
MBRM140T3
GND
U906
+5V
1
D909
3
6
33uF
Vout
4
C904
2
+ C936
Vin
GND
GND
5
+5Q
TP912
12V
2
GND
+
100nF
L907
ZRC400F01
+5D2
BLM31P121SG
L908
3u3F
GND
+5D3
BLM31P121SG
A
A
Rev No.
ECO No.
Description of Change
Title Power Generation Section
Size:
A3
Number:
Print Date: 20-Feb-2002
Rev. Release Date:
File:
1
2
3
4
5
6
9154
23:40:01
Revision:
Sheet 9
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - power.sch
7
8
1
2
3
4
5
6
7
8
D
D
28V
L800
R813
C801
100R
C827 +
100nF
10uF
35V
+10V
L801
BLM31A601
R806
100R
BLM31A601
Murata Ferrite
SMD Choke
C806
R819
68R
C810 C811 +
C802
100uF
35V
100nF
L803
558nH
1n2F
Coilcraft Maxi Spring Coils
C
10nF
GND
R802
47R
R807
100R
C
GND
L804
558nH
GND
C823
R812
220R
100nF
L810
1uH
L805
120nH
C807
GND
L806
169nH
C824
L811
3u3H
100nF
GND
1
RF_in
C822
Q804
R808
Q805
C808
1p8F
1n2F
C812
1p8F
RF_out
4
GND
C825
3
L809
180nH
U800
220pF
2
MSA0311
R811
10nF
Q801
BFQ17
27R
10R
BFQ17
C804
C820
470pF
R804
10R
BFQ17
C816
33pF
C805
R805
10R
470pF
NF
R803
100R
GND
C813
C815
56pF
100pF
C821
D800
BAT54C
10pF
C814
47pF
C817
NF
C819
C809
68pF
NF
C803
GND
B
PWRCNTRL
220uH
R809
L808
3u3H
27R
C829
R816
10K
GND
100nF
L807
RF_out
C818
1nF
R810
10R
LOC_FWD_PWR
B
R823
4K7
GND
C826 +
100nF
3u3F
GND
GND
A
A
Rev No.
ECO No.
Description of Change
Title Broadband Power Amplifier
Size:
A3
Number:
Print Date: 20-Feb-2002
Rev. Release Date:
File:
1
2
3
4
5
6
9154
23:39:04
Revision:
Sheet 8
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - pa.sch
7
8
3
4
R237
47K
GND
1K
47
MMBT2369
44
R202
C203
10K
100nF
EXTAL
Q204
R238
1K
GND
C205
C204
C206
C207
100nF
100nF
100nF
100nF
100nF
XTAL
U204
PF6
PF3
PF2
PF1
LCD_RS
LCD_R/W
LCD_E
GND
74
71
70
69
MOD_PLL_SEL
LCD_RS
LCD_R/W
LCD_E
+5D3
MOD_PLL_SEL
+5D1
R220
10K
D
R219
10K
+5D2
R/W
14C88
U202C
9
14C88
8
TXDATA
TERM_EN2
TERM_EN1
Fo_MOD_2
Fo_CHAN_2
5
10
1
DSR
14C89A
3
2
C
U201A
4
CTS
TX_LED
U201B
6
5
C
10
DBGRX
14C89A
14C89A
9
C
U201C
13
RXDATA
U201D
11
12
C
3
DTR
14C89A
2
14C88
+5V
R232
R204
10K
R245
560R
R212
Q205 10K
MMBT3906
220R
R229
PTT_IN
R211
220R
+5D1
R206
2K2
R203
10K
R234
1K
BKGD
560R
ALARM_LED
Q206
RESET
GND
3u3F
A
BKGD_ISO
DEV_H_L
ALARM_LED
RESET
19
50
49
40
GND
SS
SCK
MOSI
MISO
TxD1
RxD1
TxD0
RxD0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
D7
D6
D5
D4
D3
D2
D1
D0
XIRQ
IRQ
BKGD
MODB
MODA
RESET
NC
NC
NC
NC
NC
S200
7914G
35
34
33
32
31
30
29
28
D7
D6
D5
D4
D3
D2
D1
D0
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
39
40
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
21
22
23
24
GND
RES
10
GND
U208
36 FRDY
22
24
29
CS
OE
WE
100nF
GND
GND
D7
D6
D5
D4
D3
D2
D1
D0
35
34
33
32
28
27
26
25
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
30
2
31
3
28
4
25
23
26
27
5
6
7
8
9
10
11
12
14C88
U202E
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
D7
D6
D5
D4
D3
D2
D1
D0
21
20
19
18
17
15
14
13
+5D3
D7
D6
D5
D4
D3
D2
D1
D0
C216
U201E
100nF
GND
B
14C89A
29F032
GND
K6T4008
GND
GND
A[0..21]
D[0..7]
MC68HC812A0
1
R222
1K
R226
180R
GND
A
R210
RESET
10K
Rev No.
Q200
MMBT3904
ECO No.
Size:
4
A3
Number:
Print Date: 20-Feb-2002
Rev. Release Date:
File:
3
4
5
Description of Change
Title Microprocessor
GND
MC33064D
2
1
100nF
GND
1
C215
100nF
GND
RY/BY
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C201
C211
100nF
L204
BLM31A601
Gnd
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C217
100nF
C
PWR_OK
U203
3
5
6
7
8
+5D3
18
17
16
13
12
11
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
CE
OE
WE
RESET
330R
2
R205
2K2
R233
22K
+5D3
R209
VCC
100nF
A21
A19
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
C219
+
RESET
PE7
PE4
PE3
MMBT3904
BAV99
C202
36
37
9
37
38
12
L203
BLM31A601
+5D2
C210
U207
CSP0
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
DEV_H_L
10K
10K
R228
10nF
PTT_uPHONE
TONE_INT
LOOP_DET
FILTER_OFF
INT
R221
D200 C209
104
103
102
101
100
99
98
97
10
9
8
7
PTT_uPHONE 6
TONE_INT
5
LOOP_DET
4
FILTER_OFF 3
+5D3
U202A
51
48
39
T/R_RELAY_H
SCLK
R230
SCK
120R
MOSI
SD
120R
PA_CS
R231
DBGTX_TTL
DBGRX_TTL
TXD_TTL
RXD_TTL
RTS_TTL
DTR_TTL
DSR_TTL
CTS_TTL
SCLK
MOSI
PA_CS
8
LCD_DB7
ECLK
TX_LED
R217
10K
12V
7
6
DBGTX
B
U202B
4
CSD
GND
14
13
14C88
112
111
110
109
108
107
106
105
+5D1
L202
BLM31A601
V+
11
RTS
EXT_REF_DIV
SPARE_SEL
CH_EN
GPS
TERM_EN2
TERM_EN1
Fo_MOD_2
Fo_CHAN_2
EXT_REF_DIV
SPARE_SEL
CH_EN
FWT
FRD
Gnd
12
LCD_DB7
LCD_DB6
LCD_DB5
LCD_DB4
LCD_DB3
LCD_DB2
LCD_DB1
LCD_DB0
7
U202D
-12V
GND
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
32
56R
LCD_DB7
LCD_DB6
LCD_DB5
LCD_DB4
LCD_DB3
LCD_DB2
LCD_DB1
LCD_DB0
+5D1
R218
10K
VCC
GND
2
19
5
16
6
15
9
12
O7
O6
O5
O4
O3
O2
O1
O0
GND
GPS-
I7
I6
I5
I4
I3
I2
I1
I0
GND
16
U212
R227
84
83
82
81
78
77
76
75
+5D1
NC
PWR_CNTRL_HIGH
CTCSS_SEL
CHAN_PLL_SEL
SIGGEN_ADSEL
CHAN_VCO_EN
LINEINP_ADSEL
LINEINP_DSEL
TEMP_LEVEL_IN
PWR_CNTRL_HIGH
CTCSS_SEL
CHAN_PLL_SEL
SIGGEN_ADSEL
CHAN_VCO_EN
3
18
4
17
7
14
8
13
100nF
74HC374
74HC138
31
LINEINP_ADSEL
LINEINP_DSEL
RAMRD
RAMWT
VCC
6
S2
S1
S0
GND
VCC
R215
120R
Vo
GND
3
2
1
11
D203
BZX84C3V3
K
NC
7
68
72
73
38
GND
29
3
4
Ve
R216
1K
CSO
CSD
CSP0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
C
E
GNDpll
GND
GND
GND
GND
GND
180R
C
NC
A
GND
GPS+
100nF
5
R214
1
2
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
10
C227
6N137
GND
FPSW1
FPSW2
FPSW3
LOOP/VOLTS_SEL
TONE_DEV_U/D
TONE_DEV_INC
EXT_TONE_SEL
VCC
8
+5TONE
GNDref
R208
22K
EN1
EN2A
EN2B
7
9
10
11
12
13
14
15
GND
BSS138
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
100nF
30
27
26
25
24
23
22
21
20
MOD_BIAS
LOC_FWD_PWR
T/R_RELAY_H
6
4
5
45
15
41
80
96
1
Q201
16
FRDY
FPSW1
FPSW2
FPSW3
LOOP/VOLTS_SEL
TONE_DEV_U/D
TONE_DEV_INC
EXT_TONE_SEL
T/R_RELAY
C208
U205
VCC
LINE_LEVEL_SENSE
CHAN_BIAS
LINE_LEVEL_IN
MOD_BIAS
LOC_FWD_PWR
LINE_LEVEL_SENSE
CHAN_BIAS
11
1
BLM31A601
GND
GND
10K
U209
+5D1
L205
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
8
VIN_SENSE
R201
SM4004
94
93
92
91
90
89
88
87
86
D202
CHAN_PLL_SENSE
MOD_PLL_SENSE
C212
CS0
XFC
12V
CHAN_PLL_SENSE
MOD_PLL_SENSE
R223
10K
100nF
GND
46
C226
R225
10K
14
100nF
C224
100nF
47K
R239
R224
10K
V+
R207
68K
9
C221
R213
1M
+5LCD
20
Q202
MMBF5484
28V
U403C
Q203
MMBT2369
+5D1
Vref
C225
R243
220R
R242
+5D3
8
VCC
11
+5D2
7
GND
TEMP 10
TEMP
10R
R240
10K
4K7
100nF
X200
14M7456
DG411
D
C220
47R
+5D2
6
V-
C214
100nF
GND
LINE_LEVEL_IN
R236
22K
R235
220uH
R244
43
14
42
79
95
2
L200
100nF
R241
5
Vddpll
VCC
VCC
VCC
VCC
VCC
C222
85
2
Vref
1
6
9154
23:32:55
Revision:
Sheet 2
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - micro.sch
7
8
1
2
3
4
5
6
7
8
JP12
uPHONE_IN
AUDIO PROCESSING SECTION
audio.sch
1
2
3
4
PTT_uPHONE
MICROPROCESSOR CONTROL SECTION
micro.sch
LCD_BIAS
LCD_BIAS
4 HEADER
GND
FILTER_OFF
+5D3
FILTER_OFF
PTT_uPHONE
LINE_LEVEL_SENSE
CTCSS_SEL
SCLK
MOSI
TONE_INT
28V
L100
BLM31P121SG
P3
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
C
C100
NFA31CC102
C101
NFA31CC102
C102
NFA31CC102
GPS+
GPS-
LINE_I/P1
L2+
L2TONE+
TONE-
C103
RESET
RESET
PWR_CNTRL_HIGH
L1-
D103
AMBER
Tx Data
D104
GREEN
PWR_OK
POWER OK
RESET
FPSW1
SW1
C&K_PB
DEV_H_L
TONE_DEV_U/D
TONE_DEV_U/D
TONE_DEV_INC
TONE_DEV_INC
LOOP_DET
PWRCNTRL
MOSI
CH_EN
SPARE_SEL
FPSW3
C
T/R_RELAY
PA_CS
MOD_IN
GPS+
GPSCH_EN
SPARE_SEL
SCLK
MOSI
RESET
VCO_out
GND
B
RESET
PA_CS
GPS+
GPSCH_EN
SPARE_SEL
GND
Debug/Monitor Port
+5LCD L102
JP2
Fo_MOD_2
Fo_CHAN_2
EXT_REF_DIV
TEMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
L104
LCD_BIAS
BLM31A601
LCD_RS
LCD_R/W
LCD_E
LCD_DB0
LCD_DB1
LCD_DB2
LCD_DB3
LCD_DB4
LCD_DB5
LCD_DB6
LCD_DB7
+5D1
BLM31A601
GND
EXT_REF_IN
BNC-2
DBGTX
DBGRX
DBGTX
DBGRX
MOD_PLL_SEL
MOD_BIAS
MOD_PLL_SENSE
CHAN_PLL_SEL
CHAN_BIAS
CHAN_PLL_SENSE
Fo_MOD_2
Fo_CHAN_2
EXT_REF_DIV
Fo_MOD_2
Fo_CHAN_2
EXT_REF_DIV
J4
1
2
3
4
5
6
7
8
9
10
T/R_RELAY
SIGGEN_ADSEL
MOD_PLL_SEL
MOD_BIAS
MOD_PLL_SENSE
CHAN_PLL_SEL
CHAN_BIAS
CHAN_PLL_SENSE
MOD_PLL_SEL
MOD_BIAS
MOD_PLL_SENSE
CHAN_PLL_SEL
CHAN_BIAS
CHAN_PLL_SENSE
RF_out
PWRCNTRL
LOC_FWD_PWR
BKGD
BKGD
CON10
SIGGEN_ADSEL
SIGGEN_ADSEL
RF_in
JP3
PTT_IN
T/R_RELAY
T/R_RELAY
POWER AMPLIFIER
pa.sch
4K7
+5D3
RF SIGNAL GENERATOR
siggen.sch
+5V
RV100
100K
R105
LINE_LEVEL_IN
MOD_OUT
L101
Vref
GND
LOOP_DET
PWRCNTRL
GND
J1
RED
FPSW2
BLM31A601
BNC Right Angle - Low Profile
D102
L1+
NFA31CC102
GND
R104
270R
PWR_CNTRL_HIGH
PTT_IN
Vref
R103
180R
TX_LED
TERM_EN2
TERM_EN1
DEV_H_L
L1+
L1-
12V
DB25RA/F
L2+
L2-
R102
4K7
ALARM_LED
LINEINP_DSEL
LINEINP_ADSEL
TERM_EN2
TERM_EN1
R101
4K7
ALARM
EXT_TONE_SEL
LOOP/VOLTS_SEL
LINEINP_DSEL
LINEINP_ADSEL
uPHONE_IN
T/R_RELAY
HiZ+
HiZTONE+
TONELINE_I/P4
CTCSS_SEL
SCLK
MOSI
TONE_INT
SCLK
MOSI
EXT_TONE_SEL
LOOP/VOLTS_SEL
SCLK
PA_CS
PTT_IN
R100
4K7
2
28V
D
LINE_LEVEL_SENSE
3 2
TP102
3
D
HEADER 14
B
TEMP
GND
CHAN_VCO_EN
5
9
4
8
3
7
2
6
1
CHAN_VCO_EN
LOC_FWD_PWR
RTS
RXDATA
CTS
TXDATA
DTR
DSR
RTS
RXDATA
CTS
TXDATA
DTR
DSR
LOC_FWD_PWR
SG
RI
P1
POWER SECTION
power.sch
GND
NB: connector signals reversed
so that straight through cable can be used to PC
12V
12V
+10V
28V
+10V
+5V
+5Q
+5V
Vref
+5Q
28V
A
+2.5V
Vref
A
Rev No.
+2.5V
GND
Size:
-5V
-2.5V
-5V
File:
5
Number:
Rev. Release Date:
-10V
4
A3
Print Date: 20-Feb-2002
71
3
Description of Change
Title T50 Master Schematic
-10V
2
ECO No.
-2.5V
GND
1
DTR
CTS
TXD
RTS
RXD
DSR
DCD
DB9
6
9154
23:28:58
Revision:
Sheet 1
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - Master.sch
7
8
1
2
3
4
5
6
+2.5V
8
TEST_DEV
1
DEV_H_L
7
R420
120K
LM13700
R415
560R
C418
100nF
C402 (NPO)
6
7
10K
1uF
R423
10K
U405B
R457
8
6
R414
560R
C423
5
-10V
GND
6
3
U404B
270K
R410
47K
-10V
R442
4K7
R447
R418
5k6
47K
R458
R427
47K
GND
2
C428
16
C403 (NPO)
10
3n3F
GND
-10V
100nF
GND
R430
47K
U403E
DG411
5
GND
100nF
PRE_EMPH1
-10V
GND
56K
+5D1
U400D
C407
C404
+
3n3F
12
15
C406
100nF
GND
-10V
100nF
-10V
100nF
R433
10nF
4K7
U403D
EN_uPHONE
C416
100nF
-10V
12
10K
C426
+10V
13
GND
D403
LM224
R453
PWR_CNTRL_HIGH
270K
+2.5V
GND
R467
4K7
R436
14
100nF
R451
47K
LM224
GND
GND
U404E
DG411
GND
DG411
C
C412
GND
14
270R
C401
C411
100nF
LM224
(NPO)
13
+5V +10V
U400E
GND
-10V
-2.5V
GND
C415
R404
R401
330R
33uF
C405
C410
100nF
R459
4K7
16
R400
C409
4K7
R440
U404C 4K7
R411
47K
+5V
C400
GND
13
270K
D400
BAV99
uPHONE_IN
R432
R460
14
11
9
+10dBm max input => |Vin| < 3.46V
For peak distortion of 0.3%
max input to transimpedance
amplifier is 100mV => need 25dB attenuation
NB: Is max (3.46/18) is less than Id/2 (0.5ma)
DG411
-10V
4
12
R409
120K
R444
4K7
+10V
V+
R424
10K
GND
+5V +10V
U405D
LM224
R445
47K
11
C
R429
22K
FLAT1
LM224
AUDIO_OUT
D401
-10V
GND
10
AUDIO_OUT
BAV99
-10V
U404D
8
8
9
GND
14
22K
9
10K
1uF
15
13
U402D
R416
560R
R417
560R
U405C
R462
9
DG411
R426
V+
C425
R422
120K
LM13700
R456
47K
V-
13
120K
10
12
12
B
GND VL
15
R438
47K
U407C
LM224
10
4K7
LM224
R463
VCC
R443
7
5
R437
47K
4
U402B
14
22K
-10V
16
LINE_IN1
R403
PRE_EMPH2
LINE1_GAIN
10K
LINE_IN1
R435
1K
-10V
6
100K
1uF
BAV99
U407B
R465
1
LM224
+10V
D402
270K
3
R407
R464
U407A
4K7
GND
5k6
4K7
2
R439
4K7
+2.5V
R434
1
R431
D
R449
6
DG411
3n3F
LM224
7
U405A
LM224
DG411
7
R461
120K
GND
U403B
-2.5V
13
4
FLAT2
120K
U402C
7
V+
A
V-
2
12
VCC
U402A
5
GND VL
3
22K
HIGH_GAIN
R428
22K
U404A
5
1
22K
LINE_INP
V-
LINE_IN2
R452
10k
3
R450
10K
DG411
2
1
LINE_IN2
LINE2_GAIN
R448
3
DG411
R425
GND
R402
U403A
2
10k
8
D
R406
10K
11
C417
100nF
Q402
MMBT3906
R446
DEV_H_L
4
Io = Is(2Iabc/Id) : Io= Vo/Rl ; Is = Vs/Rs; Iabc = Vabc/Rabc; Id = Vd/Rd
=> Vo/Vs = 2*Rl*Rd*Vabc/(Rs*Rabc*Vd) = Vabc*0.11
=> +10dBm peak voltage is transformed to 1.57V(max) to 6.15mV(min) (8 bit DAC, 4V reference)
8
+10V
BAV99
14
U407D
PWRCNTRL
C413
GND
R413
100nF GND
PWR_CNTRL_HIGH
V+
V-
LM224
Vref
V+
R455
U405E
B
V-
PWR_CNTRL_HIGH
4
GND 100nF
4
-10V
U407E
R408
5K6
10K
B
LM224
C408
GND
C427
GND 100nF
11
R421
22K
11
GND
R419
22K
100nF
+5V
1K
-10V
C414
LM224
R405
5
5K6
100nF GND
C419
R454
6
100nF
14
Din
7
6
9
10
11
8
A
PDE
CLR
LDAC
CS
SCLK
Din
9
OUTA
OUTB
OUTC
OUTD
GND
LCD_BIAS_RAW
Dout
UPO
2
1
16
15
10
U400C
8
LINE2_GAIN
8
4
A
Rev No.
14
12
ECO No.
EN_uPHONE
Size:
A3
Number:
Print Date: 20-Feb-2002
File:
3
Description of Change
Title Line Input Processing Section
GND
2
2K2
Q400
MMBT3906
Rev. Release Date:
1
R466
LM224
MAX534
MOSI
SCLK
RESET
LINEINP_ADSEL
R412 10K
10K
+5V
Vref
5
74HC595A
LINEINP_ADSEL
LINE1_GAIN
PWR_CNTRL_RAW
U406
GND
AUDIO_DEV_U/D
AUDIO_DEV_INC
Q401
MMBT3906
LCD_BIAS
3
13
100nF
AGND
MOSI
MOSI
SRCLR
SRCK
Dout
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
7
LM224
C422
9
7
PRE_EMPH2
6
FLAT2
5
PRE_EMPH1
4
FLAT1
3
TEST_DEV
2
HIGH_GAIN
1 AUDIO_DEV_U/D
15 AUDIO_DEV_INC
VCC
10
11
VCC
RESET
SCLK
G
RCK
5
DGND
RESET
SCLK
LINEINP_DEN
U401
GND
LINEINP_DEN
13
12
+5V
16
GND
U400B
7
U302B
6
4
5
6
9154
23:31:21
Revision:
Sheet 4
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - lineinp.sch
7
8
1
2
3
4
5
6
TERM_EN2
7
8
+5V
D307
BAT54C
TERM_EN1
R317
uPHONE_IN
1K
R324
LINE_LEVEL_SENSE
LINE_IN2
TP300
AUDIO_XFRMR
F300
R300
T300
L2+
120mA
3u3F
27R
U301B
D300
1.5KE11CA
7
*
R301
C300
22uF
GND
TERM_EN2
LINE_IN1
PWRCNTRL
RESET
F301
R302
120mA
27R
L1-
GND
R303
DG411
GND
TERM_EN1
R310
560R
9
27R
PWRCNTRL
LCD_BIAS
LCD_BIAS
DEV_H_L
AUDIO_DEV_INC
AUDIO_DEV_U/D
LINEINP_ADSEL
LINEINP_DEN
SCLK
MOSI AUDIO_OUT
11
L1+
PWRCNTRL
LCD_BIAS
PWR_CNTRL_HIGH
U301C
10
D
LINE_INP
LINE_INP
R309
560R
LINE_IN1
TP301
AUDIO_XFRMR
T301
D305
BAV99
GND
LINE_IN2
DG411
8
27R
R312
22K
uPHONE_IN
6
L2-
AUDIO_DEV_INC
AUDIO_DEV_U/D
C312
D301
12V
TP302
1uF
GND
8
6
R306
3
5
*
C301
22uF
2
1.5KE11CA
1k
10R
AUDIO_OUT
R313
22K
D306
RL300
SM4004
C
R315
R318
R319
R320
22K
120K
120K
120K
R322
R323
C
R305
330R
7
Q300
BSS138
GND
U302A
2
R321
1
3
R311
22K
GND
R307
LOOP/VOLTS_SEL
4K7
D303
BAV99
GND
+5D3
D304
2
3
BAV99
68K
C302
2n2F
(NPO)
68K
C305
10nF
(NPO)
12
13
A
B
K
C
NC
E
R308
2K2
6
5
8
GND
TONE GENERATION SECTION
tonetx.sch
RESET
22K
-10V
-10V
MMBT3906
AUDIO_DEV_INC
R328
U303
Q301
10K
TP303
2
INC
U/D
R334
NF
1
GND
-2.5V
MAX5161L
B
GND
3
TONE_OUT
R333
1K
5
4
DEV_H_L
LINEINP_ADSEL
LINEINP_DSEL
R327
47K
R335
22K
+2.5V
TONE_OUT
B
MOD_OUT
+2.5V
LOOP_DET
R330
47K
PWR_CNTRL_HIGH
MOD_OUT
R336
GND
R326
47K
LOOP_DET
4
LM224
9
LM224
GND
4N32
+2.5V
FILTER_OFF
FILTER_OFF
CTCSS_SEL
SCLK
MOSI
AUDIO_DEV_U/D
CTCSS_SEL
SCLK
MOSI
MMBT3906
R329
10K
-2.5V
Q302
F302
TONE+
TONEP+
TONE_INT
R331
47K
TONE_INT
120mA
1.5KE11CA
D302
-2.5V
TONEP-
A
100nF
GND
100nF
GND
13
C309
V-
U302E
LM224
* C300, and C301 are Bipolar electrolytic capacitors
C307
V+
TONE_DEV_U/D
TONE_DEV_INC
C310
100nF
GND
V-
TONE_DEV_U/D
TONE_DEV_INC
+10V
12
EXT_TONE_SEL
V+
EXT_TONE_SEL
+5V
GND VL
+10V
4
TONE-
A
-10V
C308
4
Rev No.
5
11
U301E
DG411
GND
-10V
Size:
C311
GND
File:
4
5
Number:
Rev. Release Date:
GND
3
A3
Print Date: 20-Feb-2002
100nF
2
ECO No.
Description of Change
Title Audio Processing Section
100nF
1
10
68K
120pF (NPO)
GND
R314
10K
R332
14
C306
TP305
MOD_OUT
U302C
-10V
U300
1
R325
47K
R316
10K
TONE_OUT
LOOP/VOLTS_SEL
68K
LM224
U302D
6
R304
330R
4
1
MR62-12
VDD
D
+ C304
Line Input Processing Section
lineinp.sch
6
9154
23:30:34
Revision:
Sheet 3
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - audio.sch
7
8
1
2
3
4
5
6
7
8
+10V
Q707
MMBT3904
R716
R703
120R
C748
47R
10nF
GND
10nF
C723
3u3F
GND
C772
GND
L708
330nH
4
3
MOD_VCO_OUT
2
10nF
MSA0611
C708
GND
R733
Q704
MMBFJ309
C732
GND
330R
22pF
+10V
GND
R701
R740
47R
120R
U702
1
3
C770
C709
C715
GND
GND
L709
C704
22pF
MSA0611
R737
D700
BAT17
1K
C733
3
10nF
100nF
GND
2
10nF
R729
-5V
100nF
100nF
C726
10nF
C727
3p9F
L722
220nH
L721
270nH
L720
220nH
2
2
LO
IF
RF
10nF
C765
15pF
MSA0611
C755
C757
C758
C759
47pF
120pF
120pF
47pF
220R
100nF
C776
7
120R
C703
C774
R723
8
100nF
U704C
L710
330nH
L704
L705
27nH
47nH
27nH
C717
C731
C729
3p9F
15pF
15pF
R742
820R
C735
R724
56R
GND
R715
10K
GND
C707
U706
3
C756
3p9F
2PORT_MOD
22K
4
R720
100K
-10V
R727
2
A
1
R714
56R MSA0611
GND
3
5
22pF
100nF
10K
U704A
LM13700
C716
22pF
C
VCC
3p9F
3
5
4
1
-5V
GND
L703
BALANCE
+10V
+10V
R704
100nF
56pF
BALANCE
TS971LT
GND
GND
C771
6
MMBT3906
6
3
GND
C763
150pF
15pF
GND
R707
MX700
MIXER
3
R725
22K
10R
C734
4
U700
1
C728
GND
GND
GND
4
GND
C714
L702
27nH
2
L725
3u3H
C749
L701
39nH
1
Q700
GND
2
L700
27nH
100nF
U707
4
1uF
C745
R735
22K
C713
2K2
C752
1uF
C700
T/R_RELAY
+5Q
C719
10K
C760
C743
4K7
+10V
R711
100K
Q701
BSS138
R734
120R
R710
R722
22K
R744
MOD_VCO_EN
220R
GND
GND
MSA0311
GND
R700
Vref
C762
GND
L724
330nH
GND
22pF
R706
100nF
12pF
1
C718
U701
C705
Q706
BSS138
D702
NF
L726
82nH
10nF
MOD_PLL_IN
D701
MMBV109
A04T
R709
10K
L712
220nH
22pF
L716
12n5H
C739
GND
330nH
10nF
5p6F
22pF
4
100nF
100nF
D
C750
C737
100nF
4
U705
1
C702
VCO_OUT
10K
+
100nF
GND
C
C754
100nF
100nF
L706
330nH
100nF
D
R738
220R
C722
5
220R
11
R730
120R C721
L714
330nH
1
R718
R717
C724
C736
2
+10V
+10V
10pF
R731
560R
C775
R743
560R
100nF
GND
R736
1K
GND
-10V
+10V
C730
U704B
LM13700
120R
12
100nF
B
GND
-10V
GND
R745
220R
15
B
R719
C720
10nF
14
C706
R705
220R
+10V
47R
16
R702
Q702
MMBT3904
R726
L715
330nH
10nF
C753
+
10K
3u3F
C712
GND
100nF
B
13
C710
GND
C751
C738
100nF
L711
330nH
GND
C740
GND
4
GND
C701
U703
1
3
10nF
MSA0611
22pF
2
CHAN_VCO_OUT
C761
10nF
4p7F
R741
D703
BAT17
C741
4K7
C764
D704
33pF
C747
L719
18n5H
10nF
A05T
R739
L707
NF
NF
C725
C773
R713
100K
10K
GND
CHAN_PLL_IN
D705
MMBV109
C711
NF
6p8F
L717
100nH
Q705
MMBFJ309
L723
330nH
1uF
10nF
GND
GND
-5V
100nF
GND
GND
C742
CHAN_VCO_EN
CHAN_VCO_EN
Q703
BSS138
R708
4K7
C746
R732
22K
10nF
GND
10nF
M1
GND
A
A
Rev No.
RFSCREEN1
ECO No.
Description of Change
Title Voltage Controlled Oscillators
GND
Size:
A3
Number:
Print Date: 20-Feb-2002
Rev. Release Date:
File:
1
2
3
4
5
6
9154
23:42:46
Revision:
Sheet 7
Originator:
of
9
B
RF Technology Pty Ltd
Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Australia
C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - vco.sch
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