Download Audio Control FOUR.1i Specifications

TLV320AIC34
www.ti.com
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
MCLK_x
BCLK_x
GPIO2_x
PLL_CLKIN
CLKDIV_CLKIN
CLKDIV_IN
Q = 2, 3,….., 16, 17
PLL_IN
(K ´ R) / P
2/Q
CLKDIV_OUT
K = J.D
J = 1, 2, 3, ...., 62, 63
D = 0000, 0001, ...., 9998, 9999
R = 1, 2, 3, 4, ...., 15, 16
P = 1, 2, ...., 7, 8
PLL_OUT
1/8
PLLDIV_OUT
CLKMUX_OUT
CODEC_CLKIN
CODEC_CLK = 256 ´ fS(ref)
CLKOUT_IN
M = 1, 2, 4, 8
N = 2, 3, ..., 16, 17
2 / (N ´ M)
CLKOUT
GPIO1_x
CODEC
DAC fS
ADC fS
WCLK = fS(ref) /NCODEC
CODEC fS = DAC fS = ADC fS
Set NCODEC = NADC = NDAC = 1, 1.5, 2, ...., 5.5, 6
DAC DRA => NDAC = 0.5
ADC DRA => NADC = 0.5
B0153-02
Figure 25. Audio Clock Generation Processing
The part can accept an MCLK_x input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK_x or
GPIO2_x inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not
powered up. The user can supply a separate clock to GPIO2_x, route this through the PLL, with the resulting
output clock driven out GPIO1_x, for use by other devices in the system.
A primary concern is proper operation of the codec at various sample rates with the limited MCLK_x frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK_x inputs, with particular
focus paid to the standard MCLK_x rates already widely used.
When the PLL is disabled,
fS(ref) = CLKDIV_IN / (128 × Q)
Where Q = 2, 3, …, 17
CLKDIV_IN can be MCLK_x, BCLK_x, or GPIO2_x, selected by page 0, register 102, bits D7–D6.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC34
31